JP2994941B2 - Pulse width modulation signal output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation signal output circuit for converting an analog signal into a pulse width modulation signal having a modulation degree of 1/3 to 2/3.

[0002]

2. Description of the Related Art In recent years, various data including video signals and the like have been transmitted by pulse width modulation signals using general telephone lines. In order to use a general telephone line, the occupied band of the pulse width modulation signal is preferably narrow,
It is known that the occupied band is narrowest when the modulation factor is 1/2. Therefore, a pulse width modulation signal whose modulation degree changes within a predetermined range around the modulation degree 1/2 is generally used.

[0003]

A conventional circuit for converting to a pulse width modulation signal is to output a pulse width modulation signal having a modulation factor corresponding to an analog signal as an input signal. Therefore, even if the analog signal has an abnormally high or low voltage value and has an error, a pulse width modulation signal with an abnormally high or low modulation factor is output in response to the error. Therefore, the modulation degree of the output pulse width modulation signal is not necessarily limited to a predetermined range, and the occupied band may be widened.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and has been made in consideration of the above-mentioned circumstances. In order to convert an analog signal into a pulse width modulation signal, a pulse having a modulation degree of 1/3 to 2/3 is used. An object of the present invention is to provide a width modulation signal output circuit.

[0005]

To achieve the above object, a pulse width modulation signal output circuit according to the present invention converts an analog signal into a pulse width modulation signal having a modulation factor of 1/3 to 2/3. A pulse width modulation sum signal output circuit, wherein a clock pulse having a frequency three times the frequency of a transmission signal is supplied to a ternary ring counter, and one digit of the output is supplied to a base of a first NPN transistor whose emitter is grounded. Given to 2
The digit output is given to the emitter of the PNP transistor, the three digit output is given to the base of the second NPN transistor whose voltage is applied to the collector, and the analog signal is sent to the PN transistor.
A collector of the PNP transistor, a collector of the first NPN transistor, an emitter of the second NPN transistor, one end of a capacitor, and an input end of a comparison inverting circuit; An end is grounded, and the pulse width modulation signal is output from an output end of the comparison inverting circuit.

[0006]

The period of one transmission signal is divided into three by the output of the ternary ring counter, and the pulse width is increased or decreased according to the voltage of the analog signal within the period of the second division.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram of one embodiment of a pulse width modulation signal output circuit according to the present invention, and FIG. 2 is a time chart illustrating the operation of the circuit of FIG.

In FIG. 1, a clock pulse having a frequency three times the frequency of a transmission signal is supplied to a ternary ring counter 10.
To the clock input terminal 12. The one-digit output terminal of the ring counter 10 is connected to a first NP through a resistor 14.
The output terminal of two digits is connected to the emitter of the PNP transistor 18, and the output terminal of three digits is connected to the base of the second NPN transistor 20. A modulation signal input terminal 22 to which an analog signal as a modulation signal is supplied is connected to the PNP transistor 1.
8 is connected to the base of the second NPN transistor 20 via the diode 24 in the reverse direction. The collector of the PNP transistor 18, the collector of the first NPN transistor 16, and the second NP
The emitter of the N-transistor 20, one end of the capacitor 26, and the input terminal of a Schmitt inverter 28 as a comparison inverting circuit are connected together. And again, the capacitor 26
Is grounded, the base of the first NPN transistor 16 is grounded via the resistor 30, and a voltage of, for example, +5 V is applied to the collector of the second NPN transistor 20. Further, the output terminal of the Schmitt inverter 28 is connected to the output terminal 32.

The operation of such a configuration will be described with reference to FIG. When the clock pulse shown in FIG. 2A is applied to the clock input terminal 12, the one-digit output of the ring counter 10 changes the period of one transmission signal to three as shown in FIG.
It becomes "H" in the first section and "L" in the second and third sections. As shown in FIG. 2C, the two-digit output becomes "H" in the second section and "L" in the first and third sections. Further, as shown in FIG. 2D, the output of three digits becomes "H" in the third section and "L" in the first and second sections.
Therefore, in the first section, the first NPN transistor 16
Is conducted, the capacitor 26 is rapidly discharged, and its terminal voltage becomes 0V. In the third section, the second NP
The N transistor 20 conducts, the capacitor 26 is charged rapidly, and its terminal voltage becomes, for example, an operating voltage of 5V. The output voltage of each digit of the ring counter 10 is 5 V of the operating voltage. In the second section, the first and second NPN transistors 16 and 20 are both non-conductive, and the emitter of the PNP transistor 18 is applied with, for example, a two-digit output of the 5 V ring counter 10. The capacitor 26 is gradually charged in accordance with the voltage of the analog signal applied to the modulation signal input terminal 22.
If the voltage of the analog signal is at the center of the fluctuation range, FIG.
As shown in (e), the terminal voltage of the capacitor 26 becomes the second voltage.
It is charged to exceed the threshold v _s of the Schmitt inverter 28 in a period the center of the segment. If the voltage of the analog signal is low, the rate of increase of the terminal voltage of the capacitor 26 is large as shown in FIG. 2E, and if the voltage of the analog signal is high, the rate of increase is small as shown in FIG. Therefore, the terminal voltage of the capacitor 26 changes the time to exceed the threshold v _s of the Schmitt inverter 28 in accordance with the voltage of the analog signal. From the Schmitt inverter 28, a pulse width modulation signal as shown in FIG. Here, if the center of the voltage fluctuation range of the analog signal, the pulse width modulation signal w ₁ is the degree of modulation is 1/2, the lower the voltage of the analog signal, the pulse width modulation signal w ₂ is modulated The degree is 1/3 or more, but lower than 1/2, and if the voltage of the analog signal is high,
The pulse width modulation signal _{W 3} being Although modulation degree is less than 2/3 higher than 1/2. Then, even if the voltage of the analog signal is abnormally low, the modulation degree of the pulse width modulation signal output becomes 1/3, and the modulation degree does not become lower than this, and conversely, the pulse width modulation signal is output even if it is abnormally high. The modulation degree of the signal is 2/3, and does not become higher.

Therefore, regardless of the voltage of the analog signal, the output pulse width modulation signal has a modulation degree of 1/3 to 2/3. Therefore, it is preferable to transmit such a pulse width modulated signal through a general telephone line because the occupied band is narrow.

In the above embodiment, the comparison inverting circuit is not limited to the Schmitt inverter 28, but may be any circuit having a comparing action and an action of inverting its output.

[0012]

As described above, since the pulse width modulation signal output circuit of the present invention is constituted, the following special effects can be obtained.

In the pulse width modulation signal output circuit according to the present invention, the modulation degree of the output pulse width modulation signal is from 1/3 to 1/3.
When the analog signal is abnormally low or high voltage, the modulation degree is set to 1/3 or 2/3.
A pulse width modulation signal having a narrow occupied band is output. Thus, a pulse width modulated signal suitable for transmission over a general telephone line or the like can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a pulse width modulation signal output circuit according to the present invention.

FIG. 2 is a time chart illustrating the operation of the circuit in FIG. 1;

[Explanation of symbols]

 10 ternary ring counter 16 first NPN transistor 18 PNP transistor 20 second NPN transistor 22 modulation signal input terminal 26 capacitor 28 Schmitt inverter 32 output terminal

Claims (1)

(57) [Claims] An analog signal having a modulation degree of 1/3 to 2/3.
A pulse width modulation signal output circuit for converting a clock pulse having a frequency three times as high as the frequency of a transmission signal to a ternary ring counter, and a one-digit output of which is grounded at an emitter. The two-digit output is given to the base of the first NPN transistor, the two-digit output is given to the emitter of the PNP transistor, and the three-digit output is given to the base of the second NPN transistor whose voltage is applied to the collector. Applied to the base of the PNP transistor,
A collector of the PNP transistor and the first NPN
A collector of the transistor, an emitter of the second NPN transistor, one end of a capacitor and an input terminal of a comparison inverting circuit are connected, the other end of the capacitor is grounded, and the pulse width modulation signal is output from an output terminal of the comparing and inverting circuit. And a pulse width modulation signal output circuit.