JPH07201822A - Dry etching device - Google Patents
Dry etching deviceInfo
- Publication number
- JPH07201822A JPH07201822A JP33849693A JP33849693A JPH07201822A JP H07201822 A JPH07201822 A JP H07201822A JP 33849693 A JP33849693 A JP 33849693A JP 33849693 A JP33849693 A JP 33849693A JP H07201822 A JPH07201822 A JP H07201822A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- lower electrode
- semiconductor substrate
- dry etching
- upper electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- ing And Chemical Polishing (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体製造用のドライエ
ッチング装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching apparatus for semiconductor manufacturing.
【0002】[0002]
【従来の技術】従来のドライエッチング装置の構成図を
図5に示す。従来のドライエッチング装置は、半導体基
板6のエッチング処理を行う真空容器11と、その内部
に設けられる上部電極5および下部電極7と、ガス源1
からの流量を制御するガス流量制御部2と、上部および
下部電極用の温度制御部3,4と、真空容器11内の圧
力を制御する圧力制御部9と、排気系10とで構成され
る。2. Description of the Related Art FIG. 5 shows a block diagram of a conventional dry etching apparatus. The conventional dry etching apparatus includes a vacuum container 11 for etching a semiconductor substrate 6, an upper electrode 5 and a lower electrode 7 provided therein, and a gas source 1.
A gas flow rate control unit 2 for controlling the flow rate from the chamber, temperature control units 3, 4 for the upper and lower electrodes, a pressure control unit 9 for controlling the pressure in the vacuum container 11, and an exhaust system 10. .
【0003】真空容器11ではガス流量制御部2にて一
定流量に制御された種々のエッチングガスが混合されて
いる。それと同時に真空容器11は圧力制御部9によっ
て一定圧力に保たれる。一定応力に保たれた真空容器1
1内に一定流量のドライエッチングガスを流しながら上
部電極5と下部電極7間に高周波電圧を印加することに
よりプラズマを発生させ、下部電極7上の半導体基板6
をエッチングする。In the vacuum container 11, various etching gases whose gas flow rate control unit 2 has controlled the constant flow rate are mixed. At the same time, the vacuum container 11 is kept at a constant pressure by the pressure control unit 9. Vacuum container 1 kept at constant stress
A high-frequency voltage is applied between the upper electrode 5 and the lower electrode 7 while a dry etching gas having a constant flow rate is flown in the plasma generating chamber 1 to generate plasma, and the semiconductor substrate 6 on the lower electrode 7 is
To etch.
【0004】下部電極7上の半導体基板6のエッチング
特性(エッチングの速さ、エッチングの速さの基板上の
面内分布、エッチングの膜質による選択性、エッチング
形状など)は、真空容器11内の圧力,エッチングガス
の流量及びその流量比,高周波電圧,上部電極5及び下
部電極7の温度に影響されるため、エッチングされる膜
質によってこれらを任意に変更することで最も適したエ
ッチング特性を得ることを可能としている。The etching characteristics of the semiconductor substrate 6 on the lower electrode 7 (etching speed, in-plane distribution of etching speed on the substrate, selectivity by etching film quality, etching shape, etc.) It is affected by the pressure, the flow rate of the etching gas and its flow rate, the high frequency voltage, and the temperature of the upper electrode 5 and the lower electrode 7, so that the most suitable etching characteristics can be obtained by arbitrarily changing these depending on the quality of the film to be etched. Is possible.
【0005】[0005]
【発明が解決しようとする課題】この従来のドライエッ
チング装置では、上部電極5及び下部電極7における一
部の温度を電極全体の温度として制御しているため、温
度制御を部分的に行うことができなかった。従って、電
極面内で温度分布に差がある場合にはエッチング特性、
特にエッチングの速さの半導体基板面内での分布(以下
エッチングの均一性と称す)が悪くなり、更にエッチン
グ形状に面内差ができるという問題点があった。In this conventional dry etching apparatus, since the temperature of a part of the upper electrode 5 and the lower electrode 7 is controlled as the temperature of the entire electrode, the temperature control can be partially performed. could not. Therefore, when there is a difference in the temperature distribution within the electrode surface, the etching characteristics,
In particular, there is a problem that the distribution of the etching speed within the surface of the semiconductor substrate (hereinafter referred to as etching uniformity) is deteriorated and the etching shape may have an in-plane difference.
【0006】[0006]
【課題を解決するための手段】本発明のドライエッチン
グ装置は、それぞれ独立して温度制御することのできる
複数のブロックに分割された上部電極および下部電極と
を備えている。A dry etching apparatus according to the present invention comprises an upper electrode and a lower electrode divided into a plurality of blocks whose temperatures can be independently controlled.
【0007】[0007]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0008】図1は本発明の第1実施例を示す図で、同
図(A)は構成図、同図(B)は、下部電極の平面図で
ある。下部電極7は、断熱部8を介して同心円状に7
A,7B,7Cの3つのブロックに分かれ、また温制御
部(下部電極用)3は各ブロックについてそれぞれ独立
した温度制御部3A,3B,3Cを有する。それぞれの
ブロックを適切な温度に設定することにより、例えば半
導体基板6の面内でのエッチングの均一性が悪い場合、
これを改善することができる。また、基板面内でエッチ
ングの形状差がある場合もこれを低減することができ
る。FIG. 1 is a diagram showing a first embodiment of the present invention. FIG. 1A is a configuration diagram and FIG. 1B is a plan view of a lower electrode. The lower electrode 7 is concentrically shaped 7 via the heat insulating portion 8.
The temperature control unit (for lower electrode) 3 is divided into three blocks A, 7B and 7C, and each block has independent temperature control units 3A, 3B and 3C. By setting each block to an appropriate temperature, for example, when the etching uniformity in the plane of the semiconductor substrate 6 is poor,
This can be improved. Further, even when there is a difference in the shape of etching in the plane of the substrate, this can be reduced.
【0009】図2は本発明の第2実施例を示す図で、同
図(A)は構成図、同図(B)は下部電極7の平面図、
同図(C)は上部電極5の平面図である。第2実施例で
は、第1実施例と同様下部電極7を各ブロック毎に温度
制御すると同時に、同様にして上部電極5も温度制御部
(上部電極用)4をブロック化した4A,4B,4Cに
より各ブロック毎に適切な温度に設定できる機能を有す
る。下部電極7及び上部電極5を同時に各ブロック毎に
温度制御することにより、さらにエッチングの面内均一
性及びエッチングの面内形状差の改善が可能となる。2A and 2B are views showing a second embodiment of the present invention. FIG. 2A is a configuration diagram, FIG. 2B is a plan view of the lower electrode 7,
FIG. 6C is a plan view of the upper electrode 5. In the second embodiment, the temperature of the lower electrode 7 is controlled for each block in the same manner as in the first embodiment, and at the same time, the upper electrode 5 also has the temperature control portion (for the upper electrode) 4 formed into blocks 4A, 4B, 4C. Has a function of setting an appropriate temperature for each block. By simultaneously controlling the temperature of the lower electrode 7 and the upper electrode 5 for each block, it is possible to further improve the in-plane uniformity of etching and the in-plane shape difference of etching.
【0010】図3はエッチングの面内均一性を比較する
図で、同図(A)は従来例と第1実施例(下部電極を分
割)と第2実施例(上部電極および下部電極の両者とも
分割)のそれぞれを比較したグラフである。また同図
(B)は半導体基板上の測定ポイントを示す図である。
ドライエッチングは枚葉式ナローギャップ反応性イオン
エッチング装置を用い、ガスはAr:400sccm,
CF4 :20sccm,CHF3 :20sccmの混合
ガスを用いた。エッチング時の圧力は850mTorr
とし、RFパワーは850Wとした。また、被エッチン
グ膜は直径6インチの半導体基板上に酸化シリコン膜を
0.7μm成長したものを用いた。エッチング時間は、
0.7μm厚の酸化シリコン膜を約半分エッチングする
時間とした。従来例の上部電極および下部電極の温度は
それぞれ40℃,−15℃とした。第1実施例では、上
部電極は40℃、下部電極は中央部から7Aを−15
℃、7Bを−10℃、7Cを−5℃とした。第2実施例
では、上部電極は中央部から5Aを35℃,5Bを40
℃,5Cを45℃とし、下部電極は第1実施例と同様の
温度とした。図3(B)の9点の測定ポイントについて
エッチングの速さの測定を行い、エッチング速さの面内
最大値から面内最小値を引き算し、それを面内9点の平
均値で割り算することにより、エッチングの面内均一性
(%)を算出した。図3(A)に示すようにエッチング
の面内均一性は、従来例のエッチングでは8.1%であ
ったが、第1実施例では4.5%,第2実施例では3.
3%にまで低減された。FIG. 3 is a diagram for comparing in-plane uniformity of etching. FIG. 3A shows a conventional example, the first embodiment (the lower electrode is divided), and the second embodiment (both the upper electrode and the lower electrode). It is a graph comparing each of the two). Further, FIG. 3B is a diagram showing measurement points on the semiconductor substrate.
A single wafer type narrow gap reactive ion etching apparatus was used for dry etching, and the gas was Ar: 400 sccm,
A mixed gas of CF 4 : 20 sccm and CHF 3 : 20 sccm was used. Pressure during etching is 850 mTorr
And the RF power was 850W. As the film to be etched, a silicon oxide film having a thickness of 0.7 μm grown on a semiconductor substrate having a diameter of 6 inches was used. The etching time is
It took about half the time to etch the 0.7 μm thick silicon oxide film. The temperatures of the upper electrode and the lower electrode of the conventional example were 40 ° C. and −15 ° C., respectively. In the first embodiment, the upper electrode has a temperature of 40 ° C. and the lower electrode has a central portion of 7 A of −15.
C., 7B was -10.degree. C., and 7C was -5.degree. In the second embodiment, the upper electrode is 5 A at 35 ° C. and 5 B is 40 B from the center.
C. and 5 C were set to 45.degree. C., and the lower electrode was set to the same temperature as in the first embodiment. The etching speed is measured at nine measurement points in FIG. 3B, the in-plane minimum value of the etching speed is subtracted from the in-plane minimum value, and the result is divided by the average value of the nine in-plane values. Thus, the in-plane uniformity (%) of etching was calculated. As shown in FIG. 3 (A), the in-plane uniformity of etching was 8.1% in the etching of the conventional example, but was 4.5% in the first example and was 3.3% in the second example.
It was reduced to 3%.
【0011】図4は測定ポイントにおけるエッチング形
状を比較する図で、同図(A),(B)は従来例の場合
の中央部と周辺部との比較,同図(C),(D)は第1
実施例の場合の中央部と周辺部との比較、同図(E),
(F)は第2実施例の場合の中央部と周辺部との比較を
それぞれ示す断面図である。サンプルは直径6インチの
半導体基板12上に酸化シリコン膜13を0.7μm成
膜し、その上にフォトレジスト膜を塗布し、光露光装置
において径が0.6μmのコンタクトを形成したものを
用い、エッチングは前記条件(ガスはAr:400sc
cm,CF4 :20sccm,CHF3 :20scc
m,圧力は850mTorr,RFパワーは850W)
にて行い、エッチング時間は、基板までエッチングを行
い更に基板までエッチングした時間の倍の時間とした。FIG. 4 is a diagram comparing etching shapes at measurement points. FIGS. 4A and 4B are comparisons of a central portion and a peripheral portion in the case of the conventional example, and FIGS. 4C and 4D. Is the first
Comparison of the central part and the peripheral part in the case of the embodiment, FIG.
FIG. 6F is a cross-sectional view showing a comparison between the central portion and the peripheral portion in the case of the second embodiment. The sample used is one having a silicon oxide film 13 of 0.7 μm formed on a semiconductor substrate 12 having a diameter of 6 inches, a photoresist film applied thereon, and a contact having a diameter of 0.6 μm formed in an optical exposure apparatus. The etching was performed under the above conditions (gas is Ar: 400 sc).
cm, CF 4 : 20 sccm, CHF 3 : 20 scc
m, pressure 850 mTorr, RF power 850 W)
The etching time was twice as long as the time for etching the substrate and then etching the substrate.
【0012】図4に示すように、従来例のエッチングで
は半導体基板中央部(半径35mm以内)と周辺部(基
板の端から10mm中心寄り)とではコンタクト底部の
角度に4°の差があった。第1実施例ではその差が1°
に改善され、第2実施例では半導体基板の中央部と周辺
部とでは同等のコンタクト形状が得られた。As shown in FIG. 4, in the conventional etching, there was a difference of 4 ° in the angle of the bottom of the contact between the central portion (within a radius of 35 mm) of the semiconductor substrate and the peripheral portion (closer to 10 mm from the edge of the substrate). . In the first embodiment, the difference is 1 °
In the second embodiment, the same contact shape was obtained in the central portion and the peripheral portion of the semiconductor substrate.
【0013】[0013]
【発明の効果】以上説明したように本発明は、上部電極
および下部電極をブロック化し、各ブロック毎に温度制
御を行えるようにしたので、エッチングの面内均一性を
改善し、エッチング形状の面内差をなくすという効果を
有する。従って、製品の歩留り及び品質を向上すること
が可能となる。As described above, according to the present invention, the upper electrode and the lower electrode are divided into blocks and the temperature can be controlled for each block. Therefore, the in-plane uniformity of etching can be improved and the surface of the etching shape can be improved. It has the effect of eliminating the internal difference. Therefore, the product yield and quality can be improved.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の第1実施例を示す図で、同図(A)は
構成図,同図(B)は下部電極の平面図である。FIG. 1 is a diagram showing a first embodiment of the present invention, in which FIG. 1A is a configuration diagram and FIG. 1B is a plan view of a lower electrode.
【図2】本発明の第2実施例を示す図で、同図(A)は
構成図,同図(B)は下部電極の平面図,同図(C)は
上部電極の平面図である。2A and 2B are views showing a second embodiment of the present invention, wherein FIG. 2A is a configuration diagram, FIG. 2B is a plan view of a lower electrode, and FIG. 2C is a plan view of an upper electrode. .
【図3】エッチングの面内均一性を比較する図で、同図
(A)は従来例と第1実施例と第2実施例のそれぞれを
比較したグラフ、同図(B)は半導体基板上の測定ポイ
ントを示す図である。3A and 3B are diagrams for comparing in-plane uniformity of etching. FIG. 3A is a graph comparing the conventional example with the first embodiment and the second embodiment, and FIG. 3B is a semiconductor substrate. It is a figure which shows the measurement point of.
【図4】基板中央部と周辺部における測定ポイントのエ
ッチング形状を比較する図で、同図(A),(B)は従
来例,同図(C),(D)は第1実施例,同図(E),
(F)は第2実施例をそれぞれ示す断面図である。4A and 4B are diagrams comparing etching shapes of measurement points in a central portion and a peripheral portion of a substrate. FIGS. 4A and 4B show a conventional example, FIGS. 4C and 4D show a first embodiment, The same figure (E),
(F) is a sectional view showing a second embodiment.
【図5】従来のドライエッチング装置の構成図である。FIG. 5 is a configuration diagram of a conventional dry etching apparatus.
1 ガス源 2 ガス流量制御部 3,3A,3B,3C 温度制御部(下部電極用) 4,4A,4B,4C 温度制御部(上部電極用) 5,5A,5B,5C 上部電極 6 半導体基板 7,7A,7B,7C 下部電極 8 断熱部 9 圧力制御部 10 排気系 11 真空容器 12 半導体基板 13 酸化シリコン膜 1 gas source 2 gas flow rate control unit 3, 3A, 3B, 3C temperature control unit (for lower electrode) 4, 4A, 4B, 4C temperature control unit (for upper electrode) 5, 5A, 5B, 5C upper electrode 6 semiconductor substrate 7, 7A, 7B, 7C Lower electrode 8 Heat insulation part 9 Pressure control part 10 Exhaust system 11 Vacuum container 12 Semiconductor substrate 13 Silicon oxide film
Claims (1)
の電極間に高周波電圧を印加して真空容器内の半導体基
板をエッチングするドライエッチング装置において、前
記一対の電極の少なくとも一方を複数のブロックに分割
し、各ブロック毎に温度を独立して制御する温度制御部
を備えることを特徴とするドライエッチング装置。1. A dry etching apparatus having a pair of upper and lower electrodes in a vacuum container and applying a high-frequency voltage between the electrodes to etch a semiconductor substrate in the vacuum container. The dry etching apparatus is characterized in that the dry etching apparatus is divided into blocks and each of the blocks is provided with a temperature control unit that controls the temperature independently.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33849693A JPH07201822A (en) | 1993-12-28 | 1993-12-28 | Dry etching device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33849693A JPH07201822A (en) | 1993-12-28 | 1993-12-28 | Dry etching device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07201822A true JPH07201822A (en) | 1995-08-04 |
Family
ID=18318705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33849693A Pending JPH07201822A (en) | 1993-12-28 | 1993-12-28 | Dry etching device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07201822A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997020179A1 (en) * | 1995-11-30 | 1997-06-05 | Komatsu Ltd. | Dispersion type multi-temperature control system and fluid temperature control device applicable to the system |
JP2006519497A (en) * | 2003-02-27 | 2006-08-24 | ラム リサーチ コーポレーション | Compensation of fine dimensional variations across the wafer by local wafer temperature control |
JP2009200529A (en) * | 2001-04-30 | 2009-09-03 | Lam Res Corp | Method and apparatus for controlling spatial temperature distribution across surface of workpiece support |
JP2013541842A (en) * | 2010-09-15 | 2013-11-14 | ラム リサーチ コーポレーション | Method for controlling the flux and deposition of plasma components during semiconductor manufacture and apparatus for realizing the same |
US8963052B2 (en) | 2001-04-30 | 2015-02-24 | Lam Research Corporation | Method for controlling spatial temperature distribution across a semiconductor wafer |
US20190157048A1 (en) * | 2017-11-17 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Plasma processing apparatus and method for forming semiconductor device structure |
-
1993
- 1993-12-28 JP JP33849693A patent/JPH07201822A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997020179A1 (en) * | 1995-11-30 | 1997-06-05 | Komatsu Ltd. | Dispersion type multi-temperature control system and fluid temperature control device applicable to the system |
US6157778A (en) * | 1995-11-30 | 2000-12-05 | Komatsu Ltd. | Multi-temperature control system and fluid temperature control device applicable to the same system |
JP2009200529A (en) * | 2001-04-30 | 2009-09-03 | Lam Res Corp | Method and apparatus for controlling spatial temperature distribution across surface of workpiece support |
US8963052B2 (en) | 2001-04-30 | 2015-02-24 | Lam Research Corporation | Method for controlling spatial temperature distribution across a semiconductor wafer |
US9824904B2 (en) | 2001-04-30 | 2017-11-21 | Lam Research Corporation | Method and apparatus for controlling spatial temperature distribution |
JP2006519497A (en) * | 2003-02-27 | 2006-08-24 | ラム リサーチ コーポレーション | Compensation of fine dimensional variations across the wafer by local wafer temperature control |
JP2013077859A (en) * | 2003-02-27 | 2013-04-25 | Lam Research Corporation | Etching system and etching method |
JP2013541842A (en) * | 2010-09-15 | 2013-11-14 | ラム リサーチ コーポレーション | Method for controlling the flux and deposition of plasma components during semiconductor manufacture and apparatus for realizing the same |
US20190157048A1 (en) * | 2017-11-17 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Plasma processing apparatus and method for forming semiconductor device structure |
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