JPH07191948A - State value acquisition system for parallel computers - Google Patents

Abstract

PURPOSE:To facilitate wiring and cable connection at the time of changing the system scale of a parallel computers. CONSTITUTION:In the state value acquisition system of complete crossbar network type parallel computers 1 consisting of plural processing element devices 3 to 5 and plural switching network devices 6 to 9, all of plural processing element devices 3 to 5 and plural switching network devices 6 to 9 have ID numbers respectively, and an ID line through which ID numbers are transmitted from a host computer 2 to all of plural processing element devices 3 to 5 and plural switching network devices 6 to 9, an ID acknowledge line B indicating the validity of the ID line, a state value line through which the device having the ID number designated by the host computer 2 returns the present state value, and a state acknowledge line D indicating the validity of the state line are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state value acquisition method for a parallel computer, and more particularly to a state value acquisition method for a parallel computer in a complete crossbar type parallel computer including a plurality of processing element devices and a plurality of stitching network devices.

[0002]

2. Description of the Related Art Conventionally, a state value acquisition method for a parallel computer of this kind is to obtain a logical product and a logical sum of the statuses of a plurality of processing element devices as described in, for example, Japanese Patent Laid-Open No. 61-275967. By reading out, an abnormal operation of each processing element is detected. A conceptual diagram of this complete crossbar network parallel computer is shown in FIG. 4A, and a connection diagram of the complete crossbar network is shown in FIG. 4B.

In this example, in order for the host computer to acquire the status values of the plurality of processing element devices and the plurality of network devices that constitute the parallel computer, the ID number output by the host computer is used for each processing element device and each switching device. Transfer directly or in parallel to the network device.
Now, an example of a three-input, three-output complete crossbar network type parallel computer including three processing element devices and four switching network devices will be described with reference to FIG.

For direct transfer, as shown in FIG. 5A, the host computer 2 sends an ID signal ((E) in FIG. 6) to the processing element device 3, and the processing element device 3 transfers the ID signal. 4, 5 and then each switching network device 7,
It will be sent to 6, 8, and 9. When the processing element device 3 outputs, the status value ((to) in FIG. 6) is returned to the processing devices 4, 5 and then the switching network device 7,
The call arrives at the host computer 2 via 6, 8, and 9.

In parallel transfer, as shown in FIG. 5B, the host computer 2 assigns the ID number to all the processing element devices 3 to 3.
5 and all switching network devices 6-9 simultaneously. Accordingly, the processing element devices 3 to 5 or the switching network devices 6 to 9 having the corresponding ID number return the status value to the host computer.

[0006]

In the above-described conventional state value acquisition method for a parallel computer, when the number of processing element devices and switching network devices owned by the parallel computer is reduced, a serial transfer method is used. Since the ID signal and the status signal are disconnected, it is necessary to delete unnecessary ID lines and unnecessary status value lines and change the connection of each line.
When the number of devices increases, the ID signal is transferred to all the processing element devices and all the switching network devices, and the increase value I is added so that the status value signals from all the processing element devices and all the switching network devices can be returned to the host computer.
It is necessary to add the D line and the state value line and change the connection of each line.

It is an object of the present invention to reduce the number of processing element devices and switching network devices in order to reduce the parallel number of parallel computers, or to process element devices and switching network devices as the number of parallel computers increases. Even if the number of components of the parallel computer changes due to the increase in the number of parallel computers, if the switching network of the parallel computer is in the complete crossbar network state, that is, in the state where all the components of the complete crossbar network parallel computer are not insufficient. If so, it is to construct a circuit configuration that does not require changes such as addition and deletion of signal lines.

[0008]

Therefore, the method of the present invention is a state value acquisition method for a parallel computer in a complete crossbar network type parallel computer including a plurality of processing element devices and a plurality of switching network devices. An ID that each of the plurality of processing element devices and the plurality of switching network devices owns an ID number, and transmits the ID number from the host computer to the plurality of processing element devices and the plurality of switching network devices.
Line and an ID acknowledge line indicating the validity of the ID line,
It is characterized in that the device having the ID number designated by the host computer has a state value line for returning the current state value and a state acknowledge line showing the validity of the state value line.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1 showing an embodiment of the present invention,
The present embodiment is a complete crossbar parallel computer including three processing element devices and four switching network devices.

When an ID signal ((a) in FIG. 2) is sent from the host computer 2, the switching network device 6 first receives the ID signal. Switching network device 6
Since the circuit configuration of the state value output section of the switching network device 9 is as shown in FIG. 3B, the ID signal is transmitted from the switching network device 8 to the switching network device 9. Next, the ID signal is transferred to the host computer 2 and all the processing element devices 3-5. Since the circuit configuration of the state value output section of each of the processing element devices 3 to 5 is as shown in FIG. 3C, all the processing element devices 3 to 5 send the ID signal first while the ID acknowledge signal is "1". It is transmitted to the switching network devices 6 to 7 of the tier. As a result, the ID signal arrives at the processing element devices 3 to 5 and the switching network devices 6 to 9 which are all the constituent elements of the parallel computer 1.

When the ID is received from the host computer 1, one of the processing element devices 3 to 5 or the switching network devices 6 to 9 corresponding to the ID number outputs a state value ((c) in FIG. 2). As an example, if the processing element device 5 outputs a state value, the state value signal is input to the switching network device 7 and then transmitted to the switching network devices 8-9. Then, it reaches the host computer 2 and the processing element devices 3 to 5. The host computer 2 resets the ID signal and the ID acknowledge signal after acquiring the status value.

In the circuit configuration of the present invention, since the ID signal is held by the flip-flop, I
Resetting the D acknowledge signal resets the ID signal outputs of all the processing element devices, and consequently resets the states of the flip-flops. Therefore, the processing element device 5 that has output the state value also resets the output of the state value.

[0013]

According to the present invention, even if the number of processing element devices and switching network devices, which are constituent elements of a complete crossbar network parallel computer, increases or decreases,
If you keep the state of the complete crossbar network,
It is not necessary to change the wiring to acquire the state value of each device, and there is an effect that the wiring and the cable can be easily connected when the system scale of the parallel computer is changed.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart explaining the operation of the embodiment according to FIG.

FIG. 3 is a diagram showing a circuit configuration of a state value acquisition unit of each device shown in FIG.

FIG. 4 is a configuration diagram of a complete crossbar network parallel computer.

FIG. 5 is a system configuration diagram showing an embodiment of a conventional circuit.

FIG. 6 is a timing chart in the operation description shown in FIG.

[Explanation of symbols]

 1 parallel computer 2 host computer 3,4,5 processing element device 6,7,9,8 switching network device A ID signal line B ID acknowledge signal line C state value signal line D state value acknowledge signal line E parallel computer bus line

Claims (2)

[Claims] 1. A state value acquisition method for a parallel computer in a complete crossbar network type parallel computer comprising a plurality of processing element devices and a plurality of switching network devices, comprising: a plurality of all the processing element devices; Each switching network device has an ID number, an ID line for transmitting the ID number from the host computer to all of the plurality of processing element devices and all of the plurality of switching network devices, and an ID acknowledge line indicating the validity of the ID line. And a state value line through which a device having an ID number designated by the host computer returns the current state value, and a state acknowledge line indicating the validity of the state value line. Value acquisition method. 2. The state value acquisition method for a parallel computer according to claim 1, wherein the ID number is held in a flip-flop.