JPH07183662A - Layered chip component - Google Patents
Layered chip componentInfo
- Publication number
- JPH07183662A JPH07183662A JP34594793A JP34594793A JPH07183662A JP H07183662 A JPH07183662 A JP H07183662A JP 34594793 A JP34594793 A JP 34594793A JP 34594793 A JP34594793 A JP 34594793A JP H07183662 A JPH07183662 A JP H07183662A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- chip component
- pattern
- substrate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、積層チップ部品に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated chip part.
【0002】[0002]
【従来の技術】自動車電話,携帯電話その他の各種通信
用の積層チップ部品は、表面に所定の導体パターン1が
印刷された誘電体からなる基板(グリーンシート)2を
複数枚積層する(図5参照)とともにプレス成型し、次
いで所定部位を切断後、導体パターン1並びに基板2を
同時焼結することにより製造される。2. Description of the Related Art In laminated chip parts for various communications such as car phones, mobile phones and the like, a plurality of substrates (green sheets) 2 made of a dielectric material having a predetermined conductor pattern 1 printed thereon are laminated (FIG. 5). (Refer to FIG. 2), press molding is performed, and then a predetermined portion is cut, and then the conductor pattern 1 and the substrate 2 are simultaneously sintered to manufacture.
【0003】そして、上記導体パターン1の設置位置
は、必ずしも均一に配置されておらず、基板上で密な部
分と粗の部分が生じる。すると、焼結の際に水平方向
(基板2の平面と平行な方向)での収縮率にばらつきを
生じ、寸法精度が損なわれ、不良品となるおそれがあ
る。The positions of the conductor patterns 1 are not necessarily evenly arranged, and a dense portion and a rough portion are formed on the substrate. Then, the contraction rate in the horizontal direction (the direction parallel to the plane of the substrate 2) varies during sintering, which may impair the dimensional accuracy and result in a defective product.
【0004】係る問題を解決するものとして、例えば特
開平5−63365号公報に開示された発明がある。こ
の発明は、基板上の所定位置にダミーの導体パターンを
形成し、全体的に導体パターン(ダミーパターンを含
む)の存在密度が均一になるようにしている。As a solution to this problem, there is the invention disclosed in Japanese Patent Laid-Open No. 63365/1993. According to the present invention, a dummy conductor pattern is formed at a predetermined position on the substrate so that the existence density of the conductor pattern (including the dummy pattern) is uniform throughout.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記し
た従来のチップ部品では、導体パターンが上下,左右対
称でない場合には、プレス時に均一に加圧されず、基板
がずれてしまう傾向にあり、各導体パターン間の相対位
値関係並びに離反距離が設計値通りとならず、不良品と
なるおそれがある。However, in the above-mentioned conventional chip component, when the conductor patterns are not vertically and horizontally symmetrical, the pressure is not uniformly applied during pressing, and the substrate tends to be displaced. The relative value relationship between the conductor patterns and the separation distance do not meet the designed values, which may result in defective products.
【0006】また、仮に図5に示すように、導体パター
ンが上下方向に重なるようにして配置されている場合に
は、最終製品のチップ部品の表面は、図6に示すように
その導体パターンの配置部位だけ上下に突出してしま
う。そして、係る突出は製品全体の高さを増すことにな
り、小型化のネックとなる。さらに下方への突出は、例
えばアースをとるために面接触させたい場合に、確実に
面接触をすることができなくなるという問題を有する。Further, if the conductor patterns are arranged so as to overlap each other in the vertical direction as shown in FIG. 5, the surface of the chip component of the final product has the conductor patterns of the conductor patterns as shown in FIG. Only the placement part projects up and down. Then, such a protrusion increases the height of the entire product, which becomes a bottleneck for downsizing. Further, the downward projection has a problem that the surface contact cannot be surely made when it is desired to make the surface contact for grounding.
【0007】また、プレス時の力の加わり方向に水平成
分が含まれていると、その方向に導体パターンが移動し
ようとし、その結果導体パターンと一体化している基板
にも横方向にずれる力が働く。さらに積層枚数が多い場
合には、その導体パターン部分での上方への突出量が大
きくなり、積層時或いはプレス時に導体パターンが下方
へずれ落ちるようにして移動しようとする。その結果、
たとえ上下方向に重なるように配置された導体パターン
であっても、例えば図7に示すように導体パターンが水
平方向にずれてしまうおそれがある。Further, if a horizontal component is included in the direction in which the force is applied during pressing, the conductor pattern tends to move in that direction, and as a result, the substrate integrated with the conductor pattern is also displaced laterally. work. Further, when the number of laminated layers is large, the amount of upward protrusion of the conductor pattern portion becomes large, and the conductor pattern tends to move downward while being laminated or pressed. as a result,
Even if the conductor patterns are arranged so as to overlap each other in the vertical direction, the conductor patterns may be displaced in the horizontal direction as shown in FIG. 7, for example.
【0008】そして、上記した公報に開示された積層チ
ップ部品は、上述の焼結時の問題は解決されたが、上記
各問題はいずれも包含しており、解決されていない。The laminated chip component disclosed in the above publication has solved the above-mentioned problems at the time of sintering, but it does not solve all the above problems.
【0009】本発明は、上記した背景に鑑みてなされた
もので、その目的とするところは、導体パターンの変形
・位置ずれを抑制し、しかも、製品の外周面への突出量
を制御し、必要に応じて隆起部をなくし平端面とするこ
とのできる積層チップ部品を提供することにある。The present invention has been made in view of the above background, and an object of the present invention is to suppress the deformation and displacement of the conductor pattern and to control the protrusion amount of the product to the outer peripheral surface. It is an object of the present invention to provide a laminated chip component that can eliminate the raised portion and have a flat end surface as needed.
【0010】[0010]
【課題を解決するための手段】上記した目的を達成する
ため、本発明に係る積層チップ部品では、表面に所定の
導体パターンが形成された誘電体基板を複数枚積層する
と共に焼結してなる積層チップ部品を前提とし、前記導
体パターンと積層方向同一直線上で導体パターンの形成
されていない少なくとも1つの誘電体基板に貫通孔を形
成した。In order to achieve the above object, a laminated chip component according to the present invention is formed by laminating and sintering a plurality of dielectric substrates each having a predetermined conductor pattern formed on the surface thereof. Assuming a laminated chip component, a through hole is formed on at least one dielectric substrate on which a conductor pattern is not formed on the same straight line as the conductor pattern in the laminating direction.
【0011】そして好ましくは、積層方向で重なってい
る導体パターンの膜厚の総計と、前記貫通孔の深さの総
計とを略一致させることである。It is preferable that the total thickness of the conductor patterns that overlap each other in the stacking direction and the total depth of the through holes be substantially the same.
【0012】[0012]
【作用】複数の基板上に形成された各導体パターンが積
層方向で同一直線上に重なるようにして配置されると、
積層チップ部品全体を見た場合に、導体パターンが重な
っている部分の外表面が隆起してしまうが、本発明では
係る導体パターンの積層方向と同一直線上に貫通孔が形
成されてるため、外表面に隆起しようとした部分の一部
または全部が貫通孔内に吸収される。これにより、隆起
部分の突出量が制御される。そして、積層方向で重なっ
ている導体パターンの膜厚の総計と、前記貫通孔の深さ
の総計とを略一致させた場合には、上記導体パターンに
よる突出量のすべてが貫通孔により相殺され、外表面の
平坦な積層チップ部品となる。When the conductor patterns formed on the plurality of substrates are arranged so as to be laid on the same straight line in the stacking direction,
When the entire laminated chip component is viewed, the outer surface of the portion where the conductor patterns overlap is raised, but in the present invention, since the through holes are formed on the same straight line as the laminating direction of the conductor pattern according to the present invention, Part or all of the portion that is going to be raised on the surface is absorbed in the through hole. This controls the amount of protrusion of the raised portion. Then, when the total thickness of the conductive patterns overlapping in the stacking direction and the total depth of the through holes are substantially matched, all of the protrusion amount due to the conductive patterns is offset by the through holes, It becomes a laminated chip component with a flat outer surface.
【0013】[0013]
【実施例】以下、本発明に係る積層チップ部品の好適な
実施例を添付図面を参照にして詳述する。図1,図2は
本発明の第1実施例を示しており、例えばコイル,コン
デンサ等の積層チップ部品である。同図に示すように、
グリーンシート等の低温焼結体からなる基板(誘電体)
10の表面所定位置に導体パターン11が形成される。
そして本例では、係る基板10はグリーンシートから形
成され、しかも複数の各基板10の厚さはすべて等しく
している。また、導体パターン11は、上下方向(基板
の積層方向)に重なるように配置されている。そして、
その厚さの一例を示すと、基板10の厚さは80〜20
0μm(本例では100μm)で、導体パターン11の
厚さは20μm程度である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the laminated chip component according to the present invention will be described in detail below with reference to the accompanying drawings. 1 and 2 show a first embodiment of the present invention, which is a laminated chip component such as a coil and a capacitor. As shown in the figure,
Substrate made of low temperature sintered material such as green sheet (dielectric)
A conductor pattern 11 is formed at a predetermined position on the surface of 10.
In this example, the substrate 10 is formed of a green sheet, and each of the plurality of substrates 10 has the same thickness. Further, the conductor patterns 11 are arranged so as to overlap each other in the vertical direction (the stacking direction of the substrates). And
For example, the thickness of the substrate 10 is 80 to 20.
The thickness of the conductor pattern 11 is 0 μm (100 μm in this example) and is about 20 μm.
【0014】ここで本発明では、導体パターン11が重
なる同一直線上に、導体パターン11を形成しない基板
10aを設け、その基板10aの当該部位(導体パター
ン11と重なる部位)に貫通孔12を形成している。そ
して、本例では、基板10の厚さは導体パターン11の
膜厚の5倍であるので、その貫通孔12を形成する基板
10aは、導体パターン11を形成する基板10を5枚
積層するごとに1枚積層するようにしている。これによ
り、貫通孔12が上下方向で平均的に配置されると共
に、上下方向同一直線上に配置される貫通孔12の深さ
(基板10aの厚さ)の総計と、導体パターン11の膜
厚の総計が等しくなる。In the present invention, the substrate 10a on which the conductor pattern 11 is not formed is provided on the same straight line on which the conductor pattern 11 overlaps, and the through hole 12 is formed at the relevant portion of the substrate 10a (the portion overlapping the conductor pattern 11). is doing. In this example, since the thickness of the substrate 10 is five times the film thickness of the conductor pattern 11, the substrate 10a forming the through hole 12 is formed by stacking the five substrates 10 forming the conductor pattern 11 one by one. It is designed to be stacked one by one. As a result, the through holes 12 are evenly arranged in the vertical direction, and the total depth of the through holes 12 (the thickness of the substrate 10a) arranged on the same straight line in the vertical direction and the film thickness of the conductor pattern 11 are set. Will be equal.
【0015】従って、係る積層状態で実際に各基板1
0,10aを重ね合わせると、導体パターン11が重な
ることによりその部分の厚さがかさみ、上下方向に膨ら
むが、その膨らんだ部分は上下に隣接する貫通孔12内
に入り込み、その突出量が吸収される。これにより、隆
起部分の突出量が制御され、本例では導体パターン11
による総突出量が貫通孔12により相殺され、積層チッ
プ部品の外表面に突出することがない(表面は平坦面と
なる)。Therefore, each substrate 1 is actually put in such a laminated state.
When 0 and 10a are overlapped with each other, the conductor pattern 11 overlaps to increase the thickness of the portion and bulges in the vertical direction. The bulged portion enters the vertically adjacent through holes 12, and the amount of protrusion is absorbed. To be done. This controls the amount of protrusion of the raised portion, and in this example, the conductor pattern 11
The total amount of protrusion due to is offset by the through hole 12 and does not protrude to the outer surface of the laminated chip component (the surface becomes a flat surface).
【0016】また、このように導体パターン11の形成
部位が積み重なって大きく隆起することがないので、そ
の導体パターン11が水平方向に移動する(ずれ下が
る)こともない。Further, since the portions where the conductor patterns 11 are formed do not pile up and largely swell, the conductor patterns 11 do not move (shift down) in the horizontal direction.
【0017】よって、積層後プレスした場合に、その加
圧力は均一に加わり、最終的な製品は図2に示すように
内部の導体パターン11は所望の設計通りに整列した状
態を維持し、外表面は平坦面となった積層チップ部品が
製造される。従って、この積層チップ部品を面実装する
ような場合に、実装基板と面接触させることができ、広
面積で確実に接続させることができる。なお、図中符号
13はアース等の外部導体である。なおまた実際には、
プレス後従来と同様の切断・焼結処理等を経て最終製品
が形成されるが、係る点は従来と同様であるので詳細な
説明は省略する。Therefore, when pressed after lamination, the pressing force is uniformly applied, and in the final product, as shown in FIG. 2, the inner conductor pattern 11 maintains the aligned state as desired and the outer portion A laminated chip component having a flat surface is manufactured. Therefore, when this layered chip component is surface-mounted, it can be brought into surface contact with the mounting substrate, and can be reliably connected in a wide area. Reference numeral 13 in the drawing is an external conductor such as ground. And again,
After pressing, the final product is formed through the same cutting / sintering process as in the conventional case, but since this point is the same as in the conventional case, detailed description will be omitted.
【0018】図3,図4は本発明の第2実施例を示して
いる。同図に示すように、本例では上記した実施例と相
違し、貫通孔12を形成する基板10aを第1実施例の
ものに比し少なくしている。すなわち、導体パターン1
1の膜厚の総計に比し、貫通孔12の深さの総計を少な
くしている。3 and 4 show a second embodiment of the present invention. As shown in the figure, in this example, unlike the above-described embodiment, the number of substrates 10a forming the through holes 12 is made smaller than that of the first embodiment. That is, the conductor pattern 1
The total depth of the through holes 12 is smaller than the total thickness of 1 in FIG.
【0019】係る構成にすると、第1実施例のようにそ
の積層チップ部品の外表面は平坦面にはならないが、導
体パターン11に伴う突出量の一部が貫通孔12により
相殺されるので、外表面に突出する量が少なくなる。従
って、図4に示すように、積層チップ部品の外表面の一
部に隆起部14が生じるが、その突出量は従来の物に比
べ少ない。係る構成では、例えば実装基板と積層チップ
部品との間に隙間を設け、積層チップ部品を若干浮かせ
たいような場合に適する。With such a construction, the outer surface of the laminated chip component does not become a flat surface as in the first embodiment, but a part of the protrusion amount due to the conductor pattern 11 is offset by the through hole 12, so that The amount of protrusion to the outer surface is reduced. Therefore, as shown in FIG. 4, the raised portion 14 is formed on a part of the outer surface of the laminated chip component, but the protruding amount thereof is smaller than that of the conventional one. Such a configuration is suitable, for example, when a gap is provided between the mounting substrate and the laminated chip component so that the laminated chip component can be slightly floated.
【0020】そして、本例でも、導体パターン形成部位
が従来のように大きく突出することがないので、導体パ
ターン11が水平方向にずれたりすることはない。すな
わち、本発明では、導体パターン11の膜厚の総計と、
貫通孔12の深さの総計の大小関係及びその差分を適宜
調整することにより、突起部14の突出量を制御するこ
とができる。Also in this example, since the conductor pattern forming portion does not largely project as in the conventional case, the conductor pattern 11 does not shift in the horizontal direction. That is, in the present invention, the total film thickness of the conductor pattern 11 and
The amount of protrusion of the protrusion 14 can be controlled by appropriately adjusting the magnitude relation of the total depth of the through holes 12 and the difference therebetween.
【0021】さらに、所定量だけ突出させる場合に、貫
通孔12の設置箇所を上側に多くすることにより、図4
に示すように、積層チップ部品の上面は平端面とし、下
面に突出させることもできる。なおその他の構成並びに
作用効果は上記した第1実施例と同様であるので詳細な
説明は省略する。Further, in the case of projecting by a predetermined amount, the number of installation places of the through holes 12 is increased to the upper side, so that FIG.
As shown in, the upper surface of the laminated chip component may be a flat end surface, and the lower surface may be projected. Since the other constructions, functions and effects are the same as those of the first embodiment, detailed description thereof will be omitted.
【0022】なお、上記した各実施例では、貫通孔12
を形成する基板10aと導体パターン11を形成する基
板10をすべて同一厚さとしているため、互いの配置枚
数を制御することにより突出量の制御を行うようにした
が、本発明はこれに限ることなく、例えば、基板10と
基板10aの厚さを変えることにより、より精密な制御
を行うことができる。In each of the above embodiments, the through hole 12
Since the substrate 10a on which the conductor pattern 11 is formed and the substrate 10 on which the conductor pattern 11 is formed are all of the same thickness, the amount of protrusion is controlled by controlling the number of arranged substrates, but the present invention is not limited to this. Instead, for example, by changing the thickness of the substrate 10 and the substrate 10a, more precise control can be performed.
【0023】さらに、上記した実施例では、いずれも導
体パターン11を形成する基板10と貫通孔12を形成
する基板10aとを分けて構成したが、本発明はこれに
限ることがなく、同一基板上の異なる位置に貫通孔と導
体パターンが存在してももちろんよい。Further, in each of the above embodiments, the substrate 10 on which the conductor pattern 11 is formed and the substrate 10a on which the through holes 12 are formed are separately configured, but the present invention is not limited to this, and the same substrate is used. Of course, the through hole and the conductor pattern may exist at different positions above.
【0024】さらにまた、上記した各実施例では、各導
体パターンがいずれも製品の全体に渡って上下方向に重
なるように配置された例を示したが、本発明はこれに限
られず、上述した従来公報に示されるように、導体パタ
ーンが上下,左右方向で不均一状態で配置されるもので
も適用できる。Furthermore, in each of the above-described embodiments, an example is shown in which the conductor patterns are arranged so as to overlap each other in the vertical direction over the entire product, but the present invention is not limited to this, and is described above. As shown in the prior art publication, it is also possible to apply a pattern in which conductor patterns are arranged in a non-uniform state in the vertical and horizontal directions.
【0025】[0025]
【発明の効果】以上のように、本発明に係る積層チップ
部品では、導体パターンが重なることにより生じる隆起
部分が、係る導体パターンの積層方向と同一直線上に形
成された貫通孔内に入り込み吸収される。よって、同一
直線上に位置する導体パターンの膜厚の総計と、貫通孔
の深さの総計とを適宜設定することにより、最終的な積
層チップ部品の外表面への突出量が制御される。また、
各基板が積層方向と直交する方向へずれることもなくな
る。As described above, in the layered chip component according to the present invention, the raised portion caused by the overlapping of the conductor patterns enters the through hole formed on the same straight line as the laminating direction of the conductor pattern, and is absorbed. To be done. Therefore, by appropriately setting the total film thickness of the conductor patterns located on the same straight line and the total depth of the through holes, the final protrusion amount of the laminated chip component to the outer surface is controlled. Also,
It is also possible to prevent each substrate from shifting in the direction orthogonal to the stacking direction.
【0026】そして、上記積層方向で重なっている導体
パターンの膜厚の総計と、前記貫通孔の深さの総計とを
略一致させた場合には、上記導体パターンによる突出量
が貫通孔により相殺され、外表面の平坦な積層チップ部
品を構成できる。When the total film thickness of the conductor patterns overlapping in the stacking direction and the total depth of the through holes are made to substantially match, the amount of protrusion by the conductor patterns is offset by the through holes. Thus, a laminated chip component having a flat outer surface can be formed.
【図1】本発明に係る積層チップ部品の第1実施例を示
す分解断面図である。FIG. 1 is an exploded cross-sectional view showing a first embodiment of a layered chip component according to the present invention.
【図2】第1実施例に係る積層チップ部品の最終製品状
態を示す断面図である。FIG. 2 is a cross-sectional view showing a final product state of the laminated chip component according to the first embodiment.
【図3】本発明に係る積層チップ部品の第2実施例を示
す分解断面図である。FIG. 3 is an exploded sectional view showing a second embodiment of the layered chip part according to the present invention.
【図4】第2実施例に係る積層チップ部品の最終製品状
態を示す断面図である。FIG. 4 is a cross-sectional view showing a final product state of a laminated chip part according to a second example.
【図5】従来の積層チップ部品の一例を示す分解断面図
である。FIG. 5 is an exploded sectional view showing an example of a conventional layered chip component.
【図6】従来の問題点を説明する図である。FIG. 6 is a diagram illustrating a conventional problem.
【図7】従来の問題点を説明する図である。FIG. 7 is a diagram illustrating a conventional problem.
10,10a 基板 11 導体パターン 12 貫通孔 10, 10a substrate 11 conductor pattern 12 through hole
Claims (2)
誘電体基板を複数枚積層すると共に焼結してなる積層チ
ップ部品において、 前記導体パターンと積層方向同一直線上で導体パターン
の形成されていない少なくとも1つの誘電体基板に貫通
孔を形成してなる積層チップ部品。1. A laminated chip component obtained by laminating and sintering a plurality of dielectric substrates having a predetermined conductor pattern formed on the surface thereof, wherein the conductor pattern is formed on the same straight line as the conductor pattern in the laminating direction. A laminated chip component formed by forming a through hole in at least one dielectric substrate.
ンの膜厚の総計と、前記貫通孔の深さの総計とを略一致
させてなる請求項1に記載の積層チップ部品。2. The laminated chip component according to claim 1, wherein the total thickness of the conductive patterns that overlap in the stacking direction and the total depth of the through holes are substantially the same.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34594793A JPH07183662A (en) | 1993-12-24 | 1993-12-24 | Layered chip component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34594793A JPH07183662A (en) | 1993-12-24 | 1993-12-24 | Layered chip component |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07183662A true JPH07183662A (en) | 1995-07-21 |
Family
ID=18380088
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34594793A Withdrawn JPH07183662A (en) | 1993-12-24 | 1993-12-24 | Layered chip component |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07183662A (en) |
-
1993
- 1993-12-24 JP JP34594793A patent/JPH07183662A/en not_active Withdrawn
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010306 |