JP2638555B2 - Multilayer printed wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board in which the order of lamination of inner layers and the accuracy of lamination can be easily checked.

[0002]

2. Description of the Related Art A multilayer printed wiring board is usually manufactured as follows. An inner-layer circuit board is manufactured by forming an inner-layer conductor pattern by applying a photoetching method or the like to a single-sided or double-sided copper-clad laminate. A plurality of these inner-layer circuit boards are stacked via a prepreg, a copper-clad laminate is further stacked on the outermost layer via the prepreg, and integrated by heating and pressing using a hot press or the like.

[0003] Next, an unnecessary portion on the outside is cut and removed, processed into a work size called an outer layer blank size, a through hole is opened, a through hole plating is performed by an additive plating method, and a selective plating method is performed. An etching-resistant metal film is selectively formed, and copper etching is performed using the metal film as a mask to form an outer conductor pattern. Finally, the unnecessary outer layer blank size portion is cut and removed to obtain a product.

In recent multilayer printed wiring boards,
With the high functionality and high performance of the set, high density mounting is required. Therefore, it is necessary to increase the number of layers and fineness of the printed wiring board.
Improvement of pattern position accuracy and its confirmation are important themes. In the multilayer printed wiring board, the problem of the difference in the stacking order of the inner circuit boards is also important. Therefore, there have been proposed several multilayer printed wiring boards capable of confirming a difference in a stacking order and a pattern position accuracy.

FIG. 4 shows the technique disclosed in Japanese Patent Application Laid-Open No. 3-250789, and FIG.
4A and 4B show cross-sectional views of the outer layer blank size cut portion, and FIGS. 4B and 4C show plan views of the inner layer circuit board. As shown in FIGS. 4B and 4C, at the end of the outer layer blank size 3 outside the product area 2 of the inner layer circuit board 5, a display conductor pattern 1 indicating the type of each inner layer circuit board is formed. I have. In the multilayer printed wiring board formed by laminating the inner layer circuit boards, when the outer layer blank size is cut,
As shown in (a), the display conductor pattern 1 appears. By visually observing the exposed portion, it is possible to easily determine the difference in the stacking order of each inner conductor pattern layer.

Japanese Unexamined Patent Application Publication No. 61-168293 discloses that, as shown in FIGS. 5 (a) and 5 (b), the end of the product region 2 of each inner layer circuit board 5 is located at the same position. It has been proposed to dispose a circular display conductor pattern 1 having a center at a portion. In this conventional example, when the outer layer blank size 3 is cut and removed after laminating these inner layer circuit boards, the display conductor pattern 1 is exposed on the end face of the product. By visually observing the exposed portion, it is possible to determine the displacement of the lamination position in the x direction and the y direction of each inner conductor pattern layer.

[0007]

In the first conventional example described above, the difference in the stacking order of the inner circuit boards can be identified, but the shift in the stacking position cannot be determined. Also,
In the second conventional example, it is not possible to determine the difference in the stacking order, and it is difficult to determine the degree of the displacement in the direction perpendicular to the cut surface, and it is determined whether the displacement is within the tolerance. There was a drawback that judgment was difficult. Further, in the second conventional example, even though it is possible to determine the displacement of the lamination position of the inner layer circuit board, since the display conductor pattern is arranged at the outer edge of the product, it is not a step after laminating the inner layer circuit board,
The determination can be made only after the product is cut out in the final step, and the discovery of a defect is delayed, resulting in a failure after spending a processing cost.

The present invention has been made in view of such a situation, and an object of the present invention is to make it possible to easily and simultaneously determine the stacking position shift in the x direction and the y direction. It is intended to be able to simultaneously determine both the stacking order difference and the stacking position shift.

[0009]

According to the present invention, there is provided a multilayer printed wiring board comprising a plurality of inner circuit boards on which an inner conductor pattern is formed and an outer layer board. the circuit board (5), across the line corresponding to the outer layer blank size (3), the
A rectangle having two parallel sides in the corresponding line, its length
Said corresponding parallel two sides in the corresponding line of the square
Added a pattern that the width gradually decreases as the distance from the line
Of the shape, and the corresponding shape of the rectangle
The length of the side perpendicular to the line is the lamination of the inner circuit board in this direction
One or more display conductor patterns that are allowable values for positional deviation
A multilayer printed wiring board characterized by being formed ,
Is provided.

[0010] More preferably, the number of display conductor patterns formed on each inner layer circuit board is gradually reduced or increased in accordance with the lamination order (FIGS. 1 and 2), or
The length of the side parallel to the rectangular cut portion of the display conductor pattern formed on each inner layer circuit board is made to gradually decrease or increase in accordance with the stacking order (FIG. 3).

[0011]

In the multilayer printed wiring board according to the present invention, a display conductor pattern having a shape obtained by adding a triangular pattern to two sides on the outside and inside of the rectangle is disposed at the cut portion of the outer layer blank size. This display conductor pattern appears on the cut cross section when cut to the outer layer blank size. By visually observing the position of the display conductor pattern, a positional shift in a direction parallel to the cut surface can be detected. Further, by observing the dimensions of the display conductor pattern, it is possible to detect a positional shift in a direction perpendicular to the cut surface. Furthermore, since the number or size of the display conductor patterns is different for each layer, the difference in the stacking order of the inner circuit boards can be recognized by observing the number or size.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a view showing a first embodiment of the present invention, and FIG. 1 (a) is a perspective view showing a laminated state of an inner circuit board, and FIG. ) Is a plan view. Also,
FIGS. 1C and 1D are a cross-sectional view showing a normal lamination state and a cross-sectional view in a state in which misalignment has occurred.

FIG. 1A is a view showing a state in which an outer layer substrate has been removed. As shown in FIG. 1A, a display conductor pattern 1 is provided on each inner layer circuit board 5. This display conductor pattern 1 does not cover the product area 2,
At the same time as the pattern in the product area 2, it is formed in a portion to be an end face of the outer layer blank size 3. That is, as shown in FIGS. 1C and 1D, the display conductor pattern 1 is formed in the inner conductor pattern layer 5a. In FIG. 1A, each inner-layer circuit board 5 is shown as a single-sided circuit board, but one or more of the inner-layer circuit boards 5 can be a double-sided circuit board.

The shape of the display conductor pattern 1 is shown in FIG.
As shown in the figure, the trapezoidal shape is formed, and the upper bottom is the tolerance of the deviation tolerance dimension (0.5 when the tolerance is ± 0.25 mm).
mm), its lower base is twice as large as its upper base, and its height is a processing precision dimension (for example, 0.25 mm).
The center of the trapezoid is disposed so as to be exposed on the end face of the external blank size 3.

The number and the positional relationship of the display conductor patterns 1 in each layer are as follows. One trapezoid is arranged in the first layer on the inner circuit board, that is, in the second layer as a whole, and in the next layer (third layer). One piece of the same shape as the second layer is arranged at the same position, and a trapezoid of the same shape is placed at a distance of 0.25 to 0.5 mm in the x direction.
Is added. In the second layer (fourth layer), two layers having the same shape as that of the third layer are arranged at the same position, and the layers having the same shape as the third layer are placed in the same direction.
One trapezoid of the same shape is added at a position 25 to 0.5 mm away. Similarly, in the subsequent layers, one trapezoid is added to the number of trapezoids arranged in the preceding layer.

In this embodiment, four inner-layer circuit boards 1 are stacked, and outer-layer boards are disposed above and below the inner-layer circuit boards 1, and the structure has a total of six conductor layers. After these six substrates are laminated and integrated, the substrate is cut into an outer layer blank size 3 which is a work size, and an inner layer blank size 4 portion is removed.

FIGS. 1C and 1D show patterns which appear on the cut surface by this cutting. In FIG. 1C, the height (0.25 mm) of the trapezoidal shape of the display conductor pattern 1 appears in all the inner conductor pattern layers 5a, and the displacement in the y direction (the direction orthogonal to the cut surface). Is within the allowable range. In addition, regarding the positional deviation in the x direction (the direction parallel to the cutting plane), the display conductor pattern 1
By comparing the positions, it can be determined that the displacement of the lamination position between the respective layers is within 0.25 mm. Also, by checking the number of display conductor patterns 1 for each layer, it can be determined that there is no difference in the stacking order.

In FIG. 1D, in the third and fifth layers, the size of the display conductor pattern 1 is 0.25 mm or less. Therefore, it can be seen that the displacement of the lamination position in the third layer and the fifth layer is not less than the allowable range of 0.25 mm. Furthermore, in the fourth layer, the display conductor pattern 1 is shifted from the other layers by 0.125 mm, which is half the height of the trapezoid. Accordingly, it can be seen that the stacking position shift of 0.125 mm occurs in the fourth layer.

[Second Embodiment] FIG. 2 is a view showing a second embodiment of the present invention, and FIG. 2 (a) is a perspective view showing a state of lamination of an inner circuit board. FIG. 2B is a plan view. FIGS. 2C and 2D are a cross-sectional view showing a normal lamination state and a cross-sectional view in a state where misalignment has occurred. In FIG. 2, portions common to those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

The difference of the second embodiment from the first embodiment is that the display conductor pattern is changed from a trapezoidal shape to a hexagonal shape (square +
(Two isosceles triangles). That is,
In this embodiment, the display conductor pattern 1 is a square (having a width of 0.25 in the direction parallel to the cut surface) that satisfies the allowable tolerance dimension.
mm, a length of 0.5 mm in a direction perpendicular to the cut surface) and a triangle added to the inside and outside thereof. In the third to fifth layers, the distance between hexagonal display conductor patterns is set to 0.25 to 0.5 mm.

In FIG. 2C, the square width (0.25 mm) of the display conductor pattern 1 appears in all the inner conductor pattern layers 5a, and the positional deviation in the y direction is within an allowable range. I understand. Also, regarding the positional deviation in the x direction (the direction parallel to the cutting plane), by comparing the positions of the display conductor patterns 1 between the respective layers, it is determined that the positional deviation between the layers is within 0.25 mm. it can.

In FIG. 2D, in the third layer and the fifth layer, the size of the display conductor pattern 1 is 0.25 mm or less. Therefore, it can be seen that the displacement of the lamination position in the third layer and the fifth layer is not less than the allowable range of 0.25 mm. Furthermore, in the fourth layer, the display conductor pattern 1 is shifted from the other layers by 0.125 mm, which is half the width of the rectangle. Accordingly, it can be seen that the stacking position shift of 0.125 mm occurs in the fourth layer.

[Third Embodiment] FIG. 3 is a view showing a third embodiment of the present invention, and FIG. 3 (a) is a perspective view showing a laminated state of an inner circuit board. FIG. 3B is a plan view. FIG. 3C is a cross-sectional view showing a normal stacked state. In FIG. 3, the same reference numerals are given to the parts common to the parts of the first embodiment shown in FIG. 1, and thus the duplicated description will be omitted.

The third embodiment is different from the first embodiment in that the display conductor pattern has one trapezoidal shape in each layer, and the height of the trapezoid is higher as it goes down. is there. In other words, in the present embodiment, the trapezoidal shape of the display conductor pattern 1 is such that the upper bottom has an allowable tolerance of 0.5 m.
m, the lower base is set to 1.0 mm which is twice the upper base, and the height of the second layer is set to 0.5 mm so that the difference in the stacking order can be easily determined. ing.
In addition, the position of the lower base of the trapezoid is common to each layer so that the stacking position shift in the x direction can be easily determined.

In FIG. 3C, the height of the trapezoid of the display conductor pattern 1 (0.5, 0.75, 1.0, 1.25 mm)
All the minutes appear, and it can be seen that the positional deviation in the y direction is within the allowable range. In addition, regarding the positional deviation in the x direction (the direction parallel to the cutting plane), the display conductor pattern 1
By comparing the left ends of the layers, it can be determined that the displacement of the lamination position between the respective layers is within the allowable value. Also, by observing the height of the display conductor pattern in each layer, it can be determined that no difference in the stacking order has occurred.

[0026]

As described above, the multilayer printed wiring board according to the present invention has a display conductor pattern having a shape obtained by adding two triangles to a rectangle having a depth within the allowable range of the lamination position shift, at the cut portion of the outer layer blank size. Since it is formed, it is possible to simultaneously determine the positional deviation in the x direction and the y direction only by displaying one side. Further, since the display is provided on the outer peripheral end face of the outer layer blank size, the display end face appears in the outer layer blank size processing step after the completion of the laminating step. As a result, defects can be detected at a stage before the outer layer processing step is performed, and it is possible to reduce defective costs. Further, since the number or the shape of the display patterns is different for each layer, it is possible to determine the stacking order difference at the same time as detecting the stacking position shift.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view, a plan view, and a cross-sectional view of a first embodiment of the present invention.

FIG. 2 is an exploded perspective view, a plan view, and a sectional view of a second embodiment of the present invention.

FIG. 3 is an exploded perspective view, a plan view, and a sectional view of a third embodiment of the present invention.

FIG. 4 is a cross-sectional view of a first conventional example and a plan view of an inner-layer circuit board.

FIG. 5 is a plan view and an exploded perspective view of a second conventional example.

[Explanation of symbols]

 1 display conductor pattern 2 product area 3 outer layer blank size 4 inner layer blank size 5 inner layer circuit board 5a inner layer conductor pattern layer

Claims (6)

(57) [Claims] 1. A multilayer printed wiring board comprising a plurality of inner circuit boards on which an inner conductor pattern is formed and an outer board, wherein each inner circuit board crosses a line corresponding to a cutting line of an outer blank size. The corresponding line
Into a rectangle with two sides parallel to the rectangle,
A shape obtained by adding a pattern width gradually decreases as the distance from the line the corresponding to two parallel edges in corresponding line
And perpendicular to the corresponding line of the rectangle.
The length of the side of the board should be
One or a plurality of display conductor patterns, which are capacitance values, are formed.
Multilayer printed wiring board, characterized in that there. 2. The method of claim 2, wherein at least one rectangle of each layer is
2. The device according to claim 1, wherein at least one of the sides orthogonal to the corresponding line is arranged at the same position in each layer.
The multilayer printed wiring board according to the above. 3. The multilayer printed wiring board according to claim 1, wherein the number of said display conductor patterns formed on each inner-layer circuit board is gradually reduced or increased according to the lamination order. 4. The length of a side of the rectangle parallel to the corresponding line is an allowable value of a lamination position shift of an inner circuit board in this direction, and a common number of display conductor patterns are the same between adjacent layers. When a plurality of display conductor patterns are formed on the same layer and the plurality of display conductor patterns are formed in the same layer, the distance between the display conductor patterns is 1 to 1 of the lamination position deviation allowable value of the inner layer circuit board in a direction parallel to the corresponding line. 4. The multilayer printed wiring board according to claim 3, wherein the number is doubled. 5. The display conductor pattern formed on each inner layer circuit board, wherein the length of a side parallel to the corresponding line of the rectangle of the display conductor pattern gradually decreases or increases in accordance with the stacking order. The multilayer printed wiring board according to the above. 6. The length of a side parallel to the corresponding line of a rectangle of the display conductor pattern formed on each inner layer circuit board is allowed according to the stacking order of the inner layer circuit boards. 6. The multilayer printed wiring board according to claim 5, wherein the value gradually increases or decreases by value.