JPH07183507A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a normally OFF type semiconductor device having excellent controllability, low ON-resistance, less variation in characteristics by hot carrier, and a high switching speed. CONSTITUTION:An emitter region 3 is provided on the surface of a collector region 2 which is a substrate, and a U-shaped fixed insulating electrode 6 is arranged in such a manner that a part of the collector region 2 and the emitter region 3 are pinched. The above-mentioned fixed insulating electrode 6 is maintained at the same potential as the emitter region 3, and it is formed with the material which forms a depletion layer on the adjacent collector region 2. The emitter region 3 and the collector region 2 are arranged in such a manner that they are electrically interrupted by the depletion region. Also, an injection region 8, which is brought into contact with the collector region 2 and the fixed insulating electrode 6 and does not come into contact with the injection region 8, is provided, and the end part 8 of the injection region is interposed between the insulating film at the tip part of the fixed insulating electrode and the collector region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar type normally-off type vertical power device.

[0002]

2. Description of the Related Art As a prior art related to the present invention, first, a trench j-MOS transistor ("Character" published in IEEE Electron Device Letters magazine is published.
isticsof Trench j-MOS Power Transistors "BERNARD
A. MacIVER. STEPHEN J. VALERI, KAILASH C. JAIN, JAM
ES C. ERSKINE, REBECCA ROSSEN, IEEE ELECTRON DEVIC
ELETTERS, VOL.10, NO.8, p.380-382, AUGUST 1989) are introduced. 18 to 20 are views showing the element structure described in the above document, FIG. 18 is a surface structure diagram of the element, and FIGS. 19 and 20 are line segments A in FIG. 18, respectively.
FIG. 3 is a cross-sectional view taken along line A-B 'or line segment B-B' and viewed in the direction of the respective arrows. First, the structure will be described.
The semiconductor is silicon. In the figure, reference numeral 81 is an n + type drain region which is a substrate, 82 is an n type channel region, and 83
Is an n + type source region. Reference numeral 84 is an insulating film, 85 is a gate electrode made of conductive polycrystalline silicon, and 86 is an interlayer insulating film. Hereinafter, 84, 85 and 86 will be collectively referred to as “insulated gate” 87. The insulated gate 87 is formed inside a groove in which a sidewall is dug vertically from the surface of the substrate, and the bottom reaches the drain region 81. 88 is p
An insulating gate 87 formed in the channel region in the mold region.
It is provided near the. Reference numeral 93 is a metal which is a source electrode and is in ohmic contact with the source region 83.
Reference numeral 95 denotes an electrode metal which makes ohmic contact with the gate electrode 85, and is hereinafter referred to as "MOS gate". Reference numeral 98 is an electrode metal which makes ohmic contact with the p-type region 88, and will be referred to as a "junction gate" hereinafter. Reference numeral 91 denotes a drain electrode, which is a metal that makes ohmic contact with the drain region 81. The drain electrode 91 was not specified in the above document, but was added for easy understanding. In the device shown in the above-mentioned document, the resistivity of the channel region 82 is 0.98 Ω-cm, which is about 5 × in terms of impurity concentration.
This corresponds to 10 ¹⁵ cm ³ . Channel length L shown in FIG.
Is 6 μm, the channel thickness a is 3 μm, and the thickness b of the insulated gate itself is 2 μm.

Next, the operation of this element will be described. A positive potential is applied to the drain electrode 91, and the source electrode 93 is grounded (0V). This device is a four-terminal device having two control electrodes, a MOS gate and a junction gate. Further, both can be connected and used as a three-terminal element. The current-voltage characteristics when driven as a three-terminal element are shown in FIG. FIG. 21 shows a characteristic curve when both gate potentials are applied in steps of 2V from -16 to 0V. The element is a normally-on type, and the stronger the negative potential of the gate, the more the main current is suppressed. The current-voltage characteristics of the four-terminal element are also shown in FIG. This is a diagram when the potential of the MOS gate is fixed and the potential of the junction gate is changed. In the figure, the case where + 16V is applied to the MOS gate and the case where -16V is applied are shown at the same time. M
When a positive potential is applied to the OS gate, it shows a very low on-resistance. This is because the storage layer induced at the interface of the insulated gate film in FIG. 20 serves as a conductive path connecting the n + type drain region 81 and the n + type source region 83. At this time, the potential of the junction gate does not significantly affect the current / voltage characteristics. When a negative potential is applied to the MOS gate, the current / voltage characteristics change depending on the potential applied to the junction gate. FIG. 22 shows characteristic curves when the voltage is applied to the junction gate in the range of −3.5 to 0 V in 0.5 V steps. This characteristic curve is a pentode characteristic having a linear region and a saturation region, as in the case of a normal long channel JFET. The operating mechanism in this state will be briefly described. First, when the junction gate is 0 V, in the linear region of the characteristic curve, that is, in the region where the drain potential is low, a depletion layer is formed in the channel region 82 near the insulated gate 87 when a negative potential is applied to the MOS gate, The holes generated there form an inversion layer at the interface of the gate insulating film. The presence of the inversion layer shields the electric field from the gate electrode. Therefore, the extent of expansion of the depletion layer is different from that of the JFET and remains within a certain range. The value is about 0.4 μm on one side when converted from the data in the above-mentioned literature, and 2 μ is deducted from the channel region.
A neutral area of about m remains. The main current flows through the remaining neutral region in the channel. Then, when the drain potential becomes high, the channel region is in a pinch-off state like a normal long channel JFET, and the current value is saturated. Next, when a negative potential, that is, a reverse bias is applied to the junction gate, the depletion layer from the p-type region 88 reaches the insulated gate close to the p-type region 88. Then, some of the holes in the inversion layer at the insulating film interface flow into the p-type region 88, and the potential at the insulating film interface is affected by the potential at the junction gate. This widens the depletion region in the channel region, narrows the conductive path in the channel region, and reduces the main current. According to the above documents, the main advantages of this device structure are (1) low on-resistance, (2) high mutual conductance due to junction gate, and (3) blocking gain when used as a four-terminal device. High, (4) fast switching speed, (5) it also operates as a three-terminal element, etc.

However, this element has the following limitations. First, this device structure is not suitable for high breakdown voltage.
As described above, the reason for the low on-resistance of this device structure is that the insulated gate is in contact with both the n + type source region and the n + type substrate, and both are formed along the gate insulating film. This is for contacting the storage layer. The design withstand voltage of the device in the literature was 60 V, but if this structure is extended to a device with a higher withstand voltage, this structure in which the insulated gate is in contact with the n + drain region becomes impossible. Next, this element is essentially a four-terminal element, and the driving method inevitably becomes complicated. Of course, as described above, the junction gate and the MOS gate can be connected together and used as a three-terminal element, but as can be seen by comparing FIGS. I can't get it. Further, this element has a normally-on characteristic, and a main current flows when a control signal is not applied. Therefore, in order to ensure safety, a device using this element has to be provided with a separate current interruption device, etc. Further, in order to realize a chip with a large current capacity, in order to draw out three electrodes from the same plane, it is necessary to complicate the electrode structure, such as using a multilayer wiring technique. Alternatively, FIG. 18 should be expanded to extend the length of the insulated gate stripe structure to approximately the length of one side of the chip. In that case, the switching time is lengthened by the speed of holes flowing in the inversion layer.

Next, as a second conventional example, the one disclosed in Japanese Patent Laid-Open No. 57-172765 (“Static induction thyristor”) will be introduced. FIG. 23 shows a cross-sectional view of the device with reference to the publication. In order to make it easy to understand that this structure is an element to which a U-shaped insulated gate is applied, FIG. 23 shows three units of the structure described in the above publication. First, the structure will be described. In the figure, reference numeral 61 is a p + type anode region, 62 is an n− type base region, 63 is an n + type cathode region, and 68 is a p + type gate region. Reference numeral 64 denotes an insulating film, which is the n − -type base region 62, the n + -type cathode region 63, and the p + -type gate region 68.
Touches. Reference numeral 71 is an anode electrode, and 73 is a cathode electrode, which are in ohmic contact with the p + type anode region 61 and the n + type cathode region 63, respectively. Reference numeral 65 denotes a gate electrode, which is in ohmic contact with the p + type gate region 68 and is also in contact with the insulating film 64. That is, this device structure has a structure in which an insulated gate is formed in a groove dug in from the surface, and the gate electrode 65 is connected to the p + type gate region 68 at the bottom of the groove. There is. Further, of the n − type base region 62, the region sandwiched between the adjacent insulated gates will be referred to as a “channel region”.

Next, the operation will be described. The cathode electrode 73 is grounded (at 0 V), and a positive potential is applied to the anode electrode 71. The OFF state of the device is maintained by applying a negative potential to the gate electrode 65 and forming a depletion layer in the channel region in front of the cathode region. That is, this element is also an element having a normally-on characteristic, like the first conventional example. To turn the element on, a positive potential is applied to the gate electrode 65. Then, the depletion layer in the base region disappears and the current path opens, and at the same time, an electron accumulation layer is formed at the interface of the insulated gate, lowering the potential in front of the cathode region and promoting turn-on of the device. .
In order to obtain this effect, it is desirable that the distance between the insulated gate and the main current path is within the diffusion length of carriers. Further, since the storage layer has high conductivity, there is also an advantage that the gate current flows quickly, and the turn-on time becomes faster than that of the static induction thyristor which does not have this mechanism. Once turned on, the on state continues even if the gate potential is released. The turn-off is achieved by applying a negative potential to the gate electrode, sucking out minority carriers in the base region 62, and forming a depletion layer again in the base region. The advantage of this device is that by adding an insulated gate that works in conjunction with the junction gate to a normal electrostatic induction thyristor, (1) the turn-on time is formed because an accumulation layer is formed at the insulated gate interface at turn-on. Get shorter,
(2) At the time of turn-off, a depletion layer is formed in the vicinity of the insulating film to easily pinch off the current, so that the turn-off time is shortened. However, the above device structure has the following difficulties. First, it must be a normally-on type device. Secondly, since it is basically a thyristor, the element cannot be turned off unless the cutoff signal is positively given to the control electrode. Thirdly, in the structure of FIG. 23, a gate insulating film is formed in the groove, and p is formed on the bottom of the gate insulating film.
A contact hole with the + type gate region must be formed. In order to provide the device with a sufficient blocking gain, the depth of the groove forming the insulated gate is required to be several μm, but even if the width of the groove is made much wider than that shown in FIG. It is difficult to form a contact hole on the bottom of such unevenness. In particular, when it is attempted to miniaturize the pattern in order to increase the current capacity, it becomes difficult with ordinary photo-etching technology.

Finally, as a third conventional example, a U-shaped IGB
Introduce T. This is for example the IEEE Transaction on Electron Devices (“500-V n-Chan
nelInsulated-Gate Bipolar Transistor with a Trench
Gate Strucuture ", HRCHANG, B. JAYANT. BALIGA,
IEEE TRANSACTION ON ELECTRON DEVICES.VOL.36, NO.9,
SEPTEMBER 1989). FIG. 24 is a sectional structural view of the above-mentioned conventional example. First, the structure will be described. In the figure,
40 is a p + type collector region, 41 is an n type drift region,
42 is a p-type base region, 43 is an n + type emitter region, 4
Reference numeral 8 is a p + type contact region. Further, 44 is an insulating film, 45 is a gate electrode made of a conductive polycrystalline semiconductor, 4
Reference numeral 6 is an interlayer insulating film. Below, these 44, 45, 46
Will be collectively referred to as “insulated gate” 47. The insulated gate 47 is formed inside a groove in which a side wall is dug vertically from the surface of the substrate, and the bottom portion is an n-type drift region 41.
Has reached. Reference numeral 50 denotes a metal film which will be a collector electrode, and p
+ Ohmic contact with the collector region 40.
Reference numeral 53 is a metal film which serves as an emitter electrode and is in ohmic contact with the n + type emitter region 43 and the p + type contact region 48. In FIG. 24, a region ch shown by a broken line near the insulated gate is a channel.

Next, the operation will be described. The emitter electrode 53 is grounded (0V), and a positive potential is applied to the collector electrode 50. This device structure is a normally-off structure, and when the gate electrode is at 0 V, the channel is closed and no main current flows. In order to turn on the device, an appropriate positive potential is applied to the gate electrode to form an inversion layer by conduction electrons at the insulated gate interface to open the channel ch, and n +
Electrons flow from the type emitter region 43 to the n drift region 41. Then, holes are also injected from the p + type collector region 40 to the n type drift region 41. Then, the n-type drift region 41, which has been made to have a low impurity concentration in order to maintain the breakdown voltage, is conductivity-modulated, and the main current flows with a low resistance. The holes injected into the drift region 42 annihilate in the drift region, or flow from the p-type base region to the emitter electrode through the p + -type contact region. The gate potential may be set to 0 V to turn the element to the off state. Then, the channel ch is closed and the supply of electron current is stopped, so that the injection of holes from the p + type collector region is stopped and the current stops flowing. The advantage of this element is (1) it has a normally-off characteristic, and can be more safe in handling than the above-mentioned two conventional examples, and (2) does not require a negative power supply for basic driving. ) It is a voltage control type device and has a high input impedance, and (4) there is no structural factor that prevents the miniaturization of the pattern for increasing the current capacity. However, this element also has the following limitations. First, referring to FIG. 24, this structure has a pnpn thyristor as a parasitic element by the p + type collector region 40, the n − type drift region 41, the p type base region 42, and the n + type emitter region 43. That is, the amount of main current usually changes in conjunction with a change in gate potential, but when a sudden change in collector potential or excessive supply of holes occurs, this parasitic thyristor operates and the gate electrode loses controllability. there is a possibility. In addition, since this device structure has a forward biased pn junction in the main current path, the collector potential is 0.7V.
No current flows below. That is, there is a theoretical limit to lowering the on-resistance. This also applies to the structure of the second conventional example shown in FIG.

[0009]

As described above, in the first conventional example, an extremely low on-resistance can be obtained, but there is a drawback in that the capacity and the withstand voltage of the chip cannot be increased. There is also a problem that it is a normally-on type and requires careful handling. In the second conventional example, there is no problem in increasing the breakdown voltage, but the structure is not suitable for miniaturization in order to increase the capacity, and there is a limit in reducing the on-resistance due to the structure of the device, and normally -There is a problem that it is an on type and requires careful handling. In addition, the third conventional example has the advantage of being a voltage control type and having normally-off characteristics, but there is a limit to the reduction of the on-resistance due to the structure of the element, and the current control capability due to the presence of the parasitic element. There is a risk of losing. In order to solve the problems of the prior art as described above, the present applicant has developed a novel transistor of normally-off type, which has excellent controllability and low on-resistance, and has already filed an application (Japanese Patent Application No. 5-33419). is doing.

The present invention is a further improvement of the above-mentioned prior art by the present applicant, is a normally-off type, and has excellent controllability.
It is an object of the present invention to provide a semiconductor device having a low on-resistance, little variation or deterioration of characteristics due to hot carriers, and a high switching speed.

[0011]

In order to achieve the above object, the present invention has a structure as described in the claims. That is, an emitter region of the same conductivity type is provided on the surface of a collector region (for example, n type) which is a substrate, and a fixed insulating electrode having, for example, a U shape is arranged so as to sandwich the emitter region of the same conductivity type. . A channel region is formed between the fixed insulated electrodes. The fixed insulating electrode is kept at the same potential as the emitter electrode, and is made of a material having a property of forming a depletion layer in the adjacent collector region and channel region, for example, a p-type polycrystalline semiconductor. Furthermore, an injection region of the opposite conductivity type is provided, which is in contact with the collector region and the insulating film of the fixed insulated electrode and is not in contact with the emitter region. That is, when the device is cut off, the depletion layer formed by the fixed insulating electrode forms a potential barrier for majority carriers (conduction electrons here) in the channel region, and the emitter region and the collector region are electrically cut off. When conducting, apply an appropriate predetermined voltage to the injection region from the outside and introduce minority carriers (here holes) into the insulating film interface of the fixed insulating electrode in contact with the injection region to form the inversion layer. Then, the electric field from the p-type polycrystalline semiconductor of the fixed insulating electrode to the n-type channel region is shielded to recede the depletion layer, thereby removing the potential barrier for majority carriers and opening the channel. Furthermore, by injecting holes from the injection region to the collector region, the conductivity of the collector region is improved. further,
The injection region extends to the interface between the insulating film at the tip of the fixed insulating electrode and the collector region, and is formed so as to surround the tip of the fixed insulating electrode, that is, the portion near the bottom surface of the groove. The extended portion may extend beyond the width of the fixed insulated electrode as shown in FIG. 1 or 2, or may be formed so as to fit within the width of the fixed insulated electrode as shown in FIG. May be. Further, a control electrode which makes ohmic contact with the injection region is provided, and a voltage is applied to the injection region via the control electrode. The collector area is
For example, the emitter region corresponds to the emitter region 3, the fixed insulating electrode corresponds to the fixed insulating electrode 6, the injection region corresponds to the p-type injection region 8, and the fixed insulating electrode of the injection region corresponds to the collector region 2 in FIG. The portion extending to the tip corresponds to the injection area 8 '. The control electrode is the gate electrode 1 in FIG.
8 (only the terminal G is shown in FIG. 1).

[0012]

In the channel region around the fixed insulated electrode fixed to the emitter potential, a depletion layer is formed due to the work function difference with the material of the fixed insulated electrode, whereby the channel region is depleted and the emitter region and the collector region are collected. It is electrically isolated from the area. Further, the fixed insulating electrode has a structure in which the channel is not opened by the collector electric field even if the collector potential rises. That is, the element structure is in the cutoff state from the beginning. However, the minority carriers excited from the depletion layer in the collector region accumulate at the interface of the insulating film and recede the depletion layer in the channel region to leak the main current. Since the injection region of the contact layer is in contact with the insulating film interface, and the injection region is also in ohmic contact with the control electrode, when the control electrode is grounded, minority carriers at the insulating film interface flow out to the control electrode through the injection region. , The potential of the interface of the insulating film does not rise, and the element keeps the cutoff state. On the other hand, when a positive potential is applied to the control electrode, conversely, minority carriers flow into the interface of the insulating film to raise the potential of the interface, the depletion layer recedes, a neutral region appears in the center of the channel, and a current flows. Further, when the injection potential exceeds a predetermined value, the pn junction formed by the injection region and the channel region is forward-biased, the minority carriers are injected into the channel region and the collector region, and the conductivity is modulated, so that the main current has a low on-resistance. It will flow. At this time, the interface of the insulating film functions as a conductive path to carry a minority carrier current to the entire channel region. In order to turn off, the potential of the control electrode is set to ground or reverse potential. In the present invention, since the device structure is minute and the potential of the channel region directly interlocks with the control electrode potential, a larger h _FE can be expected than a single bipolar transistor. Further, the on resistance is low, and a large amount of main current can be controlled with a small base current. Further, since the injection region extends to the interface between the insulating film at the tip of the fixed insulated electrode and the collector region and is formed so as to surround the tip of the fixed insulated electrode, the insulating film at the tip of the fixed insulated electrode is formed. Does not come into direct contact with the collector region, the insulating film can be protected from hot carriers, and fluctuations and deterioration of characteristics due to hot carriers are reduced. In addition, since the minority carriers are quickly supplied and removed, the switching speed is increased and the channel shielding effect is increased, so that the channel length can be shortened.

[0013]

EXAMPLES The present invention will be described in detail below with reference to examples. 1 to 5 show a first embodiment of the present invention. Figure 1
1 is a perspective view for explaining the basic structure of the element, and FIG. 2 is FIG.
3 is a cross-sectional view showing the same portion as the front surface of FIG. 3, and FIG. 3 is a front view of the device. In FIG. 3 and FIG. 1 described above, the electrode (metal film) on the surface is removed. That is, FIG. 3 corresponds to FIG.
A cross section taken along a line perpendicular to the paper surface including the line segment A-A 'is shown. On the contrary, FIG. 2 is a sectional view taken along a plane perpendicular to the plane of the drawing through the line segment AA ′ in FIG. 4 is a sectional view taken along a plane perpendicular to the plane of the drawing through the line segment BB ′ in FIG. 3, and like the case of FIG. 2, the line segment B- in FIG.
A sectional view taken along the line B'corresponds to FIG. Further, FIG. 5 is a sectional view taken along line DD ′ of FIG. In this embodiment, the semiconductor will be described as silicon. Next, the structure of the device will be described. First, in FIGS. 1 to 5, 1 is a substrate n +
The type substrate region, 2 is an n-type collector region, and 3 is an n + type emitter region. Reference numeral 4 denotes a MOS electrode, which is made of a high-concentration p-type polycrystalline semiconductor and is in ohmic contact with an emitter electrode, which will be described later, and has a fixed potential. Reference numeral 5 is an insulating film that insulates the MOS type electrode 4 from the collector region 2. These 4 and 5 are collectively referred to as "fixed insulated electrode" 6. The fixed insulating electrode 6 is formed in a groove whose side wall is dug vertically from the element surface. A region of the n-type collector region 2 sandwiched by the fixed insulating electrodes 6 will be referred to as a “channel region” 7.
The channel region 7 is adjacent to the MO via the insulating film 5.
Since the S-type electrode 4 is a high-concentration p-type semiconductor, the depletion layer formed by the work function difference forms a potential barrier for conduction electrons in the channel region, and the emitter region 3 and the collector region 2 are separated from each other. In this state, it is electrically cut off. Further, 11 is a collector electrode, which is in ohmic contact with the n + type substrate region 1. An emitter electrode 13 is in ohmic contact with the emitter region 3 and the MOS electrode 4. That is, the potential of the MOS electrode 4 is fixed to the potential of the emitter electrode 13. In the figure, H is called a channel thickness and L is called a channel length. Further, 8 is a p-type injection area, and 8'is an injection area 8
It is a portion that wraps and contacts the tip portion of the fixed insulated electrode 6 among them. This 8'is a fixed insulated electrode 6 as shown in FIG.
10 may extend beyond the width of, or may not extend as shown in FIG. Reference numeral 18 denotes a control electrode which makes ohmic contact with the injection region 8 and is hereinafter referred to as a "gate electrode". Further, as shown in FIG. 3, in this embodiment, the fixed insulating electrode 6 has a stripe shape, and both ends thereof are in contact with the injection region 8. In this way, the channel region 7 surrounded by the fixed insulating electrode 6 and the injection region 8 forms one unit cell, and FIG. 2 shows four units of this cell. Note that the shape of the fixed insulating electrode, the shape of the emitter region, and the like that form the unit cell are arbitrary as long as the condition that "the current can be interrupted or the current amount can be controlled depending on the channel state" is satisfied. Also, the shape of the channels may be bent, curved, or have branches. Further, in FIG. 4, the broken line indicates the existence of the fixed insulating electrode 6, and 9 indicates the interlayer insulating film. Also, in FIG.
The relationship between the mold injection areas 8 and 8'is shown. In the present embodiment, the corners of the insulating film 5 of the fixed insulating electrode 6 in the cross-sectional view and the corners of the insulating film 5 in the front view are illustrated as being square, but these are schematic diagrams and are actually shown. May be rounded. It is widely adopted that the corners are rounded in order to suppress the electric field concentration.

Next, the operation will be described. In this device, the emitter electrode 13 is grounded (0 V) and the collector electrode 1
1 is used by applying a positive potential. First, the cutoff state will be described. When the gate electrode 18 is grounded, the device is in a cutoff state. As described above, the MOS type electrode 4
Is made of a high-concentration p-type semiconductor and is fixed to the emitter electrode potential, a depletion layer is formed around the fixed insulating electrode 6, and the channel region 7 is depleted to form the emitter region 3. The collector region 2 has a structure in which it is electrically cut off. Usually, in such a MOS diode-like structure, even if a reverse bias is applied, carriers generated in the depletion layer in the collector region accumulate at the interface of the insulating film 5 to form an inversion layer, and the depletion layer does not spread and is insulated. The potential at the membrane 5 interface increases. However, in this structure, the insulating film 5
However, since they are in contact with the grounded p-type injection regions 8 and 8 ′, the carriers generated in the depletion layer reach the interface of the insulating film 5, but immediately pass through the injection regions 8 and 8 ′ to the outside of the device. Be eliminated by. That is, the potential at the interface of the insulating film 5 is fixed without rising, and the depletion layer spreads in accordance with the reverse bias voltage.

In order for this device to have a normally-off structure, there are two conditions that the structure of the channel must meet. First, one of them is the relationship between the channel thickness and the impurity concentration. FIG. 6 is a diagram in which the potential distribution of the channel region along the line segment CC ′ near the center of the channel region in FIG. 2 is calculated. The vertical axis in FIG. 6 is the potential at the center of the energy band with reference to the Fermi level. Below, the "potential at the center of the energy band based on the Fermi level" is simply referred to as "potential".
I will call it. Here, the build-in potential of the MOS electrode 4 was set to 0.6 eV, the insulating film 5 was made of silicon dioxide, and the thickness was 100 nm. The broken lines at both ends are auxiliary lines showing the potential distribution in the insulating film. The dashed line in the center is the potential position of the semiconductor in the channel region 7 in the neutral state. In FIG. 6, when the potential V _j of the injection region 8 is 0 V, the potential is positive in the entire region of the channel, and conduction electrons do not exist in the channel region 7. In order to satisfy this condition, the impurity concentration N _D of the channel region 7, the channel thickness H, and the insulating film thickness _tox must satisfy the following expressions. First, assuming that the build-in potential of the MOS electrode 4 is P and the potential of the interface between the semiconductor in the channel region and the insulating film 5 is Q, the electric field strength E _ox in the insulating film is constant, and Indicated by.

[0016]

[Equation 1]

On the other hand, since the entire channel region 7 is depleted in the cutoff state, its potential distribution V _ch can be approximated by a quadratic curve as shown in the following (Equation 2).

[0018]

[Equation 2]

In the above equation (2), however, q is a unit charge, ε _si is the dielectric constant of the semiconductor in the channel region, x is the center of the C-C ′ cross section of the channel, that is, the center of the horizontal axis of FIG. The distance R measured in the direction of the insulating film is the lowest point of the potential. The potential Q at the interface between the channel region 7 and the insulating film 5 is expressed by the following (Equation 3).

[0020]

[Equation 3]

Further, the electric field E _{si at} this point is expressed by the following equation (4).

[0022]

[Equation 4]

Further, since the electric fluxes must match at the interface, the following equation (5) must be satisfied. ε _ox E _ox = ε _si E E _si (Equation 5) The build-in potential of the MOS type electrode 4 is 0.6e.
V, the minimum value R of the potential of the channel region 7 is set to 0.3 eV so that the channel is not easily opened due to noise of the control signal, and the above equations (1) to (5) are satisfied. FIG. 7 shows the relationship among the impurity concentration N _D of the channel region 7, the insulating film thickness t _ox , and the channel thickness H. Note that FIG. 7 shows curves when the insulating film thickness _tox is 50 nm and 100 nm, but the lower left region of each line is a condition to be satisfied by this device. For example,
In either case of the above two insulating film thicknesses, the impurity concentration N _D
= 1 × 10 ¹⁴ / cm ³ and channel thickness H = 2 μm are suitable conditions.

Next, as the second condition for the device to have the normally-off characteristic, there is a condition that the channel thickness H and the channel length L must be satisfied. Figure 8
Is the result of numerical calculation of the potential distribution of the channel region 7. The plane serving as the base is a view of the center of the channel from the emitter interface side of the channel region 7 in FIG. 2, and the vertical axis represents the potential. Although the equipotential lines are shown in FIG. 8, it can be seen that the potential of the channel region 7 is lowered by the influence of the emitter region (not shown) in the front of the drawing. The side surface is the interface with the insulating film, and the back surface in the figure coincides with the line segment CC ′ in FIG. 2, and the potential distribution there is not affected by the emitter region 3, 6 is equivalent to the curve of V _j = 0. As a result of performing the same numerical calculation with some settings satisfying the conditions of FIG. 7, the influence of the potential decrease at the emitter end of the channel region 7 is about 1 to 1.5 times the channel thickness in the channel length direction. It turned out to stop by that point. On the other hand, in the portion of the channel region 7 facing the collector region 2, the effect of lowering the channel potential by the collector electric field is almost the same,
The channel normally-off characteristic, that is, the condition that the channel does not open due to its influence even if the collector electric field rises is that the ratio of (channel length L) / (channel thickness H) is 2 to
It will be 3 or more. For example, the impurity concentration of the channel is 1 × 10 ¹⁴ / cm ³ , that is, the specific resistance is about 40Ω−.
cm, and when the insulating film thickness is 100 nm or less, a channel length of 6 μm is sufficient when the channel thickness H is 2 μm. As an example, if the channel thickness H is 2 μm, the effect of distorting the electric field in the channel region 7 due to the presence of the emitter region 3 is about 2 μm in the channel length direction.
m. Also, as shown in FIG. 10, the fixed insulation electrode 6 has an injection region 8'that encloses the tip of the fixed insulation electrode 6.
In the case where it does not extend beyond the width of, the effect of the collector electric field distorting the electric field in the channel region 7 is still about 2 μm in the channel length direction. However, when the injection region 8'is out of the width of the fixed insulated electrode 6 as shown in FIG. 1, if the distance between the adjacent injection regions 8'is, for example, 1 μm, the collector electric field is The distance that affects the channel region 7 is about 1 μm. Therefore, even if a margin is taken into consideration, if the channel length is 6 μm in the case of FIG. 10 and 4 μm in the case of FIG. 1, the channel will not open no matter how strong the collector electric field becomes. Under this condition, the specific resistance of the channel region 7 must be 10 Ω-cm or more so that the channel region 7 can be completely depleted. As described above, by providing the injection region 8 ', the channel shielding effect is enhanced and the channel length can be shortened. When the collector electric field is increased, a slight amount of holes are generated from the depletion layer. The holes reach the vicinity of the channel and flow into the injection region 8 as an inversion layer at the interface of the insulating film 5, or enter the injection region 8'and quickly flow to the gate electrode. Furthermore, since the injection region 8'covers the tip of the fixed insulating electrode 6, it also has the function of protecting the insulating film 5 from hot carriers. Therefore, there is little variation or deterioration of characteristics due to hot carriers. The concentration of the injection region 8 ′ is the highest near the interface of the insulating film 5, and the closer it is to degeneracy, the better the concentration.

Next, a mechanism for changing from the disconnected state to the conductive state will be described. In the potential distribution diagram of the channel region shown in FIG. 6, when the gate potential VG is 0 V, that is, in the cutoff state, the potential is positive in the entire region of the channel, and conduction electrons do not exist in the channel region 7. When a slightly positive potential (VG = 0.3eV) is applied to the gate electrode 18, the potential near the center of the channel is 0e.
It becomes V or less, and conduction electrons can exist. In this way, the potential of the channel region 7 is lowered by increasing the gate potential, contrary to the case of the blocking state, holes flow into the inversion layer at the interface of the insulating film 5 from the p-type injection region 8 having a high potential. And M for the channel region 7
This is because the electric field from the OS type electrode 4 is shielded. When a positive potential is applied to the gate electrode 18 in this way, the depletion layer recedes, a neutral region appears at the center of the channel, and a current flows. Further, when the gate potential becomes 0.5 eV or more, the potential becomes lower than the one-dot chain line, and the shape of the band in the channel region 7 becomes flat. This is because the junction between the n-type collector region 2 and the injection region 8 is in the forward bias state, and the entire collector region is in the high level injection state. At this time, the holes directly propagate through the injection region 8 and are also supplied from the interface of the insulating film 5 to the collector region. At this time, the injection region 8'has a function of promptly supplying holes to the channel. Under this condition, the interface between the insulating film 5 and the injection region 8'acts as a conductive path having a very high conductivity and carries the hole current. At this stage, it is easier to understand the collector current control by paying attention to the current rather than the gate potential. That is, the conductivity of the collector region 2 is controlled by the hole current injected into the collector region 2, and the main current is controlled. In the conductive state, the channel region 7
The supply of holes to the channel region 7 is predominantly from the interface of the fixed insulating electrode 6, and the amount of holes directly supplied from the injection regions 8 and 8'to the channel region 7 is smaller.
There is no need for non-uniformity of conductivity. For that purpose, the distance between the emitter region 3 and the injection region 8 (see FIG.
It is desirable that D) of is not less than the channel thickness H.

Next, a mechanism for changing from the conductive state to the cutoff state will be described. To turn off, the gate potential is grounded (to 0V) or a negative potential. Then, a large amount of holes existing in the collector region 2 and the channel region 7 disappear, or the injection region 8,
The channel region 7 is filled with the depletion layer again by being eliminated through 8 '. Here, the injection region 8'at the bottom of the fixed insulated electrode 6 has a function of promptly removing excess carriers. This turn-off mechanism is similar to that of a bipolar transistor.

As described above, the injection area 8 '
Has a function of promptly supplying holes to the channel and a function of promptly removing excess carriers, the provision of the injection region 8'accelerates the switching speed. In FIG. 4, the depth of the injection region 8 is drawn deeper than that of the fixed insulated electrode 6. With such a structure, a negative potential can be applied to the gate electrode 18 and turn-off can be performed faster. However, even if the depth of the injection region 8 is not so large as that of the fixed insulating electrode 6, it functions as a device.

Next, FIG. 9 is a characteristic diagram showing a voltage / current characteristic curve of the device of this embodiment. As shown in FIG. 9, the voltage / current curve rises linearly from the origin. This is similar to the characteristics of a single bipolar transistor. However, since there is no base region like the bipolar transistor in the structure of FIG. 1, there is no saturation characteristic in the current / voltage characteristic. Therefore, the current curve fluctuates depending on the gate current even when the collector voltage is low. The reason why the amount of current saturates as the collector potential rises is that when the collector potential rises, most of the holes exist only in the channel region 7, the depletion layer spreads in the collector region 2, and the electron current is in a pinch-off state. . Further, since the collector current is determined by the injected hole current, h _FE (DC current amplification factor) similar to that of the bipolar transistor can be defined. In this element, since the element structure is fine and the potential of the channel region 7 directly interlocks with the gate potential, a larger h _FE than that of a single bipolar transistor can be expected.

Next, a method of manufacturing the structure shown in FIG. 1 will be described.
11 to 16 are perspective views showing an embodiment of the manufacturing process of this embodiment. First, as shown in FIG. 11, the surface of the n + -type region 1, which is the substrate, is n-grown by epitaxial growth.
A mold collector region 2 is formed. Further, on the surface thereof, an n + type region which becomes the emitter region 3 and an injection region 8 are formed.
Forming a p-type region. Next, as shown in FIG. 12, a mask material 100 is formed on the surface, and a pattern for forming a groove for a fixed insulated electrode is formed. This is etched by anisotropic dry etching to form a groove whose side wall is almost vertical as shown in FIG. Next, as shown in FIG. 14, the inner wall of the groove is oxidized to form the insulating film 5, and ion implantation for the injection region 8'is performed. And M
A high-concentration p-type polysilicon 4'which will become the OS-type electrode 4 is deposited. Next, as shown in FIG. 15, p only in the groove
Etch to leave mold polysilicon. Next, as shown in FIG. 16, the mask material 100 is removed and an interlayer insulating film and an electrode are formed, whereby the structure of FIG. 1 can be formed. Note that in FIG. 16, the electrode terminals E and G are schematically drawn in order to facilitate understanding of the device operation. The MOS electrode 4 may be made of the same metal as the emitter electrode 3 as long as the condition that the channel is not opened by the collector electric field when the gate potential is in the cutoff state is satisfied. In addition, in the process of FIG.
Before the ion implantation, as shown in FIG. 17, if the side wall 101 is formed of a silicon nitride film or the like,
The injection region 8 ′ can be formed so that the size of the injection region 8 ′ does not extend beyond the width of the fixed insulating electrode 6 when the ion-implanted impurities are diffused. In this way, the structure of FIG. 10 can be formed. In the above description, the substrate has been described as an n-type semiconductor, but this structure will work even if all the impurity types are reversed.

Next, the difference between the present invention and the conventional example will be summarized. First, the present invention and the first conventional example (see FIG. 18).
20), the potential of the insulating electrode (MOS gate 95) is variable in the first conventional example, and by making the potential of the insulating electrode positive, an electron storage layer is formed at the interface of the insulating film. An insulating electrode is used as a control electrode so as to realize a low channel resistance by being formed. On the other hand, in the present invention,
The insulating electrode (fixed insulating electrode 6) is fixed to the emitter potential and is basically not a control electrode. This is a crucial difference. In addition, the first conventional example is a normally-on type device, and in order to cut off the main current, it is necessary to positively apply a negative potential to the junction gate 98 and the MOS gate 95. However, the device of the present invention is a normally-off type device, and cannot be used otherwise. Therefore, in order to maintain the off state, the gate electrode 18 may have the same potential as the emitter region 3, that is, the ground potential. Further, in the present invention, it is essential that the injection region 8 is in contact with the interface of the insulating film 5, whereby the potential of the interface of the insulating film 5 is changed to the gate electrode 18.
It is actively controlled by the potential of. On the other hand, the junction gate 98 in the first conventional example does not contribute to the ON state of the device. As far as it is described in the literature of the first conventional example, the p-type region 88 is the insulating film 84.
Therefore, even if the potential of the junction gate 98 is positive, the condition of the insulating film interface cannot be controlled. The on-state of the device of the invention then opens the channel by supplying minority carriers from the injection region and modulates the conductivity of the collector region as well as the channel region. On the other hand, in the first conventional example, even if a positive potential is applied to the junction gate 98 and minority carriers are injected, the channel region containing a large amount of impurities is used in order to allow the main current of the monopolar to flow with a low ON resistance. The conductivity of 82 can be hardly affected. As described above, the first conventional example is a monopolar device, whereas the present invention is a bipolar device. In the present invention, the insulating film 5 and n +
Since it is separated from the region 1, it is possible to increase the breakdown voltage of the device.

Next, the difference from the second conventional example (FIG. 23) will be described. In the second conventional example, it is the same that the p-type region is located at the bottom of the insulating electrode. However, in the second conventional example, the p-type region and the insulating electrode are connected to each other, but in the present invention, they are not in contact with each other, the insulating electrode potential is a fixed potential, and only the p-type injection region is provided. Is clearly different in that it acts as a control electrode.
In the present invention, since it is not necessary to provide a contact hole at the bottom of the insulated electrode as described above, there is no limitation in pattern miniaturization as in the conventional example. Further, in the second conventional example, since the main current path has a pn junction, a satisfactory current does not flow unless the voltage between the main current terminals becomes approximately 0.7 V or higher. However, since the present invention does not have such a pn junction, the characteristic curve rises linearly near the origin of the current / voltage characteristic in FIG.

Next, differences from the third conventional example (FIG. 24) will be described. In the third conventional example, the insulated electrode (gate electrode 45) is a control electrode whose potential is variable, and the junction region (p
While the electric potential of the mold base region 42) is fixed,
In the present invention, conversely, the junction region (injection region 8) is a control electrode whose potential is variable, and the potential of the insulating electrode (MOS electrode 4) is fixed, which is clearly different.
Further, in the third conventional example, the main current path is the inversion layer by electrons at the interface of the insulating film, but the present invention is different in that it is in the central portion of the channel or the entire channel. Also, in the third conventional example, the conductivity modulation mechanism is the second one.
It is the same as the conventional example and is clearly different from the present invention. As described above, in the second and third conventional examples, since the main current path has the pn junction, a satisfactory current will flow unless the voltage between the main current terminals becomes approximately 0.7 V or more. There is a characteristic that it does not exist. However, with the device of the present invention,
Since there is no such pn junction, a sufficient current can flow even at a lower voltage.

[0033]

As described above, in the present invention,
The following effects can be obtained.

(1) It has a normally-off characteristic. (2) It is a current control type three-terminal element. (3) Low on-resistance. (4) A large main current can be controlled with a small control current. (5) This structure is suitable for miniaturization (large capacity) and high breakdown voltage. (6) It has no parasitic element. (7) It can be realized only by the conventional LSI manufacturing technology. (8) Little change and deterioration in characteristics due to hot carriers. (9) The switching speed is fast.

[Brief description of drawings]

FIG. 1 is a perspective view of a first embodiment of the present invention.

FIG. 2 is a sectional view of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the surface structure in the first embodiment of the present invention.

FIG. 4 is a sectional view taken along line BB ′ of FIG.

5 is a cross-sectional view taken along the line DD ′ of FIG.

FIG. 6 is a potential distribution diagram of a channel region in the first embodiment.

FIG. 7 is a diagram showing a relationship between an impurity concentration of a channel region, an insulating film thickness, and a channel thickness.

FIG. 8 is a potential distribution diagram of a channel region.

FIG. 9 is a characteristic diagram showing a voltage / current characteristic curve in the first embodiment.

FIG. 10 is a sectional view of an embodiment showing another structure of the present invention.

FIG. 11 is a perspective view showing a part of the manufacturing process of the first embodiment of the present invention.

FIG. 12 is a perspective view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 13 is a perspective view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 14 is a perspective view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 15 is a perspective view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 16 is a perspective view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 17 is a sectional view showing a part of the manufacturing process for forming the structure of FIG.

FIG. 18 is a plan view of a first conventional example.

FIG. 19 is a sectional view of a first conventional example.

FIG. 20 is another cross-sectional view of the first conventional example.

FIG. 21 is a current-voltage characteristic diagram when the first conventional example is operated as a three-terminal element.

FIG. 22 is a current-voltage characteristic diagram when the first conventional example is operated as a four-terminal element.

FIG. 23 is a sectional view of a second conventional example.

FIG. 24 is a sectional view of a third conventional example.

[Explanation of symbols]

1 ... Substrate region 8, 8 '... Injection region 2 ... Collector region 9 ... Interlayer insulating film 3 ... Emitter region 11 ... Collector electrode 4 ... MOS type electrode 13 ... Emitter electrode 5 ... Insulating film 18 ... Gate electrode 6 ... Fixed insulating electrode 100 ... Mask material 7 ... Channel region 101 ... Sidewall

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, which is a collector region, is in contact with one main surface thereof, and has one or a plurality of island-shaped emitter regions of the same conductivity type, and the main surface is provided with the emitter region. There is one or a plurality of grooves sandwiching the groove, and inside the groove, there is a fixed insulating electrode insulated from the collector region by an insulating film and kept at the same potential as the emitter region. The insulating electrode is made of a conductive material having a property of forming a depletion region in the collector region adjacent to the collector region through the insulating film, and is in contact with the insulating film surrounding the fixed insulating electrode and the collector region, An injection region of opposite conductivity type that is not in contact with the emitter region, is a part of the collector region adjacent to the emitter region, and is sandwiched by the fixed insulated electrode; In the state where the potential of the injection region is kept at the same potential as the potential of the emitter region, the channel region that electrically cuts off the emitter region and the collector region by the potential barrier formed by the depletion region is formed. And a control electrode which has the injection region and also intervenes at the interface between the insulating film and the collector region at the tip of the fixed insulating electrode, that is, in the vicinity of the bottom surface of the groove, and which makes ohmic contact with the injection region. A semiconductor device comprising: