JPH07176705A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To form a two-layer gate structured MOSFET with a one-layer gate structured MOSFET adjacently in high-density packing, by forming a dummy buffer wiring layer between the two-layer gate structured MOSFET and the one-layer gate structured MOSFET. CONSTITUTION:A dummy buffer wiring SG has a two-layer gate structure on the two-layer gate side and a one-layer gate structure on the one-layer gate side. Each gate electrode of a drain-side switching MOSFET (STMOS) and a source-side switching MOSFET (STMOS) is formed with the dummy buffer wiring (surplus gate) SG in between, including a second-layer polysilicon layer SG formed in one body. An error in mask alignment at the dummy buffer wiring can be absorbed. In a productive step, the self-alignment patterning in two-layer gate structure is carried out separately from self-alignment of a source/drain diffusion layer in one-layer gate structure, and the semiconductor device is formed in high-density packing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing method, and more particularly to a MOSF having a two-layer gate structure.
The present invention relates to a technique effectively used for a batch erase type nonvolatile memory device or the like including an ET and a MOSFET having a single-layer gate structure.

[0002]

2. Description of the Related Art An electrical batch erasing type EEPROM is a system in which all of the memory cells formed on a chip are collectively operated, or a group of memory cells among the memory cells formed on the chip are collectively operated. It is a non-volatile memory device that has a function of erasing physically. Such a batch erase type EEPR
Regarding OM, for example, 1980 IEE, International, Solid-State
Circuits Conference (IEEE INTERNATIONAL SOL
ID-STATE CIRCUITS CONFERENCE) pages 152-153, 19
1987 IEE, International, Solid-State Circuits Conference
(IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENC
E) pages 76-77, IEE Journal
Of Solid State Circuits, Vol. 23, No. 5 (1988), pages 1157 to 1163 (IEEE, J. Solid-S
tate Cicuits, vol.23 (1988) pp.1157-1163).

[0003]

In the applicant of the present application, a write operation is performed by a tunnel current as a memory transistor having a control gate and a floating gate, and charges are injected into the floating gate contrary to the conventional case. By doing so, a memory transistor has been developed which performs an erase operation by making the threshold voltage higher than the selection level of the word line. In this configuration, since the threshold voltage of the erase operation for the memory transistor is set higher than the selection level of the word line, the charge of the floating gate is extracted to the substrate side as in the conventional case. Like a memory transistor that lowers the voltage, other memory cells may become unreadable by being turned on regardless of the word line being at the non-selection level due to the depletion mode due to overerasure. Absent.

However, in the case where the write operation is performed by the tunnel current, the tunnel current does not flow in the non-selected storage transistor at the time of writing so that the tunnel current is not generated by the read operation and erroneous erasure is prevented. It is necessary to devise such a device as to reduce the voltage applied to the drain of the memory transistor during reading. Therefore, in order to prevent such a soft write to the storage transistor, it is considered that a plurality of storage transistors are set as one block and a selection MOSFET is provided and connected to a data line or a common source line. However, when forming such a circuit on a semiconductor substrate,
A new device is required to efficiently lay out the memory transistor having the double-layer gate structure and the select MOSFET having the single-layer gate structure.

An object of the present invention is to provide an MO having a two-layer gate structure.
It is an object of the present invention to provide a semiconductor integrated circuit device in which an SFET and a MOSFET having a single-layer gate structure can be formed adjacent to each other with high density, and a manufacturing method thereof. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a MOSF having a two-layer gate structure
A buffer dummy wiring layer having a double-layer gate structure on the double-layer gate structure side and a single-layer gate structure on the single-layer gate structure side is provided between the ET and the single-layer gate structure MOSFET.

[0007]

According to the above means, patterning by self-alignment of the double-layer gate structure and diffusion by self-alignment of the source and drain of the single-layer gate structure are performed while absorbing the mask shift in the buffer dummy wiring portion. The layer and the layer can be separately formed to have a high density.

[0008]

The outline of other typical inventions among the inventions disclosed in the present application will be briefly described as follows. That is, M having a two-layer gate structure
A MOSFET having a single-layer gate structure, in which a first-layer gate electrode forming an OSFET is integrally formed, an insulating film is formed on the first-layer gate electrode, and a buffer region is almost at the center as a boundary. A gate insulating film is formed, and a second-layer gate electrode forming a MOSFET having a two-layer gate structure, a gate electrode forming the MOSFET having a one-layer gate structure, and a dummy wiring for buffering are simultaneously formed. Two-layer gate structure MOSFET and one-layer gate structure MO
Patterning of a gate electrode having a substantially double-layer structure is performed by self-alignment using the second-layer gate electrode as a mask by masking the first-layer structure side with the buffer region provided between the SFETs as a boundary. Then, the source and drain of the MOSFET having a one-layer structure are diffused by self-alignment using the two-layer structure side as a mask and the gate electrode as a mask.

[0009]

According to the above-mentioned means, the MOSFET having the double-layer gate structure and the MOSFET having the single-layer gate structure can be formed at a high density by absorbing the mask shift in the buffer dummy wiring portion while self-aligning the double-layer gate structure. Can be formed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a schematic circuit diagram of one embodiment of a memory mat and its peripheral portion in a batch erase type nonvolatile memory device according to the present invention. The memory cell is a stacked gate structure MOSFE having a control gate and a floating gate similar to a conventional memory cell.
T. In this embodiment, both a writing operation and an erasing operation are performed by utilizing a tunnel current passing through a thin oxide film as described later.

As shown in the memory MOSFET QM in which the floating gates are indicated by dots, a plurality of memory MOSFETs QM are made into one block and the drain and the source are commonly used. The common drain of the storage MOSFET is connected to the data line DL through the selection MOSFET QD. The common source of the storage MOSFET is connected to the common source line through the selection MOSFET QS. This common source line is the signal MSC
Is connected to the voltage VMW through a switch MOSFET Q2 which is switch-controlled by. The voltage VMW is given the ground potential of the circuit during the read operation and the write operation, and is given a negative voltage during the erase operation according to the operation mode. The control gate of the memory MOSFET is typically connected to a word line WL, which is represented by one circuit symbol. Select MOSFE above
T is selected by a select line extending in parallel with the word line WL. That is, the selection MOSFET QD
And QS are main word lines selected by the main decoder MAN-DEC.

As described above, the memory cell is divided into blocks, and the data line DL is connected to each block through the selection MOSFET.
With the configuration for applying the VMW (ground potential) of the circuit or the circuit, the stress on the non-selected memory cells can be reduced. That is, the word line WL is selected and the data line D
L is a non-selected memory cell, and conversely, the word line W
When L is set to the non-selected state and the data line DL is set to the non-selected state, the write or erase voltage is applied to the memory cell that should hold the data in the write or erase operation. And soft erase. In this configuration, the above stress is applied only to a small number of memory cells in the block.

In this embodiment, although not particularly limited, the adjacent data lines DL are divided into odd-numbered and even-numbered data lines. And corresponding to each short MOSFET
Is provided. In this short MOSFET, odd-numbered and even-numbered data lines DL are alternately selected,
The data line DL in the non-selected state is set to a fixed level of the ground potential of the circuit to reduce mutual coupling noise in the adjacent data line DL. Corresponding to such a configuration of the data line DL, a transfer MOSF as a switch circuit, which will be described later, is provided for the sense amplifier SA that amplifies the read signal appearing on the data line DL.
ET is also divided into odd number and even number and is selected.

One of the memory cells in the block selected by the main decoder MAN-DEC is selected by the sub-decoder SUB-DEC. The sub-decoder SUB-DEC selects one word line WL in the block. Such a selection signal for one word line is formed by a gate decoder (Pre Dec). That is, the sub-decoder SUB-DEC receives the selection signal of the word line formed by the gate decoder and the selection / non-selection level formed according to the operation mode formed by the main decoder MAN-DEC,
A drive signal for selecting / non-selecting a word line in the block is formed.

A sub-decoder SUB-DEC is provided so as to sandwich the small memory mat MAT. For example, the sub-decoder SUB-DEC sandwiched between two small memory mats is
The drive signal for every other word line on both sides thereof is formed. Sub-decoder SUB-DEC distributed vertically
Form a selection signal for every other word line provided between them. In this way, the word lines of the small memory mat are alternately connected to the two sub-decoders provided with the small memory mat interposed therebetween, and an efficient layout is realized.

FIG. 4 shows a schematic circuit diagram of an embodiment of the sense amplifier and its peripheral portion. Of the pair of inputs and outputs of the sense amplifier, the peripheral portion corresponding to the data line of one of the small memory mats is shown as a representative, and the circuit on the side of the other small memory mat, which is a symmetrical circuit, is partially omitted. Has been done.

In this embodiment, the sense amplifier SA is shown as a sense latch SL because it has an amplifying operation and a data holding function. The sense latch is composed of a CMOS inverter circuit in which inputs and outputs are cross-connected and such a CMOS inverter circuit, and the CMOS inverter circuit is selectively operated by supplying activation voltages VSAP and VSAN. Be put in a state.

A pair of input / output nodes of the sense latch SL are commonly provided for a MOSFET switch-controlled by a selection signal formed by a Y decoder (YG Dec) and the adjacent odd and even switch MOSFETs. And a pair of input / output lines IOL and IOR via a switch MOSFET. The switch MOSFET provided in common is switch-controlled by a selection signal formed by a Y-system predecoder (YPG Dec) provided between the sense latch trains. Thus, the Y gate is composed of two MOSFETs whose switches are controlled by the selection signals of the two Y system decoders.

In the figure, a predecoder is provided for each sense latch column corresponding to four data lines in order to facilitate understanding of the invention. As shown in the figure, the predecoder as a Y-system subdecoder is provided in a space between the sense latch rows SL for each small memory mat, in other words, in an empty area corresponding to the X-system subdecoder SUB Dec. By separating the Y-system decoder in this way, the number of selection signal lines supplied to the gate of the column switch MOSFET can be reduced. That is, the column switch M
It is necessary to make a wiring area wide by arranging a large number of selection signal lines corresponding to the number of OSFETs in parallel with the sense latch column, but the number of wirings is reduced by dividing the Y decoder into two as described above. be able to.

A precharge signal RPC is applied to the data line DL.
2 and RPC1 receive precharge MOSFE respectively
T is provided. A transfer MOSFET controlled by selection signals TR1 and TR2 is provided between the data line DL and the input / output node of the sense amplifier. The right side circuit of the sense latch SL corresponding to these MOSFETs is omitted.

Although not shown in the figure, the pair of inputs of the sense latch has an input node M set to 0V.
An OSFET is provided. As a result, the input signal is set to 0V before the amplification operation is started. The pair of inputs of the sense latch SL is the transfer MOSF.
The data lines DL01L to DL04L and the like are connected via ET. The transfer MOSFET includes odd-numbered data lines DL01L and DL03L and an even-numbered data line D.
It is divided into two corresponding to L02L and DL04L, and selection signals TR1 and TR2 are respectively supplied. Correspondingly, the gates of the precharge MOSFETs provided in the odd data lines DL01L and DL03L are supplied with the precharge voltage RPC1, and the gates of the precharge MOSFETs provided in the even data lines DL02L and DL04L are supplied with the precharge voltage. RPC2 is supplied.

In this embodiment, like the above, when one of the pair of memory mats is activated, the other is deactivated. In this inactivated memory mat, the transfer MOSFET is turned on and the corresponding data line is connected to the input of the sense amplifier, although it is inactivated. Then, as described above, on the non-active memory mat side, the precharge voltage of the data line is set low so as to be an intermediate potential between the high level and the low level of the data line of the activated memory mat. In this way, the data line of the memory mat on the inactive side is used as the reference voltage of the sense amplifier.

Although not particularly limited, in response to the sense latch SL being composed of a CMOS latch circuit,
During a write operation, write data is held in each latch. That is, the Y gate YG is sequentially opened to set write data, and then the even-numbered and odd-numbered transfer MOSFETs are simultaneously turned on to simultaneously perform the write operation.
In accordance with such a write operation, the operating voltage of the sense amplifier is switched to a voltage such as 4V corresponding to the write voltage. On the other hand, at the time of read operation and write verify, even-numbered and odd-numbered data lines are alternately activated in a zigzag pattern except for the first memory cycle, thereby enabling pipeline continuous access.

FIG. 5 shows a layout diagram in the direct peripheral portion of the memory mat of an embodiment of the batch erasing type nonvolatile memory device according to the present invention. Sense latches SL are arranged vertically in the central portion of the vertically long area. Two memory mats are provided sandwiching the row of sense latches SL. The memory mats divided into the above two are small memory mats MAT0L to MAT7L and MA, respectively.
It is composed of T0R to MAT7R. Small memory mat M
Memory mats for redundant data lines and management bits are provided above the AT0L and MAT0R.

X-system sub-decoders SUB-Dec are arranged on both sides of the small memory mat. A discharge MOSF is placed between the small memory mat and the periphery of the left chip.
ET (DMOS) and source MOSFET (SMOS)
Is provided. The main decoder (M
ain Dec) is arranged. A gate decoder (Pre Dec) is provided at the upper left end of the gate decoder, and a driver circuit for driving the DMOS and SMOS is provided below the gate decoder.

The sense latch SL shown in the figure also includes the Y gate as described above. A Y-system decoder YG Dec is arranged on the upper portion corresponding to the Y gate portion, and the X-system sub-decoder SUB D is provided between the sense latches SL.
A predecoder YPG Dec as a Y-system sub-decoder is provided in a portion corresponding to ec.

1 and 2 are schematic layout diagrams of one embodiment of a memory cell array portion of a batch erase type nonvolatile memory device to which the present invention is applied. 1 and 2
1 and FIG. 2 are the upper and lower parts of the cut-back pattern, which are the central part to facilitate understanding of the mutual relationship.
Of the joints are shown as overlapping one another.

1 and 2, the switch MOSFET QS on the source side and the switch MOSFET QD on the memory side and the drain side are arranged symmetrically with respect to the common source contact row in the center. Further, with respect to the drain / well contact row, which is the upper end of FIG. 1, the lower pattern of FIGS. 1 and 2 is symmetrically arranged on the upper side (not shown). A drain similar to the above, which is the lower end of FIG.
The upper pattern shown in FIGS. 2 and 1 is symmetrically arranged on the lower side (not shown) centering on the well contact row. A memory mat MAT as shown in FIG. 3 is configured by such a repeating pattern.

Referring to FIG. 1 as an example, the memory section forms a word line connected to the control gate.
A plurality of second-layer polysilicon layers SG are extended in the vertical direction of FIG. 1 corresponding to the blocks. In the figure, the word lines forming the data lines at both ends of the memory block are shown as an example, and a plurality of word lines to be arranged therebetween are omitted.

A bit line (data line) BL made of a metal wiring layer M1 made of aluminum or the like in the first layer is extended in the lateral direction so as to be orthogonal to the word line. In the lower part where the data line BL and the word line overlap, in other words, the drain diffusion layer and the source diffusion layer are formed in common along both sides of the data line BL, and 2 are formed under the word line WL. A storage transistor having a layer gate structure is formed. This will be apparent from the pattern diagram and the sectional view according to the manufacturing process sequence described later.

The gate electrodes of the drain side switch MOSFET (STMOS) and the source side switch MOSFET (STMOS) are integrally formed on both ends of the memory through a remaining gate (buffer dummy wiring) which will be described later. Second polysilicon layer SG (SID and SI formed)
S) are respectively formed. These second polysilicon layers (SID and SIS) are used as the main word lines.

The drain / well contact column connects the data line BL to one of the drain and the source of the switch MOSFET on the drain side. This switch MO
The other source and drain of the SFET are connected to a common drain region of the plurality of storage transistors forming the one block by a diffusion layer. In this embodiment, the common source line SL is arranged between the plurality of data lines. The common source line SL is composed of the same first metal wiring layer M1 as the data line BL, has the same conductivity type as the well region on the semiconductor substrate below the contact hole, and is connected to the ohmic contact region. To be done. That is, the memory array of this embodiment is formed in the well region in order to change the substrate potential on which the memory transistor is formed according to the operation mode in order to perform the erase / write using the tunnel current as described above. The common source line is electrically connected to the well region.

The source contact row connects the common source line SL to one of the drains and sources of the switch MOSFETs on the source side. Source side switch MOS
In the FET, one source and drain of a plurality of switch MOSFETs formed side by side in the word line direction are commonly formed by extending in the extension direction of their gate electrodes. Connected to the common source line SL. Switch MOS above
The other drain and source of the FET are connected to a common source region of a plurality of storage transistors forming the one block by a diffusion layer.

The remaining gate is provided for the following reason. A self-alignment technique using the second polysilicon layer SG as a mask is used in order to form the two-layer gate forming the memory transistor with high density. on the other hand,
Also in the switch MOSFET, a self-alignment technique is used in which the drain and the source thereof are masked by the second polysilicon layer SG. However, in the above-mentioned memory transistor having the two-layer gate structure, it is necessary to etch a relatively thick thickness under the second-layer gate electrode, such as the interlayer insulating film and the first-layer gate electrode. Against
In a MOSFET with a single-layer gate structure, since only a thin oxide film exists on a semiconductor substrate on which a source and a drain are to be formed, simultaneous etching causes formation of a source and a drain on the MOSFET side with a single-layer gate structure. The problem arises that the surface of the substrate to be etched is also etched.

In the case of using a memory transistor having a two-layer gate structure such as a conventional EPROM, the field insulating film for element isolation is used as a buffer area so that there is no problem even if the above-mentioned excessive etching is performed. However, in the structure in which the MOSFET of the single-layer gate structure is arranged close to the storage transistor of the double-layer gate structure as in this embodiment, the integration degree may be lowered if the field insulating film as described above is formed. Besides, it becomes impossible to connect the common drain side or the common source side of the memory transistor to the source and drain to be connected to that of the switch MOSFET by using the diffusion layer.

Even if the field insulating film can be formed narrowly, the common drain and common source of the memory transistor and the drain side switch MOSFET and the source side switch MOSFET are formed by the polysilicon or metal wiring layer. The connection is unavoidable, and the contact area is provided so that the degree of integration is reduced. In order to solve such problems,
The remaining gate is provided. The structure of the residual gate and its role will be described in detail with reference to FIGS.

FIGS. 6 to 21 show a pattern diagram and a sectional view according to the manufacturing process order of the memory transistor, the remaining gate and the switch MOSFET. In the sectional view, the word line direction corresponding to aa 'in the pattern diagram is shown as (A), and the data line direction corresponding to bb' in the pattern diagram is shown as (B). In addition, in FIGS. 6 to 21 described below, in order to make the drawings easy to see, symbols are attached to main portions formed in the steps of the respective drawings, and symbols already described are omitted.

As shown in the pattern diagram of FIG. 6, the field insulating film 1 is formed. That is, as shown in FIG. 7A, a silicon nitride film (Si ₃ N ₄ ) is formed after the well is formed.
To form the field insulating film 1. After removing the sacrificial oxide film, a memory gate oxide film (SiO ₂ ) 2 is formed. The film thickness of this memory gate oxide film 2 is 7-1.
It is thinly formed so that a tunnel current of 0 nm flows. In (B), only the memory gate insulating film 2 is shown.

As shown in the pattern diagram of FIG. 8, a silicon nitride film (CVD-Si ₃ N ₄ ) 4 and a first phosphorus-doped polysilicon film 3 thereunder are formed. The silicon nitride film 4 and the first-layer phosphorus-doped polysilicon film 3 thereunder are patterned so as to form the source and drain of the memory transistor, and a region on the common drain side of a switch MOSFET formed later. MO on the switch side up to the portion where the source and drain are formed (upper side in FIG. 8)
It is formed so as to extend toward the SFET. Switch M
The region where the OSFET is formed covers the entire surface.

As shown in the sectional view (A1) of FIG.
A layer phosphorus-doped polysilicon film (lower floating gate) 3 is formed. The film thickness of the first layer phosphorus-doped polysilicon film 3 is set to about 100 nm. A silicon nitride film (CV) is formed on the first phosphorus-doped polysilicon layer 3.
D-Si ₃ N _{4) 4} is formed. After forming these,
As shown in the pattern diagram of FIG. 8 described above, the source and drain portions of the memory (memory transistor) are opened and etched. Then, after forming the light oxide film 5, the source and drain portions are separately opened by using a resist film, and a diffusion layer constituting the drain 6 and the source 7 which are shared by the memory transistors is formed by ion implantation and annealing. .

As shown in (A2), CVD-SiO ₂
After forming the film, the sidewall 8 is formed at the end of the memory gate by etching back the entire surface. As shown in (A3), a drain doped with As by thermal oxidation,
An oxide film 9 is selectively formed on the source. At this time, the sidewall 8 plays a role of a stopper so that the end of the memory gate is not oxidized. In the above steps (A1) to (A3), as shown in FIG.
The SFET portion is covered with the first layer phosphorus-doped polysilicon layer 3 and the silicon nitride film (CVD-Si ₃ N ₄ ) 4. In addition, the memory transistors of different blocks are
As in (A1) to (A3), the first-layer gate electrode (floating gate) is separated, but the gate electrodes in the same block remain integrally formed as in (B). .

As shown in the pattern diagram of FIG. 10 and the sectional view of FIG. 11, the silicon nitride film (CVD-Si ₃ N ₄ ) 4 is completely removed by immersing in hot phosphoric acid. As a result, the first-layer phosphorus-doped polysilicon film (lower floating gate) 3 and the sidewall 8 are left.

As shown in the pattern diagram of FIG. 12, the second layer phosphorus-doped polysilicon film 10 is formed. The second-layer phosphorus-doped polysilicon film 10 constitutes the upper floating gate and has a film thickness of about 40 to 100 nm. This second layer phosphorus-doped polysilicon film 1
0 is removed on the field insulating film in the portion where the memory is formed, and the gate is separated between blocks.

As shown in the sectional view (A) of FIG. 13, the floating gate of the storage transistor is the first layer phosphorus-doped polysilicon film (lower floating gate).
3 and the second-layer phosphorus-doped polysilicon film 10 formed thereon are T-shaped so as to cover the upper portions of the source and drain. As described above, the memory transistors of different blocks are separated on the field insulating film, but the gate electrodes of the same block have the same switching MOSF as above.
It remains integrally formed as in (B) including the peripheral portion where ET is formed.

As shown in the pattern diagram of FIG. 14, the portion where the switch MOSFET is formed is removed by etching with the boundary between the substantially central portions of the portions which will be the remaining gates after the interlayer insulating film 11 is formed. That is, as shown in the sectional view (B1) of FIG. 15, the interlayer insulating film 11 is formed on the second-layer phosphorus-doped polysilicon film 10. This insulating film 11 is formed from the bottom by SiO ₂ / Si ₃ N ₄ / SiO ₂ /
Four layers of Si ₃ N ₄ are formed by CVD, and the respective film thicknesses are 5 nm / 10 nm / 3 nm / 10 n from the bottom.
m, respectively.

As shown in (B2), the interlayer insulating film 11 and the first layer in the portion where the switch MOSFET is formed so as to cover the memory portion with the center of the portion that will be the remaining gate as a boundary are formed. Second layer Phosphorus-doped polysilicon layer 3
And 10 are etched away.

As shown in (B3), the switch MOSFET and the peripheral MOSFET are formed after the sacrificial oxide film is formed and removed.
To form the gate oxide film 12. At this time, on the memory side, since the uppermost Si ₃ N ₄ of the interlayer insulating film 11 serves as a mask, it is not oxidized or removed.

As shown in the pattern diagram of FIG. 16 and the sectional view of FIG. 17, the third-layer polycide film 13 is formed. That is, the third-layer polycide film 13 is formed from a silicide / CV of phosphorus-doped Si / WSi ₂ , MoSi ₂ or the like in order from the bottom.
It is made of D-SiO ₂ , and each film thickness is 1 from the bottom.
It is formed as 00 nm / 150 nm / 300 nm.

The third-layer polycide film 13 has a word line, a switch MOSFET, and a peripheral MOSFE (not shown).
The T gate and the portions covering the first and second polysilicon stepped portions are removed by etching. The portion that covers the first and second polysilicon step portions formed in the steps of FIGS. 14 and 15 is the remaining gate. This remaining gate is used as a buffer area for buffering the mask shift, and since it is made of the same wiring material as the word line, it can be called a buffer dummy wiring.

As shown in the pattern diagram of FIG. 18 and the sectional view of FIG. 19, the switch MOSFET and the peripheral MOSFET except for the memory section are covered with a resist film or the like at the remaining gate as a boundary, and the memory section and the remaining gate are covered. By the self-alignment in which the memory side end is the mask of CVD-SiO ₂ of the third-layer polycide film 13, the interlayer insulating film 11 and the second
The polysilicon layer 10 and the first polysilicon layer 3 are removed by etching. In such deep etching, the switch MOSFET and the peripheral MOSFET are covered with the resist film but are not etched.

As shown in the pattern diagram of FIG. 20 and the sectional view of FIG. 21, the memory side is covered with a resist film or the like, and in the switch MOSFET and the peripheral MOSFET, the CVD-SiO ₂ of the third layer polycide film 13 is used as a mask. The source and drain are opened by self-alignment to diffuse and form the source and drain 14. At this time,
(C) The source and drain on the memory side are formed so as to overlap with the common source and drain diffusion layer 6 (source diffusion layer 7 in the switch MOSFET on the source side) which is a memory diffusion layer.

At this time, the switch MOSFET and the peripheral M
The OSFET may have an LDD structure or a single drain structure. In the figure, the sidewall 15
Is shown to form an LDD structure. Note that C
N-channel type MOSFET and P forming a MOS circuit
The channel type MOSFET is formed so as to cover the other when forming one. After this, the metal wiring layer forming the data line DL and the source line SL is formed.

As shown in the cc 'sectional view of (C) above, one of the source / drain regions 14 to be connected to the common drain 6 or the source of the memory transistor of the switch MOSFET is on the memory side. Common drain region and common source region of the switch MOSFET
Since the third layer polycide film 13 is formed so as to extend to the side, the third layer polycide film 13 is formed so as to overlap when the source and drain are diffused by self-alignment using CVD-SiO ₂ as a mask, and are electrically connected. It This also applies to the connection between the common source region 7 on the memory side and the source / drain 14 of the switch MOSFET provided corresponding thereto.

The remaining gate thus formed can be used as a buffer area in terms of process,
The switch MOSFE is provided by grounding the remaining gate by AC so that the ground potential of the circuit is constantly applied.
A function of preventing the selection / non-selection signal of the main word line supplied to the gate of T from acting as noise on the word line side to which the control gate of the memory transistor arranged adjacent to the switch MOSFET is connected. Can be fulfilled As a result, the storage MOSFETs and the switch MOSFETs can be arranged in high density both in terms of layout and electrically.

The effects obtained from the above embodiment are as follows. That is, (1) a buffer dummy having a double-layer gate structure side and a single-layer gate structure side between the double-layer gate structure MOSFET and the single-layer gate structure MOSFET. By providing the wiring layer, patterning by self-alignment of the double-layer gate structure and self-alignment of the source and drain of the single-layer gate structure can be performed while absorbing the mask shift in the buffer dummy wiring portion. It is possible to obtain the effect that the diffusion layer and the diffusion layer can be separately formed with high density.

(2) The gate electrode of the first layer constituting the MOSFET having a two-layer gate structure is integrally formed, and the insulating film is formed on the gate electrode of the first layer, and the buffer region is almost formed. A gate insulating film forming a MOSFET having a single-layer gate structure is formed with the center as a boundary, and an MO having a double-layer gate structure is formed.
A second-layer gate electrode that constitutes the SFET and a gate electrode that constitutes the above-mentioned MOSFET of the one-layer gate structure are simultaneously formed, and are provided between the above-mentioned MOSFET of the two-layer gate structure and the MOSFET of the one-layer gate structure. The gate electrode of the two-layer structure is substantially patterned by self-alignment using the one-layer structure side as a mask with the center of the buffer region as a boundary and the second-layer gate electrode as a mask. A one-layer structure MOSFE by self-alignment using the gate electrode as a mask
By the manufacturing method in which the source and the drain of T are diffused, the mask displacement at the dummy wiring for buffer is absorbed and the self-alignment of the two-layer gate structure is performed.
Layer gate structure MOSFET and single layer gate structure MOS
The effect that the FET and the FET can be formed at high density is obtained.

(3) Due to the relative potential relationship between the control gate connected to the word line and the data line connected to the drain, the charge of the floating gate is discharged to lower the threshold voltage of the memory, and the high voltage is applied to the control gate. A plurality of storage transistors are connected in parallel to increase the threshold voltage of the memory in word line units by injecting charges into the floating gate according to the relative potential relationship with the source or substrate potential. Common drain of each storage transistor is connected to a corresponding data line via a switch MOSFET, and common sources of the plurality of storage transistors are switch MOSFEs.
In a memory array connected to a source line via T, a storage transistor having a two-layer gate structure,
By providing a buffer dummy wiring layer having a two-layer gate structure on the memory transistor side with the switch MOSFET having a one-layer gate structure and the switch MOSFET having a one-layer gate structure, diffusion on the semiconductor substrate is achieved. There is an effect that both layers can be connected by using the layer and that both MOSFETs can be formed at high density.

(4) By applying an AC ground potential to the buffer dummy wiring layer, the word line to which the control gate of the memory transistor is connected and the gate of the switch MOSFET are connected. The effect of preventing the occurrence of coupling noise with the select line (main word line) is obtained.

(5) The storage transistor and the switch MOSFET are formed in the well, and the switch MOSFET provided in the common drain
The other end of is connected to a data line composed of a metal wiring layer, and the common source line is composed of the metal wiring layer composed of the same wiring layer and extended in parallel, and the metal wiring that composes the common source line. Stabilizing the well potential setting by providing a well contact semiconductor region on the underlying semiconductor substrate and obtaining a contact between the common source line and the well in the same arrangement as the contact of the data line and the switch MOSFET. The effect that it can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the gate wiring material of the first layer or the second layer, or the interlayer insulating film material between them can adopt various embodiments, and any manufacturing method thereof can be used. Memory MOSF
The ET and the switch MOSFET connected to the ET include a batch erase type nonvolatile memory device in which writing and erasing are performed using the tunnel current as described above, a MOSFET having a two-layer gate structure, and a one-layer gate structure connected to the MOSFET. MO
It can be widely used for semiconductor integrated circuit devices provided with SFET.

[0061]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a MOSF having a two-layer gate structure
By providing a buffer dummy wiring layer having a two-layer gate structure side on the two-layer gate structure side and a one-layer gate structure on the one-layer gate structure side between the ET and the MOSFET of the one-layer gate structure, Patterning by self-alignment of the double-layer gate structure and diffusion layer by self-alignment of the source and drain of the single-layer gate structure are separately formed at high density while absorbing the mask shift in the buffer dummy wiring portion. can do.

A first-layer gate electrode forming a MOSFET having a two-layer gate structure is integrally formed, an insulating film is formed on the first-layer gate electrode, and a buffer region is formed at a substantially central portion. Forming a gate insulating film forming a MOSFET having a one-layer gate structure, and a MOSFET having a two-layer gate structure
The second-layer gate electrode that constitutes the
Each of the gate electrodes constituting the OSFET is formed at the same time, and the one-layer structure side is masked with the buffer region provided between the two-layer gate structure MOSFET and the one-layer gate structure MOSFET as a boundary. Then, the gate electrode having a substantially two-layer structure is patterned by self-alignment using the second-layer gate electrode as a mask, and the one-layer structure is formed by self-alignment by masking the two-structure side and using the gate electrode as a mask. By the manufacturing method for performing the diffusion of the source and drain of the MOSFET of
While absorbing the mask shift in the buffer dummy wiring part,
The two-layer gate structure MOSFET and the one-layer gate structure MOSFET can be formed at high density by self-alignment of the two-layer gate structure.

The charge of the floating gate is discharged by the relative potential relationship between the control gate connected to the word line and the data line connected to the drain to lower the threshold value of the memory, and a high voltage is applied to the control gate. A plurality of storage transistors are connected in parallel to increase the threshold voltage of the memory in word line units by injecting charges into the floating gate according to the relative potential relationship with the source or substrate potential. In the memory array in which the common drain of each of the storage transistors is connected to the corresponding data line via the switch MOSFET, and the common sources of the plurality of storage transistors are connected to the source line via the switch MOSFET.
Between the storage transistor having the layer gate structure and the switch MOSFET having the one-layer gate structure, the storage transistor side has the two-layer gate structure, and the switch MOSF
By providing a buffer dummy wiring layer having a single-layer gate structure for the ET, both can be connected using the diffusion layer on the semiconductor substrate,
The FET can be formed with high density.

By applying an AC ground potential to the buffer dummy wiring layer, a word line to which the control gate of the memory transistor is connected and a selection line (to which the gate of the switch MOSFET is connected ( It is possible to prevent the generation of coupling noise with the main word line).

Storage transistor and switch MOS
The FET is formed in the well, and the other end of the switch MOSFET provided in the common drain is connected to the data line made of a metal wiring layer and is made of the same wiring layer and extended in parallel. The metal wiring layer constitutes the common source line, and a well contact semiconductor region is provided on the semiconductor substrate below the metal wiring layer constituting the common source line.
By setting the contact between the common source line and the well in the same arrangement as the contact of the OSFET, the setting of the well potential can be stabilized.

[Brief description of drawings]

FIG. 1 is a partial schematic layout diagram of an embodiment of a memory cell array section of a batch erase type nonvolatile memory device to which the present invention is applied.

FIG. 2 is a schematic partial layout diagram of the remaining part of the embodiment of the memory cell array portion of the batch erase type nonvolatile memory device to which the present invention is applied.

FIG. 3 is a schematic circuit diagram showing one embodiment of a memory mat and its peripheral portion in the batch erase nonvolatile memory device according to the present invention.

FIG. 4 is a schematic circuit diagram showing one embodiment of a sense amplifier and its peripheral portion in the batch erase nonvolatile memory device according to the present invention.

FIG. 5 is a layout diagram of a memory mat direct peripheral portion of an embodiment of a batch erasing type nonvolatile memory device according to the present invention.

FIG. 6 is a pattern diagram according to the manufacturing process order of the storage transistor, the remaining gate, and the switch MOSFET.

7 is a cross-sectional view corresponding to aa 'and bb' in FIG.

FIG. 8 is a pattern diagram according to the manufacturing process order of the storage transistor, the remaining gate, and the switch MOSFET.

9 is a cross-sectional view corresponding to aa 'and bb' in FIG.

FIG. 10 is a pattern diagram according to the manufacturing process order of the storage transistor, the remaining gate, and the switch MOSFET.

11 is a cross-sectional view corresponding to aa 'and bb' in FIG.

FIG. 12 is a pattern diagram according to the manufacturing process order of the memory transistor, the remaining gate, and the switch MOSFET.

13 is a cross-sectional view corresponding to aa ′ and bb ′ of FIG.

FIG. 14 is a pattern diagram according to the manufacturing process order of the memory transistor, the remaining gate, and the switch MOSFET.

15 is a cross-sectional view corresponding to aa 'and bb' in FIG.

FIG. 16 is a pattern diagram according to the manufacturing process order of the storage transistor, the remaining gate, and the switch MOSFET.

17 is a cross-sectional view corresponding to aa 'and bb' in FIG.

FIG. 18 is a pattern diagram according to the manufacturing process order of the memory transistor, the remaining gate, and the switch MOSFET.

19 is a cross-sectional view corresponding to aa 'and bb' in FIG.

FIG. 20 is a pattern diagram according to the manufacturing process order of the memory transistor, the remaining gate, and the switch MOSFET.

21 is a cross-sectional view corresponding to aa ′, bb ′, and cc ′ of FIG. 20.

[Explanation of symbols]

MAT, MAT0L to MAT7R ... Small memory mat, S
UB-DEC ... Sub-decoder, MAN-DEC ... Main decoder, SL ... Sense latch circuit, YPGDEC ... Y
Predecoder, YG Dec ... Y decoder. DESCRIPTION OF SYMBOLS 1 ... Field insulating film, 2 ... Memory gate oxide film, 3 ... 1st layer phosphorus dope polysilicon film, 4 ... Silicon nitride film, 5 ... Write oxide film, 6 ... Memory drain diffusion layer, 7 ... Memory source diffusion layer, 8 ... Sidewalls, 9 ... Oxide film, 10 ... Second layer phosphorus-doped polysilicon film, 11 ... Interlayer insulating film, 1
2 ... Gate insulating film of switch MOSFET, 13 ... Third
Layer Polycide film, 14 ... Source / drain diffusion layer of switch MOSFET, 15 ... Sidewall.

Claims (5)

[Claims] 1. A MOSFET having a two-layer gate structure and a MOSFET having a one-layer gate structure arranged in the vicinity thereof are provided, and provided between the MOSFET having the two-layer gate structure and the MOSFET having one-layer gate structure. A semiconductor integrated circuit device comprising a buffer dummy wiring layer having a double-layer gate structure side and a single-layer gate structure side having a single-layer gate structure. 2. The charge of the floating gate is discharged by the relative potential relationship between the control gate connected to the word line and the data line connected to the drain to lower the threshold voltage of the memory, and a high voltage is applied to the control gate. A plurality of storage transistors are connected in parallel, which are applied to inject charges into the floating gate according to the relative potential relationship with the source or substrate potential to raise the threshold value of the memory in word line units. A memory array is provided in which common drains of the storage transistors are connected to corresponding data lines via switch MOSFETs, and common sources of the plurality of storage transistors are connected to source lines via switch MOSFETs. , The memory transistor has a two-layer gate structure, and the switch MOSFET has one layer A semiconductor having a gate structure, wherein a buffer dummy wiring layer having a two-layer gate structure on the memory transistor side and a switch MOSFET having a one-layer gate structure is provided between the memory transistor and the switch MOSFET. Integrated circuit device. 3. The semiconductor integrated circuit device according to claim 2, wherein an alternating ground potential is applied to the buffer dummy wiring layer. 4. The memory transistor and the switch MO.
The SFET is formed in the well, and the other end of the switch MOSFET provided in the common drain is connected to the data line made of a metal wiring layer and is made of the same wiring layer and extends in parallel. The metal wiring layer constitutes the common source line, and a semiconductor region for well contact is provided on the semiconductor substrate below the metal wiring layer constituting the common source line, and the data line and the contact of the switch MOSFET are arranged in the same arrangement. 3. The semiconductor integrated circuit device according to claim 2, wherein the contact between the common source line and the well is obtained. 5. A step of integrally forming a first-layer gate electrode forming a MOSFET having a two-layer gate structure, a step of forming an insulating film on the first-layer gate electrode, and a step of forming a buffer region. MOSF with a single-layer gate structure with almost the center as a boundary
A step of forming a gate insulating film forming ET, a step of simultaneously forming each of a second layer gate electrode forming a MOSFET having a two-layer gate structure and a gate electrode forming the MOSFET having a one-layer gate structure, Substantially by self-alignment using the second layer gate electrode as a mask by masking the one layer structure side with the buffer region provided between the MOSFET of the one layer gate structure and the MOSFET of the one layer gate structure as a boundary. Patterning a gate electrode having a two-layer structure, and a step of masking the two-structure side and diffusing the source and drain of a one-layer MOSFET by self-alignment using the gate electrode as a mask. A method for manufacturing a semiconductor integrated circuit device, comprising: