JPH07169918A - Semiconductor device with protection circuit - Google Patents

Abstract

PURPOSE:To inhibit the generation of parasitic bipolar current and prevent deterioration even when overvoltage is applied by using only a p channel MOSFET for a protection circuit which is designed to prevent the application of over voltage added from the outside upon an internal circuit. CONSTITUTION:A signal line 3, which is connected to an outside circuit and connected to a pad 1 which an outside signal is inputted, is connected to a sate electrode 25 of MOSFET 2 of an internal circuit. The signal line 3 is connected to power supply voltage Vdd by way of pMOS 4 and it is also connected to reference voltage Vss by way of pMOS 5. More specifically, outside signal voltage is turned into overvoltage which exceeds the power supply voltage Vdd, the polarity between source and drain electrodes of the pMOS 4 will be inverted. Since the gate electrode is connected to the source electrode S4 at that time, no overvoltage will be applied to the internal circuit due to an on-state which is produced when voltage is applied to a drain electrode D4, which exceeds a total sum of the power supply voltage Vdd and a threshold voltage value Vth of the pMOS 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an ultra thin semiconductor layer (S) on an insulating surface.
The present invention relates to a protection circuit for protecting an internal circuit when an excessive voltage such as static electricity is applied to the integrated circuit formed in OI).

[0002]

2. Description of the Related Art As a protection circuit for an excessive voltage due to static electricity of a MOS type IC, a field MOSFET type,
A clamp type MOSFET type, a CMOS buffer circuit type and the like are known.

FIG. 6A is a circuit diagram of a field MOSFET type protection circuit, and FIG. 6B is a sectional view thereof.
As shown in FIG. 6A, a pad 100 for inputting an external signal is connected to an internal circuit such as a gate electrode of the MOSFET 102 by a signal line 103. The signal line 103 is connected to the reference voltage Vss via the field MOSFET 101 having a thick field oxide film as a gate insulating film. Field MOSFET 1
The gate electrode of 01 is connected to the signal line 103 side.

As shown in FIG. 6B, the field MO
SFET101 and MOSFET102 of the internal circuit,
For example, it is formed in the p-type well 111 formed on the surface of the silicon substrate 110. Each element in the p-well is
It is separated by the field oxide film 112.

A field oxide film is used for the gate insulating film of the field MOSFET 101. The gate electrode 115 on the field oxide film 112 is the interlayer insulating film 11
Pad 100 through the contact hole provided in FIG.
Is connected to the wiring 114. The wiring 114 is connected to the electrode (drain electrode) on the side opposite to the reference voltage Vss of the field MOSFET 101.

The field oxide film 112 is the M of the internal circuit.
Since it is thicker than the gate insulating film used for the OSFET 102, the threshold voltage Vth1 of the field MOSFET 101 is
Is higher than the threshold voltage Vth2 of the MOSFET 102 in the internal circuit. Therefore, the field MOSFET 101 is
It does not operate at a normal voltage equivalent to the threshold voltage Vth2 of the MOSFET 102 in the internal circuit, and becomes conductive only when an excessive voltage equal to or higher than the threshold voltage Vth1 is applied. In this way, an excessive voltage equal to or higher than the threshold voltage Vth1 is prevented from being directly applied to the internal circuit.

However, the threshold voltage of the field MOSFET is usually quite high, and the threshold voltage Vth2 of the MOSFET 102 in the internal circuit and the threshold voltage Vth of the field MOSFET are high.
The voltage between th1 and the field MOSFET 101 does not become conductive. Therefore, the protection function does not work, and there is a voltage region where an excessive voltage is applied to the gate electrode of the MOSFET 102 in the internal circuit.

FIG. 7A is a circuit diagram of a clamp type protection circuit, and FIG. 7B is a sectional view thereof. The circuit shown in FIG. 7A has a field MOSFET 101 of the field MOSFET type protection circuit shown in FIG.
It is replaced with the OSFET 104. Clamp M
The gate electrode of the OSFET 104 is connected to the reference voltage Vss.

As shown in FIG. 7B, the clamp MOS
The gate electrode 116 of the FET 104 is connected to the electrode (source electrode) on the side of the reference voltage Vss via the wiring 117. The wiring 114 from the pad 100 is a clamp MOS.
Drain electrode of FET 104 and MOSFE of internal circuit
It is connected to the gate electrode of T102.

Since the gate electrode of the clamp MOSFET 104 is connected to the potential of the source electrode, it is normally off. However, when a voltage higher than the punch-through voltage is applied to the drain electrode, a depletion layer around the drain region develops and reaches the source region, and the potential barrier between the source and drain regions disappears, and punch-through current flows.

Therefore, by selecting the punch-through voltage lower than the threshold voltage Vth1 of the field MOSFET type protection circuit of FIG. 6, it is possible to lower the lower limit of the excessive voltage which functions as the protection circuit. However, even in this case, the clamp protection circuit does not function as a protection circuit at a voltage between the threshold voltage Vth2 of the MOSFET 102 of the internal circuit and the punch through voltage.

As a method for solving the above problems, the CMO
S-buffer protection circuits are known. FIG. 8A shows C
A circuit diagram of the MOS buffer protection circuit, FIG. 8B is a cross-sectional view thereof.

As shown in FIG. 8A, the signal line 103 connected to the pad 100 is an n-channel MOSFET.
(Hereinafter referred to as nMOS) 106 through the reference voltage Vss
And a p-channel MOSFET (hereinafter referred to as pMO
It is called S. ) 105 to the power supply voltage Vdd.

For convenience of explanation, the power supply voltage Vdd side electrode of the pMOS 105 is the source electrode S105, the wiring 103 side electrode is the drain electrode D105, the reference voltage Vss side electrode of the nMOS 106 is the source electrode S106, and the wiring 103 side electrode is the drain. This is designated as electrode D106. pMOS105
And the gate electrode of the nMOS 106 are connected to the source electrode S105 and the source electrode S106, respectively.

As shown in FIG. 8B, the silicon substrate 1
In the n-type well 118 formed on the surface of the
5, the nMOS 106 and the MOSFET 102 of the internal circuit are formed in the p-type well 111.

The drain electrode D105 of the pMOS 105 and the drain electrode D106 of the nMOS 106 are connected to the wiring 114 extending from the pad 100 through a contact hole provided in the interlayer insulating film 113. pM
The source electrode S105 and the gate electrode of the OS 105 are connected to the power supply voltage Vdd, and the source electrode S1 of the nMOS 106 is
06 and the gate electrode are connected to the reference voltage Vss.

When a normal voltage higher than the reference voltage Vss and lower than the power supply voltage Vdd is applied, the pMOS 10
5 and the nMOS 106 are off. Therefore, the applied voltage is directly applied to the internal circuit.

When an excessive voltage higher than the power supply voltage Vdd is applied to the pad 100, the polarity between the source and drain electrodes of the pMOS 105 is inverted. At this time, since the gate electrode is connected to the source electrode S105 which has a relatively low voltage, the drain electrode D105 is connected to the power supply voltage Vdd and pM.
When a voltage equal to or higher than the sum of the threshold voltage Vth of the OS 105 is applied, it is turned on. Therefore, no voltage higher than the sum of the power supply voltage Vdd and the voltage drop due to the pMOS 105 is applied to the internal circuit.

Similarly, when a negative excessive voltage of the threshold voltage Vth of the nMOS 106 or more than the reference voltage Vss is applied to the pad 100, the nMOS 106 is turned on, and the internal circuit of the nMOS 106 is higher than the reference voltage Vss. Excessive negative voltage above the threshold voltage is not applied.

[0020]

The CMOS type buffer protection circuit described above is generally used in an integrated circuit using a normal semiconductor substrate. However, if this protection circuit is applied to an integrated circuit in which a MOSFET is formed on an ultra-thin SOI semiconductor layer on an insulating surface, the following problems occur.

When a large drain current flows through the nMOS, electron-hole pairs are generated in the channel portion by impact ionization. In the case of an nMOS formed in a p-type well or the like on the surface of a semiconductor substrate, the generated holes are discharged through the p-type well. However, when it is formed on the SOI, it is not discharged through the well, and holes are accumulated in the channel portion.

The accumulated holes increase the potential of the channel portion. This becomes a forward bias of the pn junction between the channel portion and the source region. Considering the operation of the npn transistor in which the source region, the channel region and the drain region are regarded as the emitter, the base and the collector, respectively, the forward bias causes a base current to flow. As a result, a large collector current (parasitic bipolar current) flows from the source region to the drain region.

When a parasitic bipolar current flows, MOSF
ET becomes an oscillating state and an excessive current flows. as a result,
It causes deterioration of the gate insulating film and deterioration of the drain pn junction,
This causes deterioration of the device characteristics of the MOSFET itself. In particular, since an excessive voltage due to static electricity reaches several hundreds of volts, an excessive parasitic bipolar current flows through the CMOS buffer protection circuit itself having the SOI structure, which easily causes deterioration.

It is an object of the present invention to provide a semiconductor device having a highly reliable protection circuit which is unlikely to deteriorate even when an excessive voltage is applied.

[0025]

[Means for Solving the Problems] The means for solving the problems will be described below with reference numerals in the drawings as an exemplification for the sake of easy understanding, not in a limiting sense.

The semiconductor device of the present invention includes an internal circuit, an input / output terminal (1) for inputting / outputting a signal to / from an external device,
A signal line (3) for connecting the internal circuit and the input / output terminal; a first p-channel MOSFET (5) for connecting the signal line and a first constant potential wiring (Vss); A wiring connecting the gate electrode of the first p-channel MOSFET and the electrode connected to the signal line of the first p-channel MOSFET, the signal line, and the potential of the first constant potential wiring High potential second constant potential wiring (V
dd) second p-channel MOSFET (4) connecting to
And another wiring connecting the gate electrode of the second p-channel MOSFET and the electrode connected to the second constant potential wiring of the second p-channel MOSFET.

The first and second p-channel MOSFEs
T may be formed in the thin film semiconductor region (21) on the insulating surface. Of the source / drain regions of the first and second p-channel MOSFETs, the portion below the insulated gate electrode may have a lower impurity concentration than the central portion. Sidewall regions formed of an insulating material are formed on the side surfaces of the insulated gate electrodes (23, 24) of the first and second p-channel MOSFETs, and the first and second p-channel M
In the source / drain region of the OSFET, the portion below the sidewall region may have a lower impurity concentration than the central portion.

Further, the signal line, the first wiring for connecting said output terminal and a predetermined position of the p ⁺ -type region p ⁺
A second connecting the other predetermined position of the mold region and the internal circuit
And a gate electrode of the first p-channel MOSFET including a wiring may be connected to the other predetermined position.

[0029]

A p-channel MOSF is provided in a protection circuit for preventing an excessive voltage applied from the outside from being applied to the internal circuit.
By using only ET, generation of parasitic bipolar current can be suppressed. This is because impact ionization by holes is less than impact ionization by electrons. Therefore, the reliability of the protection circuit itself can be improved. This structure is a MOS formed in the thin film semiconductor layer and susceptible to impact ionization.
It is particularly effective in FET.

The source of the MOSFET of the protection circuit /
Impact ionization can be further suppressed by forming the drain region into the LDD structure or the double diffusion drain structure.

The first and second p-channel MOSFEs
By providing a resistor between the connection point between T and the signal line and the input / output terminal, when a pulsed excessive voltage is applied, the waveform is blunted and transmitted to the internal circuit. it can.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A protection circuit according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1A shows a circuit diagram. The signal line 3 connected to the pad 1 to which an external signal is input and which is connected to the external circuit is the MOSFET 2 of the internal circuit.
Connected to the gate electrode of. The signal line 3 is a pMOS
Connected to the power supply voltage Vdd via p.
It is connected to the reference voltage Vss via. For ease of explanation, the power supply voltage Vdd side electrode of the pMOS4 is the source electrode S4, the signal line 3 side electrode is the drain electrode D4, and the pM4
The reference voltage Vss side electrode of OS5 is indicated as the drain electrode D5, and the signal line 3 side electrode is indicated as the source electrode S5.

The gate electrodes of the pMOSs 4 and 5 are connected to the source electrodes S4 and S5, respectively. Figure 1 (B)
The cross section of pMOS4, 5 and MOSFET2 of an internal circuit is shown. Ultra-thin semiconductor regions 21 and 22 are formed in an island shape on the surface of the insulating region 10. In the semiconductor region 21, the p ⁺ type region 13, the n type region 18, the p ⁺ type region 14,
The n-type region 19 and the p ⁺ -type region 15 are formed in this order so that the respective regions are in contact with each other.

In the semiconductor region 22, the n ⁺ type region 16 and p
The mold region 20 and the n ⁺ type region 17 are formed in this order so that the respective regions are in contact with each other. n-type regions 18, 19
Gate electrodes 23, 24, 25 having an insulated gate structure are provided on the p-type region 20 and the p-type region 20, respectively.

P ⁺ type regions 13 and 14 and n sandwiched between them
The type region 18 and the gate electrode 23 constitute the pMOS 5, and the p ⁺ type regions 14 and 15 and the n-type region 1 sandwiched between them are formed.
9 and the gate electrode 24 form a pMOS 4. In addition, the n ⁺ type regions 16 and 17 and the p type region 2 sandwiched between them.
The 0 and the gate electrode 25 form the nMOS 2.

Gate electrodes 23 and 25, and p ⁺ type region 1
4 is connected to the wiring 12 through a contact hole provided in the interlayer insulating film 11. The wiring 12 is connected to a pad 1 (not shown in FIG. 1B) for inputting an external signal.

Here, the thickness of the ultrathin film semiconductor layers 21 and 22 is 0.1 μm, and the channel lengths of the pMOSs 4 and 5 are both 0.
The channel length of the nMOS 2 is 8 μm, the impurity concentration of the n-type regions 18 and 19 and the p-type region 22 is 4 × 1.
0 ¹⁶ cm ⁻³ , the thickness of the gate insulating film is 15 nm, the impurity concentration of the p ⁺ type regions 13, 14, 15 and the n ⁺ type regions 16, 17 is 1 × 10 ²⁰ cm ⁻³ , and the gate electrodes 23, 24 Two
Reference numeral 5 is polysilicon, and the wiring 12 is an alloy of Al and Si.

Although not shown in the figure, the wiring 12 and p ⁺
Two metal layers of TiN / Ti are formed as barrier metals at the interface with the diffusion layer such as the mold region 14. The interlayer insulating film 11 is a 0.6 μm thick BPSG film, and the insulating region 10 is a 0.5 μm thick embedded SiO ₂ film formed on a silicon substrate.

When the external signal voltage is between the reference voltage Vss and the power supply voltage Vdd, both pMOSs 4 and 5 are in the off state. Therefore, the external signal voltage is directly applied to the internal circuit. When the external signal voltage becomes an excessive voltage higher than the power supply voltage Vdd, the polarity between the source and drain electrodes of pMOS4 is inverted. At this time, since the gate electrode is connected to the source electrode S4 having a relatively low voltage, the drain electrode D4 is turned on when a voltage higher than the sum of the power supply voltage Vdd and the threshold voltage Vth of the pMOS4 is applied. Becomes For this reason, no voltage higher than the sum of the power supply voltage Vdd and the voltage drop due to the pMOS4 is applied to the internal circuit.

Similarly, when the external signal voltage becomes a negative excessive voltage higher than the threshold voltage Vth of the pMOS5 from the reference voltage Vss, the internal circuit has a negative excessive voltage exceeding the sum of the reference voltage Vss and the voltage drop due to the pMOS5. No voltage is applied. In this way, it is possible to prevent excessive voltage from being applied to the internal circuit.

The use of only pMOS has the following merits. Impurity concentration 4 × 10
The electron mobility in bulk silicon at ¹⁶ cm ^-3 and a temperature of 300 K is about 900 cm ² / Vs, and the hole mobility is about 400 cm ² / Vs. The surface mobility of electrons in the inversion layer of the MOS structure is about 40 times that of the bulk.
%, The hole surface mobility is about 34% of the bulk mobility. Therefore, the surface mobility of holes is about 140 cm ² / V
· S, which is about 40% of the electron surface mobility of 360 cm ² / V · s.

Therefore, the impact ionization rate by holes is smaller than that by electrons. The multiplication coefficient obtained by integrating the impact ionization rate over the entire channel section is
The multiplication factor by electrons is 3 × 10 ⁻² to 2 × 10 ⁻³ , whereas the multiplication factor by holes is 3 × 10 ⁻³ to 2 × 10 ^3.
-5 and 1 to 3 digits smaller. The range of numerical values is because there are differences depending on process conditions such as channel impurity concentration and gate insulating film thickness.

For this reason, impact ionization is less likely to occur in the pMOS than in the nMOS. Furthermore, pMOS
Boron, which is usually used as an impurity in the source / drain regions, has a larger diffusion coefficient than that of impurities such as phosphorus and arsenic used in the source / drain regions of nMOS. Therefore, the impurity concentration gradient at the boundary between the source and drain regions formed by annealing after ion implantation is p
The MOS becomes slower than the nMOS.

For example, the maximum electric field in the horizontal direction of the channel at the drain end when the drain region is formed under the conditions of ion implantation at a dose of 5 × 10 ¹⁵ cm ^-2 and annealing at 950 ° C. for 30 minutes is arsenic. , And about 9 × 10 ⁵ V / cm and 6 × 10 ⁵ V / cm, respectively, when phosphorus is used.
On the other hand, when boron is used, 1 × 10 ⁵ V
/ Cm.

As described above, since the maximum electric field strength at the drain end of the pMOS is smaller than that of the nMOS, impact ionization is less likely to occur. As explained above, p
Impact ionization can be suppressed by using a MOS. Thereby, the parasitic bipolar current can be suppressed and the deterioration of the element can be prevented.

The drain region may be formed by implanting boron ions in two steps. 2 (A), (B)
Is the pMOS5 when the ion implantation is performed twice.
FIG.

In FIG. 2A, after the gate electrode 23 is formed,
An example is shown in which boron ion implantation is performed twice. An example
For example, first dose 4 × 10¹³cm^-2Ion implantation
Then, annealing is performed to form a medium-concentration region.
Dose amount 3 × 10¹⁵cm ^-2Ion implantation of
A high-concentration region is formed by performing the anneal.

The boron ion-implanted first diffuses for a long distance, so that the drain and source regions have a high concentration of p ^+.
The mold regions 13a and 14a are formed outside the gate electrode, and the medium-concentration p ⁺ type regions 13b and 14b are formed below the gate electrode.

FIG. 2B shows an example in which a sidewall is formed on the gate electrode 23 to form an LDD structure. After forming the gate electrode 23, boron ions are implanted to form p ⁺ type regions 13d and 14d having a relatively medium concentration. After that, the sidewalls 26 are formed on the side surfaces of the gate electrode 23 by using low pressure CVD and reactive ion etching.

Next, boron is ion-implanted using the gate electrode 23 and the side wall 26 as a mask to form the p ⁺ type regions 13c and 14c having a relatively high concentration. In this way, by providing a region having a relatively low impurity concentration at the junction between the drain region and the channel region, it is possible to further suppress the generation of a high electric field. Therefore, impact ionization is suppressed, and deterioration of the element due to a parasitic bipolar current can be prevented.

Furthermore, the gate lengths of the pMOSs 4 and 5 of the protection circuit may be made longer than the gate lengths of the MOSFETs of the internal circuit. Increasing the gate length corresponds to increasing the base width of the pnp bipolar transistor having the source region, the channel region, and the drain region of the MOSFET as the emitter, the base, and the collector, respectively. Therefore, generation of parasitic bipolar current can be suppressed.

The protection circuit according to the embodiment has been described above focusing on the sectional shape thereof, but the planar layout of each element will be described below. FIG. 3A shows a plan view of one protection circuit. Each part in FIG.
The same reference numerals are given to the corresponding portions of (B).

The wiring 12a extends from the pad to which the external signal voltage is applied. The wiring 12a is connected to the p ⁺ type region 14 thereunder via the contact hole H1. In addition, the wiring 1 for supplying an external signal to the internal circuit
2b is the p ⁺ type region 14 through the contact hole H2
It is connected to the.

In this way, the external signal voltage is the p ⁺ type region 1
4 is supplied to the internal circuit. Since the p ⁺ type region functions as a resistance, it has the effect of blunting the waveform when a pulsed excessive voltage is applied from the outside.

The wiring 12b on the internal circuit side is formed in the semiconductor region 2
1 through the contact hole H3 formed outside
It is connected to the gate electrode 23 of the MOS5. pMOS
By connecting the gate electrode of No. 5 to the wiring 12b on the inner side, it is possible to prevent external noise from being directly applied to the gate electrode of the pMOS5. As a result, it is possible to prevent the deterioration of the gate insulating film of the pMOS 5 itself of the protection circuit.

Gate electrode 23 extends between p ⁺ type regions 13 and 14 formed in semiconductor region 21. p ⁺
The mold region 13 is connected to the wiring of the reference voltage Vss formed thereon via the contact hole H5.

The p ⁺ type region 15 formed in the semiconductor region 21 is connected to the wiring of the power supply voltage Vdd through the contact hole H6. p ⁺ type region 15 and n type region 14
A gate electrode 24 is formed between and. The gate electrode 24 has a contact hole H outside the semiconductor region 21.
It is connected to the wiring of the power supply voltage Vdd through the line 4.

The contact hole H2 of the internal circuit side signal wiring 12b and the contact hole H1 between the pad side wiring 12a and the n-type region 14 should be arranged as far apart as possible.

By disposing the contact holes H1 and H2 apart from each other, the resistance between the pad side wiring 12a and the internal circuit side wiring 12b can be increased. As a result, the effect of blunting the voltage waveform of electrostatic noise applied from the outside is increased.

FIG. 3B is a schematic plan view showing the layout of the entire integrated circuit. Internal circuits are formed in the central portion 31 of the substrate. Around the inner circuit region 31, a predetermined number of pads 1 for connecting to the outside are provided. The protection circuit 30 corresponds to each pad and has an internal circuit area 3
1 is provided in the peripheral portion. Pad 1 and protection circuit 30
Are connected by wiring 12a.

In this way, by bringing the pad 1 and the protection circuit 30 as close to each other as possible, the wiring 12a to which an external signal is directly applied can be shortened. This can reduce the influence of high voltage on the internal circuit.

As described above, according to this embodiment, not only is the internal circuit protected from electrostatic damage, but the MO of the protection circuit is also protected.
The resistance of the SFET itself to static electricity can be improved.

Since the conventional CMOS buffer protection circuit uses two types of MOSFETs, nMOS and pMOS, as shown in FIG. 8B, two drain regions connected to the signal line extending from the pad are used. (D105, D1
06) It was necessary to form.

According to this embodiment, since only one type of pMOS is used in the protection circuit, one diffusion region 14 can also serve as the drain regions of two MOSFETs. Therefore, the area of the protection circuit occupied on the substrate can be reduced.

Next, a method of manufacturing an SOI structure MOSFET will be described. 4A to 4E show an example using a bonded substrate. As shown in FIG. 4A, the surface of the silicon substrate 40 is selectively etched leaving an element formation region to form a groove for element isolation.

As shown in FIG. 4B, the silicon substrate 4
C so that the groove is thicker than the depth of the groove formed on the surface of 0.
The SiO ₂ film 41 is deposited by the VD method or the like. Further thereon, a polysilicon film 42 is deposited by vapor deposition or the like. The surface of the polysilicon film 42 is mirror-polished.

As shown in FIG. 4C, the surface of the mirror-polished polysilicon film 42 and another silicon substrate 43 are adhered and bonded. For bonding, silicon substrate 4
By applying a high voltage between 0 and 43, the polysilicon film 42 and the silicon substrate 43 are bonded at the atomic level.

As shown in FIG. 4D, the silicon substrate 4
0 is polished from the surface opposite to the bonding surface. SiO ₂
The polishing is stopped when the upper surface of the convex portion of the film 41 is exposed. As a result, island-shaped silicon semiconductor layers 40a to 40d remain in the concave portion of the SiO ₂ film.

As shown in FIG. 4E, for example, polysilicon gate electrodes 46 and 47 having an insulated gate structure are formed in the central portions of the silicon semiconductor layers 40b and 40c, respectively. Next, using the gate electrodes 46 and 47 as masks, predetermined impurities are ion-implanted to form the source / drain regions 4.
4a, 44b and 45a, 45b are formed.

5A to 5C show an example using a SiMOX substrate having a buried oxide film. Figure 5 (A)
A SiMOX substrate 50 shown in is prepared. In this case, a SiO ₂ layer 52 is formed at a predetermined depth on a silicon substrate 51 by oxygen implantation and high temperature annealing. Si
The silicon thin film layer 53 is left on the upper layer of the O ₂ layer 52.

As shown in FIG. 5B, the semiconductor element formation region is covered with a SiN film or the like and selectively thermally oxidized to form field oxide films 54a to 54c. The field oxide films 54a to 54c are formed so that their lower surfaces reach the SiO ₂ layer 52. Thereby, the silicon thin film layer 53
Are separated into islands, and semiconductor element formation regions 53a to 53d are formed.
Is formed.

As shown in FIG. 5C, for example, polysilicon gate electrodes 57 and 58 having an insulated gate structure are formed in the central portions of the semiconductor element forming regions 53b and 53c, respectively.
To form. Next, using the gate electrodes 57 and 58 as masks, predetermined impurities are ion-implanted to form source and drain regions 55a and 55b and 56a and 56b.

In this way, the MOS is formed on the ultrathin film semiconductor layer.
A FET can be formed. Above, M of SOI structure
The protection circuit composed of OSFET has been explained,
The invention is not limited to SOI structures. The present invention can be applied to a protection circuit formed on a bulk silicon substrate, a protection circuit formed on a germanium (Ge) layer, a SiGe layer, or the like.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0075]

As described above, according to the present invention,
It is possible to improve the resistance of the protection circuit itself for preventing electrostatic breakdown of the integrated circuit to static electricity.

[Brief description of drawings]

1A is a circuit diagram of a protection circuit according to an embodiment of the present invention, and FIG. 1B is a sectional view thereof.

FIG. 2A is a p-channel MOSF having a double diffused drain structure used in a protection circuit according to an embodiment of the present invention.
2B is a cross-sectional view of a p-channel MOSFET having an LDD structure.

3A is a plan view of a protection circuit according to an embodiment of the present invention, and FIG. 3B is a schematic plan view of an integrated circuit using the protection circuit according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view of a substrate illustrating a method of manufacturing a protection circuit using a bonded substrate according to an embodiment of the present invention.

FIG. 5 is a substrate cross-sectional view illustrating a method of manufacturing a protection circuit using a SiMOX substrate according to an exemplary embodiment of the present invention.

FIG. 6A shows a conventional field MOSFET.
A circuit diagram of the mold protection circuit, FIG. 6B is a cross-sectional view thereof.

FIG. 7A is a conventional clamp type MOSFET.
A circuit diagram of the protection circuit and FIG. 7B are cross-sectional views thereof.

8A is a circuit diagram of a conventional CMOS buffer type protection circuit, and FIG. 8B is a sectional view thereof.

[Explanation of symbols]

1 Pad 2 MOSFET 3 of Internal Circuit Signal Line 4, 5 p-Channel MOSFET 10 Insulating Region 11 Interlayer Insulating Film 11a Gate Insulating Film 12 Wiring 13, 13a to 13d, 14, 14a to 14d, 15
p ⁺ type region 16, 17 n ⁺ type region 18, 19 n type region 20 p type region 21, 22 ultra thin film semiconductor region 23, 24, 25 gate electrode 26 sidewall 40 silicon substrate 40a-40d thin film semiconductor region 41 SiO ₂ Film 42 Polysilicon film 43 Silicon substrate 44a, 44b, 45a, 45b Source / drain regions 46, 47 Gate electrode 50 SiMOX substrate 51 Silicon substrate 52 Embedded SiO ₂ layer 53 Silicon layer 53a to 53d Thin film semiconductor region 54a to 54c Field oxide film 55a, 55b, 56a, 56b Source / drain regions 57, 58 Gate electrode 100 Pad 101 Field MOSFET 102 MOSFET of internal circuit 103 Signal line 104 Clamp MOSFET 110 Silicon substrate 111 p-type well 12 field oxide film 113 interlayer insulating film 114 the wiring 115, 116 gate electrode 117 line 118 n-type well

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/78

Claims (8)

[Claims] 1. An internal circuit and an input / output terminal (1) for inputting / outputting a signal to / from an external device.
A signal line (3) for connecting the internal circuit and the input / output terminal, and a first p-channel MOSFET (5) for connecting the signal line and a first constant potential wiring (Vss). A wiring connecting the gate electrode of the first p-channel MOSFET and an electrode connected to the signal line of the first p-channel MOSFET, the signal line, and the potential of the first constant potential wiring A second p-channel MOSFET (4) that is connected to a second constant-potential wiring (Vdd) having a higher potential than that, a gate electrode of the second p-channel MOSFET, and the second p-channel MOSFET. A semiconductor device including another wiring that connects an electrode connected to the second constant potential wiring. 2. The semiconductor device further includes a support (10) having an insulating surface and a thin film semiconductor region (21) formed on the insulating surface, and the first and second p-channel MOSFETs. The semiconductor device according to claim 1, wherein is formed in the thin film semiconductor region (21). 3. The semiconductor device according to claim 2, wherein the thin film semiconductor region is formed of one kind of material selected from the group consisting of silicon, germanium, and silicon-germanium. 4. The first and second p-channel MOSFs
The source / drain region of the ET has a lower impurity concentration in a portion below the insulated gate electrode than in a central portion.
3. The semiconductor device according to any one of 3 above. 5. A sidewall region made of an insulating material is provided on a side surface of the insulated gate electrode (23, 24) of the first and second p-channel MOSFETs, and the first and second p-channel MOSFETs have side wall regions. Source of p-channel MOSFET /
The semiconductor device according to claim 1, wherein a portion of the drain region below the sidewall region has a lower impurity concentration than a central portion. 6. The first and second p-channel MOSFs
The semiconductor device according to claim 2, wherein the signal line side electrode of the ET is composed of one common p ⁺ type region (21) formed in the thin film semiconductor region. 7. The signal line includes a first wiring connecting a predetermined position of the p ⁺ -type region and the input / output terminal, and a second wiring connecting another predetermined position of the p ⁺ -type region and the internal circuit. 7. The semiconductor device according to claim 6, further comprising a wiring, wherein the gate electrode of the first p-channel MOSFET is connected to the other predetermined position. 8. The first and second p-channel MOSFs
The semiconductor device according to claim 1, wherein a gate length of ET is longer than a gate length of a MOSFET of the internal circuit.