GB2374200A - Radiation tolerant MOS layout - Google Patents

Radiation tolerant MOS layout Download PDF

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Publication number
GB2374200A
GB2374200A GB0031344A GB0031344A GB2374200A GB 2374200 A GB2374200 A GB 2374200A GB 0031344 A GB0031344 A GB 0031344A GB 0031344 A GB0031344 A GB 0031344A GB 2374200 A GB2374200 A GB 2374200A
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Prior art keywords
gate
type
semiconductor device
edge portion
drain
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GB0031344A
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GB0031344D0 (en
Inventor
Walter Snoeys
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European Organization for Nuclear Research CERN
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European Organization for Nuclear Research CERN
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Application filed by European Organization for Nuclear Research CERN filed Critical European Organization for Nuclear Research CERN
Priority to GB0031344A priority Critical patent/GB2374200A/en
Publication of GB0031344D0 publication Critical patent/GB0031344D0/en
Priority to AU2002222359A priority patent/AU2002222359A1/en
Priority to PCT/IB2001/002493 priority patent/WO2002050914A2/en
Publication of GB2374200A publication Critical patent/GB2374200A/en
Withdrawn legal-status Critical Current

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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
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Abstract

An edge portion 46 of an NMOS gate electrode 44 has a different work function to its central portion and the gate electrode overlies most of the transistor structure active region. The work function variation is used to increase the threshold voltage of the device at the device edges. In this manner the central portion of the gate is used for switching the device on or off, and the edge portion of the gate provides isolation from adjacent devices. The enhanced device isolation improves the radiation tolerance of the device. The device layout may also be applied to PMOS and gated diode devices.

Description

A SEMICONDUCTOR DEVICE
The present invention relates to a semiconductor device, in particular, a 5 radiation tolerant semiconductor device and, more specifically, a radiation tolerant NMOS device.
Radiation tolerance of integrated circuits is a primary concern in highenergy physics experiments. This is because the components used for detecting lo radiation need, themselves, to be resilient to such radiation in order to ensure their reliability. Irradiation measurements on MOS capacitors performed in the early 80's showed a significant decrease of the radiation induced oxide trapped charge and interface states for oxides thinner than about 10nm. Such measurements are described in the articles "Radiation effects in MOS capacitors 15 with very thin gate oxides at 80K", IEEE Trans. Nucl. Sci. NS-31 (1984) 1249, and "Generation of interface states by ionizing radiation in very thin MOS oxides", IEEE Trans Nucl. Sci. NS-33 (1986) 1185, by N. S. Saks, M.G.
Ancona, J.A. Modolo.
20 Gate oxides in present day submicron CMOS technologies are often thinner than 10 nm. Figure 1 shows a plot of the measurements on MOS capacitors from the above- mentioned article "Radiation effects in MOS capacitors with very thin gate oxides at 80K". Measurements taken on present day transistors are also plotted on Figure 1. These measurement points are marked A, B. C and 25 D. Figure 1 illustrates that radiation induced parameter shifts of the present day
transistors are similar to those of the earlier measurements on MOS capacitors.
This confirms that, if gate oxides thinner than 10nm are used to implement MOS transistors, radiation induced parameter shifts are greatly reduced. The reason for this reduction is that in addition to thermal annealing, tunnelling s becomes more effective to neutralize radiation- induced charge when the gate oxide thickness is below this threshold.
To take full advantage of the reduction of radiation induced transistor parameter shifts in order to obtain a circuit that remains functional after very high ionising lo radiation doses, the problem of radiation induced leakage needs to be addressed.
Ionising radiation can lead to leakage for NMOS transistors. This is because radiation causes the formation of an inversion layer in the ptype substrate or P well underneath the field oxide or at the edge of the active area, the inversion
layer being formed due to the accumulation of positive charge in the silicon 5 oxide. Formation of the inversion layer leads to the leakage of charge between the source and drain contacts and, in multi-device configurations, the leakage of charge between neighbouring N+ implants.
In order to overcome the problem of radiation induced source-drain leakage, 20 NMOS transistors with an edgeless transistor (ELT) geometry can be used. In this the gate is formed as a continuous, edgeless ring, with the drain contact being located inside the ring and the source contact outside the gate ring or vice versa, as shown in Figures 2 and 3. In this way all source to drain current is forced to run underneath the gate oxide and leakage between the source and 25 drain is avoided.
To avoid the problem with the leakage of charge between neighbouring N+
implants, P+ guardrings are sometimes used. These guard rings are P+ implants that extend around and separate adjacent devices. Again, this is shown in Figures 2 and 3. P+ guardrings prevent inter-device leakage by increasing the doping level between the devices to such an extent that the threshold for s inversion is so high that the positive charge generated in the oxide would no longer be sufficient to invert the silicon at the silicon-silicon dioxide interface.
The use of ELTs with P+ guardrings has been successful for a number of circuits to obtain radiation tolerance beyond 10 Mrad for SiO2. Circuits in lo which this configuration is used are described in the articles "A Pixel Readout Chip for 10-30 Mrad in Standard 0.25 micron CMOS" by M. Campbell et al, presented at the 1998 Nuclear Science Symposium, October 1998, Toronto, Canada and "Development of a Radiation Tolerant 2.0V Standard Cell Library Using a Commercial Deep Submicron CMOS Technology for the LHC 15 Experiments", by K. Kloukinas et al, 4th Workshop on Electronics for LHC Experiments, pp. 574-580, September 1998. However, the edgeless layout transistor imposes practical limitations, the most significant of which is that the ratio of gate width (W) to gate length (L) generally has to be high. Small effective W/L ratios quickly lead to prohibitively large transistor sizes. This to constitutes a severe limitation, especially for analogue circuits.
Attempts have been made to prevent radiation-induced leakage using transistor geometries other than an ELT, which do not impose a W/L limitation. One such device is shown in Figure 4. This has a traditional shaped polysilicon gate :5 over a p-type active area, which p-type active area extends beyond the N+ implant that defines the transistor. On opposing sides of the gate are a source and a drain contact. Extending partially over the device and wholly around its
periphery is a P+ implant that acts as a guardring. It should be noted that the P+ implant does not extend over the source and drain contact, but does extend over the sides of the gate that extend between the source and drain. Using this device configuration, there is no leakage path between the source and drain, as 5 the P+ guardring isolates them. In addition to the guard ring that extends around the gate, a Pi guard may be provided around the gate contact to isolate the transistor channel from other components.
Whilst the structure of Figure 4 overcomes the problems with earlier ELTs, it lo will not work if the source and drain areas are covered with silicide or salicide, which is the case for many present-day deep submicron technologies. In that case source and drain will be shorted to the P+ region, and hence to the P-well or P-type substrate underneath. This would preclude normal transistor operation. An object of the present invention is to provide a new transistor structure that avoids the W/L limitation of ELTs and does not cause problems for silicized or salicized sources and drains.
to According to one aspect of the present invention, there is provided a semiconductor device having a bias contact deposited on a substrate, the bias contact having an active portion and an edge portion, the work functions of the active portion and the edge portion being different and such that over a biasing voltage range, a region under the active portion is switched on and a region 25 under the edge portion is switched off By edge portion it is meant any part of the bias contact that is adjacent to or
defines a limit of the main active area of the bias contact.
An advantage of this is that it is possible over a certain pre-determined biasing voltage range to turn on the main active portion of the device, while keeping the s edges turned off. This means that the edge portions can act to isolate the device from leakage current over a particular working voltage range of the contact.
The pre-determined voltage range may be substantially 1V above the threshold for the active portion of the biasing contact. This means that to turn on and start lo contributing to current, a gate bias which is about 1V higher than the threshold voltage for the region under the active portion has to be applied to the edge portion. The device may be a diode or a transistor. Where the device is a transistor, the Is bias contact is the gate contact and source and drain contacts are provided.
The active portion of the biasing contact may be e-type material or ptype material. When the substrate is p-type material, the active portion is e-type and the edge portions are preferably p-type. When the substrate is e-type material, to the active portion of the biasing contact is ptype and the edge portions are preferably e-type. In any case, one of the edge portion and the main active portion may be substantially un-doped and the other may be doped either p-type or e-type, provided that the work functions of the main active portion and the edge portion are such that over a pre-determined voltage range, the main active as region of the device is on and regions under the edge portion is switched off.
Preferably, the bias contact is made of a single material, such as polysilicon,
that is doped so as to provide the active and edge portions, the work functions of the active portion and the edge portion being different and such that over a pre-determined biasing voltage range, a region under the active portion is switched on and a region under the edge portion is switched off.
5 The source may be formed through an opening in the gate, so that the source is, in effect, wholly enclosed by the gate. The drain may be formed through an opening in the gate, so that the drain is, in effect, wholly enclosed by the gate.
The edge portion may extend entirely around the periphery of the bias contact.
According to another aspect of the present invention, there is provided a transistor having a source, a drain and a gate, the source and drain being enclosed by the gate.
Is The gate contact may have an active portion and edge portions, the work functions of the active portion and the edge portions being different and such that over a biasing voltage range, a region of the device under the active portion is switched on and regions under the edge portions are switched off to The active portion of the gate may be e-type material or p-type material. When the substrate is p-type material, the active portion is e-type and the edge portions are preferably p-type. When the substrate is e-type material, the active portion of the biasing contact is p-type and the edge portions are preferably n type. In any case, one of the edge portion and the main active portion may be 25 substantially un-doped and the other may be doped either p-type or e-type, provided that the work functions of the main active portion and the edge portion are such that over a pre-deterrnined voltage range, the main active region of the
device is on and regions under the edge portion is switched off. Preferably, the gate is made of polysilicon.
Various devices and methods in which the invention is embodied will now be s described by way of example only and with reference to the following drawings, of which: Figure 5 is a plan view of a transistor; Figure 6 is a side elevation of the gate of the transistor of Figure 5; Figure 7 is a section on the line A-A' of Figure 5; lo Figure 8 is a section on the line B-B' of Figure 5; Figure 9 is a section on the line C-C' of Figure 5; Figure 10 is a section on the line D-D' of Figure 5; Figure 11 is a plan view of another transistor; Figure 12 is a section on the line E-E' of Figure 1 1; Is Figure 13 is a section on the line F-F' of Figure 11; Figure 14 is a section on the line G-G' of Figure 11; Figure 15 is a section on the line H-H' of Figure 1 1; Figure 16 is an elevation of an array of the gates of Figures 5 and 1 1; Figure 17 is an elevation of an alternative gate structure for a transistor; no Figure 18 is a plan view of yet another transistor; Figure 19 is a section on the line J-J' of Figure 18, Figure 20 is an elevation of an alternative transistor structure, Figure 21 is an elevation of a gate structure for a diode, and Figure 22 is a cross section through a diode that is similar to that of as Figure 21.
In modern CMOS processes, polysilicon is used as gate material, often with
Q o some silicide on top for reduced resistance. The work function of the gate therefore depends on the doping level of the polysilicon. This is used in deep submicron CMOS, where it is common practice to dope the polysilicon with p type material over the PMOS transistor and with e-type material over the 5 NMOS transistor. The availability of two doping types of polysilicon in the standard process can be used advantageously to locally change the threshold of the transistor.
Figure 5 to 10 show a new NMOS device 30 having an p-type substrate or p o type well 31 with a thin oxide layer 33, on which is deposited a generally rectangular shaped polysilicon gate 32. Formed through the main portion of the gate 32 and at opposing ends thereof are two openings 34. A central portion of the gate 32 and the active material exposed by the gate openings 34 are implanted with N-type dopant to form N+ regions, see Figures 8 and 10. In this 15 way, the implanted material 36 in the openings 34 forms source and drain contacts 38 and 40 respectively. A region 42 over and wholly round the gate's periphery and the active area that surrounds the gate 32 is implanted with P type dopants to form P+ regions. Hence, the gate 32 has a main rectangular central region 44 that is N-type and a periphery 46 that is implanted with P-type to material. The gate 32 is shown in more detail in Figure 6. The P+ regions created in the substrate (as opposed to the P+ region created in the polysilicon) can be used to contact the P-well or the P- type silicon substrate.
Surrounding the P+ implant is a layer of field oxide 48. This can be seen in the
25 cross-sections of Figures 7 to 10. Extending over the field oxide 48 and to the
gate 32, is a p-type polysilicon gate contact portion 50 that provides a means for making direct electrical contact thereto, as shown in Figure 9. Optionally
provided over the gate 32 and/or the source and drain contacts is a layer of silicide (not shown). Over the full structure is a layer of oxide 52, through which electrical contacts 54 for contacting the source 38, drain 40 and gate 32 are formed. Connected to the electrical contacts 54 are metal pads 56 for 5 making external connection to the source and drain 38 and 40 respectively.
It should be noted that the source and drain contacts 38 and 40 respectively of the device of Figure 5 are wholly enclosed by the gate 32. This avoids a butted contact between N+ and P+ implanted regions in the active area, which could lo lead to a short when the source and drain are covered with silicide.
The transistor 30 of Figures 5 to 10 functions in a standard manner. However, by making the edges 46 of the transistor gate P-type, rather than N-type, the work function of the transistor 30 varies across the gate 32. In particular, the Is threshold of the gate region is about 1V higher (the Si bandgap) for the p-type periphery than for the main e-type region, particularly if both the p-type and n type regions are heavily doped. This means that to turn on and start contributing to the transistor current the region under the P-type polysilicon needs a gate bias which is about 1V higher than the region under the N-type to polysilicon. This allows a gate voltage to be applied to cause the central part of the transistor to be turned on and the periphery turned off. Hence, provided the gate bias is sufficiently low to avoid turn-on of the perimeter region, radiation induced leakage to the source, the drain and the transistor channel can be prevented. In the structure shown in Figure 5, the polysilicon gate 32 is surrounded by P type guard ring 42. This is included in order to allow the device to be operated
at biases greater that the threshold for the gate periphery turn on and so is in effect a secondary line of defence. However, if the device 30 is only to be operated within a gate bias range that avoids turn on of the gate periphery region, the guard ring 42 is not necessary.
5 Figures 11 to 15 show an NMOS transistor, in which no guard ring is provided.
In this case, a polysilicon gate 60 is deposited over the active region and extends over the edges of a thick layer of field oxide 62 that is deposited on and
wholly surrounds the active region of the semiconductor material. As before, the main active portion 64 of the gate 60 is e-type and its periphery 66 is lo implanted with a P+ type dopant, in such a manner that a relatively narrow portion of the gate 60 that extends around and in contact with the edges of the active region of the substrate is P-type. As before, the doping levels of the N type active portion 64 and the P+ type periphery are chosen so that it is possible over a certain, predetermined, biasing voltage range to turn on the main active Is portion of the device, while keeping the edges turned off. Hence, the edge portions of the gate 60 act to isolate the device from leakage current over a working range of bias voltages.
As will be appreciated, the principle of confining the active channel region to underneath N+ polysilicon surrounded by P+ polysilicon can be used to define an array of AMOS transistors, as shown in Figure 16. Alternatively, the polysilicon can be processed to provide gates that define an active channel that has an unusual shape.
25 Figure 17 shows a gate 68 that has a snake shaped active N-type polysilicon region 71 that winds through P-type polysilicon 72. In use, the snake shaped polysilicon region 71 defines a snake shaped channel in the substrate or p-type
well. Formed through the N-type polysilicon region 70 are openings for source and drain contacts 73 and 74 respectively. As before, doping levels of the active and edge portions of the polysilicon are selected, so that the work functions of the N and P-type polysilicon are different and such that over a pre 5 determined biasing voltage range, the region of the device under the N-type polysilicon is switched on and the region under the P-type polysilicon is switched off. In this way, the gate 68 acts to isolate the transistor from external leakage currents. An advantage of the device of Figure 17 is that the effective W/L ratio is relatively small, but the overall device is compact. Another lo advantage is that the P-type implant can be used to define the width of the gate, which can simplify processing.
The devices of Figures 5 to 17 operate well in the bias range below the threshold voltage for turning on the periphery of the gate contact. However, for Is higher gate biases the channel region under the P+ periphery turns on, and no longer serves to isolate the active area. If a device that operates at relatively high voltage is required, the structure in Figure 18 can be used.
Figures 18 and 19 show a transistor that has all of the features of the transistor 20 of Figure 5, but additionally has a pope guard ring 80 round the gate contact.
At low voltages the p-type periphery of the polysilicon gate acts to prevent leakage. However, at higher bias voltages, the P+ guardring 80 provides the isolation. Contrary to the structure of Figure 4, this structure works if the active areas are covered with silicide. As before, this is because the source and drain 25 contacts are wholly enclosed by the gate.
Many structures based on the principles in which the various aspects of the
invention are embodied can be envisaged. An example of another such structure can be seen in Figure 20, which shows a transistor that has a gate 86 with a work function that varies across its width. The gate 86 is generally rectangular, but has recesses 88 formed in opposing ends thereof. As before, 5 the substrate is p-type, the gate 86 has a main active portion that is N+ type polysilicon 89 and edge portions 90 that are P+ type polysilicon. The gate 86 is deposited over two thick layers of field oxide 92, so that the parts of the gate
that define each recess 88, each extends over one of the thick layers of field
oxide 92. Located in the space defined by the gate recesses and the field oxide
lo are a source and drain contact (not shown). Outside of the gate recesses and the overlap regions with the gate, this field oxide is fully surrounded by a P+
guardring 94. In this way, although the source and drain contacts are not fully enclosed by the gate 86, they are both isolated in use from leakage currents by the combined action of the gate and the P+ guardring.
In the device of Figure 20, the source and drain are not fully enclosed by a p type polysilicon gate portion, but are terminated in part by a thick layer of field
oxide 92. The thick oxide layer 92 is surrounded with a P+ guardring 94 that reaches the edges of the P-type polysilicon to prevent leakage from the source to or the drain to a nearby N+ or Newell implant. It should be noted that the polysilicon strap leading to the gate contact is not shown in Figure 20, but can be attached to the gate at any location. If necessary, the gate contact on the field oxide can be surrounded by a P+ guard.
25 Figures 5 to 20 show transistors. It will, however, be appreciated that the isolation technique of the present invention could be used to provide isolation for a diode.
Figure 21 shows an example of a gated diode that is isolated using the technique in which the invention is embodied. This has an N-type implant in the silicon substrate forming the diode (not shown). Fully surrounding the diode is a 5 polysilicon ring 96 that is deposited over a thin oxide layer. The polysilicon ring is contacted by means of a polysilicon strap 98 leading to a contact to the polysilicon that is deposited over field oxide. An inner part lOO of the
polysilicon ring is e-type and an outer part 102 thereof is p-type. As before, the work functions of the N and P-type polysilicon are different and such that over lo a pre-determined biasing voltage range, the region of the diode under the inner edge portion 100 is switched on and the region under the outer edge portion is switched off 102. Due to the increased threshold for inversion of the silicon underneath the p-type polysilicon 102, the voltage range over which the diode is isolated from nearby N-implants or N-wells is increased.
Surrounding all of the polysilicon gate except under the polysilicon contact strap, is optionally provided a P+ guard (not shown). If necessary the contact over field oxide to this strap can be surrounded by a P+ guard as well. Also,
here the P+ guard is a secondary line of defence only necessary if a sufficiently 20 large voltage range on the diode implant is foreseen to invert the substrate under the p-type polysilicon region. If the device is only to be operated in a voltage range that avoids this turn on, no- guard ring needs to be provided and the gate extends over the whole active region and over a thick layer of field oxide
surrounding the active region.
Figure 22 shows a cross-section of a gated diode 104 isolated using the technique shown in Figure 21, where no P+ guard is used. As before, the full
device is covered in a layer of oxide 105 and the polysilicon gate may optionally be covered by a layer of salicide (not shown). Both the contact 106 to the polysilicon gate 108 and the contact 109 to the N+ implant 110 are shown. The other terminal of the diode is the P-well or the P-type substrate, 5 which can be contacted by means of a contact to the P+ implant inside this P well or P-type substrate.
It should be noted that the polysilicon gates of the diodes in each of Figures of 21 and 22 have to be contacted separately from the diode. In some cases, both lo can be connected together using metal to bring them to the same potential, but usually two separate metal contacts are needed, one to the polysilicon gate and the other to the N+ implant that creates the diode.
Whilst the above examples are described with reference to an NMOS transistor, Is it will be appreciated that the same principle can also be applied to PMOS transistors. In this case, the main active area of the polysilicon would be p-type and the periphery thereof would be e-type. Equally although the implant creating the diode of Figures 21 and 22 is described as being e-type, it could, of course, be p-type. In this case, the inner portion of the polysilicon would be p o type and the periphery thereof would be e-type.
All of the devices described above have a polysilicon gate that is doped so as to have a work function that varies, thereby to provide a means for isolating the active area of the device. Other materials could be used in this way to produce 25 a single material bias contact, with the different work functions being provided by the doping levels of the different regions of the gate. Alternatively, the active and edge portions of the gate could be made of different materials.
An advantage of the present invention is that it prevents radiation induced transistor leakage and so provides radiation tolerant circuits that can be made using standard MOS, in particular CMOS, technology. It also allows transistors s with a small W/L ratio to be designed. Furthermore, the device layout is not affected by silicidation /salicidation of a polysilicon gate and source and drain.
One of the main principles embodied in the structures described above is to act on the workfunction of the gate to locally change the threshold of the transistor lo channel underneath. The validity of the new structure has been verified experimentally: the devices behaved as expected prior to irradiation, and remained fully functional after a 40 Mrad (SiO2) irradiation.
It will be understood that the technique for isolating the devices described herein can be used for devices other than those intended for use in readout circuitry for radiation detectors. It can be used more generally as a technique to isolate devices even when radiation tolerance is not a concern. For example, it can be applied to PMOS transistors and P+ or P type to N well or N-substrate diodes, where radiation tolerance is not often a concern.
A skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the invention. Accordingly, the description
of the specific embodiments is made by way of example and not for the purposes of limitation. It will be clear to the skilled person that minor :5 modifications can be made without significant changes to the operation described above.

Claims (1)

1 6 Claims
1. A semiconductor device having a bias contact deposited on a semiconductor substrate, the bias contact having an active portion and an edge portion, the 5 work functions of the active portion and the edge portion being different and such that over a biasing voltage range, a region under the active portion is switched on and a region under the edge portion is switched off.
2. A semiconductor device as claimed in claim 1, wherein the active portion of lo the biasing contact is e-type material.
3. A semiconductor device as claimed in claim 2, where in the edge portion is p-type material.
Is 4. A semiconductor device as claimed in claim 1, wherein the active portion of the biasing contact is p-type material.
5. A semiconductor device as claimed in claim 4, where in the edge portion is e-type material.
6. A semiconductor device as claimed in claim 1, wherein the edge portion is substantially un-doped and the main active portion is doped either ptype or e-type, depending on the material of the substrate.
25 7. A semiconductor device as claimed in claim 1, wherein the main active portion is substantially un-doped and the edge portion is doped either p-type or e-type, depending on the material of the substrate.
8. A semiconductor device as claimed in any one of the preceding claims that is a diode.
5 9. A semiconductor device as claimed in claim 8, wherein the bias contact comprises a ring that extends wholly around an active part of the diode, thereby to isolate it.
lO.A semiconductor device as claimed in any one of claims 1 to 7 wherein the lo device is a transistor.
11.A semiconductor device as claimed in claim 10, wherein the bias contact is the gate contact and source and drain contacts are provided.
15 12.A semiconductor device as claimed in claim 12, wherein the source is formed in an opening in the gate, so that the source is wholly enclosed by the gate.
13.A semiconductor device as claimed in claim 11 or claim 12, wherein the 20 drain is formed in an opening in the gate, so that the drain is wholly enclosed by the gate.
14.A transistor having a source, a drain and a gate, the source and drain being wholly enclosed by the gate.
15.A semiconductor device as claimed in claim 14, wherein the gate has an active portion and an edge portion, the work functions of the active portion
and the edge portion being different and such that over a biasing voltage range, a region of the device under the active portion is switched on and regions under the edge portions are switched off.
GB0031344A 2000-12-21 2000-12-21 Radiation tolerant MOS layout Withdrawn GB2374200A (en)

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GB0031344A GB2374200A (en) 2000-12-21 2000-12-21 Radiation tolerant MOS layout
AU2002222359A AU2002222359A1 (en) 2000-12-21 2001-12-17 A semiconductor device with bias contact
PCT/IB2001/002493 WO2002050914A2 (en) 2000-12-21 2001-12-17 A semiconductor device with bias contact

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