JPH07165496A - Production of silicon wafer - Google Patents

Production of silicon wafer

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Publication number
JPH07165496A
JPH07165496A JP23447694A JP23447694A JPH07165496A JP H07165496 A JPH07165496 A JP H07165496A JP 23447694 A JP23447694 A JP 23447694A JP 23447694 A JP23447694 A JP 23447694A JP H07165496 A JPH07165496 A JP H07165496A
Authority
JP
Japan
Prior art keywords
heat treatment
oxidation
gas
silicon wafer
induced stacking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23447694A
Other languages
Japanese (ja)
Other versions
JP2652346B2 (en
Inventor
Hiroshi Shirai
宏 白井
Norihei Takai
法平 高井
Yoshio Kirino
好生 桐野
Kenji Akai
賢二 赤井
Takeshi Kon
武志 今
Hiromitsu Nakanishi
宏円 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coorstek KK
Original Assignee
Toshiba Ceramics Co Ltd
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To obtain a silicon wafer with low crystal defect density. CONSTITUTION:A silicon wafer is heat treated by staying at 1000-1350 deg.C for 30min or longer in a hydrogen gas atmosphere and then further heat-treated for 16hr in a dry oxygen gas atmosphere to conduct an etching to bring the average oxidatively induced laminate defect density of the wafer surface to about 1/5 times that before heat treatment.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明はシリコンウエーハの製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon wafer.

【０００２】[0002]

【従来の技術】半導体用のシリコン単結晶において、結
晶欠陥を低減するために種々の処理が行なわれている。
例えば、そのような結晶欠陥を低減する技術の１つとし
て無欠陥層（Ｄenuded Ｚone ）処理が知られている。2. Description of the Related Art In a silicon single crystal for semiconductors, various treatments are performed to reduce crystal defects.
For example, a defect-free layer treatment is known as one of the techniques for reducing such crystal defects.

【０００３】無欠陥層処理を施したウエーハは高温熱処
理工程を経て製造されるため、ウエーハ表面の格子間の
酸素濃度が減少する。そのために、ウエーハ表面近傍に
は微小欠陥（Ｂulk Ｍicro Ｄefect 、酸素析出物）
が生成せず、デバイスプロセスにおいて、結晶欠陥の誘
因となる汚染重金属元素がバルク中の微小欠陥（Ｂulk
Ｍicro defect）にトラップされる。すなわち、イン
トリンシック・ゲッタリング効果（ＩＧ効果）が生ずる
のである。この結果、酸化誘起積層欠陥（Ｏxidation
Ｉnduced Ｓtacking Ｆault）の発生が減少する。A wafer subjected to a defect-free layer treatment is manufactured through a high temperature heat treatment step, so that the oxygen concentration between lattices on the surface of the wafer is reduced. Therefore, micro defects (bulk micro defects, oxygen precipitates) near the wafer surface.
Is not generated, and contaminating heavy metal elements that are the cause of crystal defects in the device process
Micro defect). That is, the intrinsic gettering effect (IG effect) occurs. As a result, oxidation-induced stacking faults (Oxidation)
Induced Stacking Fault) is reduced.

【０００４】一般にＩＧ効果は製造歩留りの向上とデバ
イスの信頼性の向上に役立つといわれている。It is generally said that the IG effect is useful for improving manufacturing yield and improving device reliability.

【０００５】[0005]

【発明が解決しようとする課題】無欠陥層処理を行なっ
たウエーハであっても、基板の元の酸化誘起積層欠陥密
度が大きい場合には、所望の酸化誘起積層欠陥密度の低
下が期待できないことがある。Even with a wafer that has been subjected to a defect-free layer treatment, if the original oxidation-induced stacking fault density of the substrate is high, the desired reduction of the oxidation-induced stacking fault density cannot be expected. There is.

【０００６】また、無欠陥層処理を行なうには、相当長
い熱処理時間が必要であり、そのため、製造効率が悪く
なる欠点がある。In addition, the treatment of the defect-free layer requires a considerably long heat treatment time, which results in a drawback that the manufacturing efficiency is deteriorated.

【０００７】また、無欠陥層処理を行なったウエーハに
あっては、結晶中の格子間の酸素を析出させてしまうた
め、ウエーハの機械的強度が低下し、スリップ等が生じ
やすくなる。Further, in a wafer which has been subjected to a defect-free layer treatment, interstitial oxygen in the crystal is deposited, so that the mechanical strength of the wafer is lowered and slips and the like are likely to occur.

【０００８】この発明は前述のような従来技術の欠点を
解消して、結晶欠陥密度を大幅に低減したシリコンウエ
ーハを提供することを目的としている。An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a silicon wafer having a significantly reduced crystal defect density.

【０００９】[0009]

【課題を解決するための手段】本発明は、水素ガスの雰
囲気下においてシリコンウエーハを１０００℃から１３
５０℃の温度範囲に少なくとも３０分間滞留させて熱処
理を施し、平均酸化誘起積層欠陥密度を熱処理前に比較
して約１／５以下にすることを特徴とするシリコンウエ
ーハの製造方法を要旨としている。According to the present invention, a silicon wafer is heated from 1000 ° C. to 13 ° C. in an atmosphere of hydrogen gas.
The gist is a method for manufacturing a silicon wafer, which is characterized in that an average oxidation-induced stacking fault density is reduced to about ⅕ or less as compared with that before heat treatment by allowing it to stay in a temperature range of 50 ° C. for at least 30 minutes. .

【００１０】[0010]

【実施例】この発明の別の態様では、水素ガスの雰囲気
下において１０００℃から１３５０℃の温度範囲に少な
くとも３０分間滞留させる熱処理を施した後に、乾燥酸
素ガス雰囲気中で１６時間熱処理を行い、エッチングを
した場合の表面の酸化誘起積層欠陥密度が、水素ガス雰
囲気中で熱処理をする前の密度１／５以下であることを
特徴とするシリコンウエーハが提供される。EXAMPLE In another embodiment of the present invention, a heat treatment is carried out in a hydrogen gas atmosphere in a temperature range of 1000 ° C. to 1350 ° C. for at least 30 minutes, followed by a heat treatment in a dry oxygen gas atmosphere for 16 hours, There is provided a silicon wafer characterized in that the density of oxidation-induced stacking faults on the surface after etching is 1/5 or less of the density before heat treatment in a hydrogen gas atmosphere.

【００１１】Ｈ2 ガスは、Ｈ2 ガス１００％のものでも
よいし、またＮ2 ガスや不活性ガスあるいはこれらの混
合ガスで希釈されたものであってもよい。後者の場合、
Ｈ2の含有割合を１０％以上にするのが望ましい。The H 2 gas may be 100% H 2 gas, or may be diluted with N 2 gas, an inert gas or a mixed gas thereof. In the latter case,
It is desirable that the content ratio of H 2 be 10% or more.

【００１２】なお、この発明は半導体用のチョコラルス
キー引き上げ法（ＣＺ法）により育成するシリコン単結
晶の製造方法を含むものである。The present invention includes a method for producing a silicon single crystal grown by the Czochralski pulling method (CZ method) for semiconductors.

【００１３】シリコン単結晶をＨ2 ガスの雰囲気下で高
温にて熱処理することにより、熱処理によって誘起され
る結晶欠陥密度を大幅に低減することができる。しか
も、このような熱処理であると、他の特性に影響を与え
ることがなく、実用上の作用効果が大である。By heat-treating a silicon single crystal at a high temperature in an atmosphere of H 2 gas, the crystal defect density induced by the heat treatment can be significantly reduced. Moreover, such heat treatment does not affect other characteristics, and has a large practical effect.

【００１４】実施例１ 同一のＣＺ―シリコン単結晶インゴットの同一領域から
切り出したn タイプ、２０Ωcm程度で面方位（１００）
のミラーウエーハを、Ｎ2 １００％ガスあるいはＨ2 １
００％ガスの雰囲気下において熱処理温度、熱処理時間
をかえて熱処理をした。さらに、これらのウエーハを乾
燥Ｏ2 ガス雰囲気下において、１０００℃にて１６時間
熱処理したのち、ライトエッチング（Ｗright etchin
g ）を行なった。 Example 1 n-type cut from the same region of the same CZ-silicon single crystal ingot, plane orientation (100) at about 20 Ωcm.
Of the mirror wafer of N 2 100% gas or H 2 1
The heat treatment was performed in an atmosphere of 00% gas by changing the heat treatment temperature and the heat treatment time. Further, these wafers were heat-treated at 1000 ° C. for 16 hours in a dry O 2 gas atmosphere and then subjected to light etching (Wright etchin).
g) was performed.

【００１５】ライトエッチングを行なったサンプルにつ
いて、顕微鏡を使って酸化誘起積層欠陥密度を測定し
た。その結果を第１図と第２図に示す。第１図は、熱処
理時間を３０分として熱処理温度を８００℃から１３５
０℃まで変えたときの酸化誘起積層欠陥の発生状況を示
す。第２図は、熱処理温度を１１００℃として熱処理時
間を０時間から１００時間まで変えたときの酸化誘起積
層欠陥の発生状況を示す。この結果から、Ｎ2 アニー
ル、Ｈ2 アニールを行なった場合の方が、行なわない場
合よりも、酸化誘起積層欠陥の発生頻度は低く、さらに
Ｎ2 アニールサンプルよりもＨ2 アニールサンプルの方
が、酸化誘起積層欠陥の発生頻度が低いことが明らかで
ある。Ｎ2 アニールサンプルよりもＨ2 アニールサンプ
ルの方が酸化誘起積層欠陥の発生頻度が低いことから、
酸化誘起積層欠陥の低減に関して、ウエーハ表面近傍の
酸素の外方拡散による効果以外に、Ｈ2 アニールによる
効果が確認される。The oxidation-induced stacking fault densities of the light-etched samples were measured with a microscope. The results are shown in FIGS. 1 and 2. FIG. 1 shows that the heat treatment time is 30 minutes and the heat treatment temperature is from 800 ° C. to 135 ° C.
The occurrence status of oxidation-induced stacking faults when the temperature is changed to 0 ° C. is shown. FIG. 2 shows the state of generation of oxidation-induced stacking faults when the heat treatment temperature is 1100 ° C. and the heat treatment time is changed from 0 hour to 100 hours. This result, N 2 annealing, who when performed with H 2 anneal, than the case of not performing, the frequency of occurrence of oxidation induced stacking faults is low, the direction of H 2 annealing samples than further N 2 anneal sample, It is clear that the frequency of occurrence of oxidation-induced stacking faults is low. Since the direction of H 2 anneal sample has a lower incidence of oxidation induced stacking faults than N 2 anneal sample,
Regarding the reduction of oxidation-induced stacking faults, the effect of H 2 annealing is confirmed in addition to the effect of outward diffusion of oxygen near the wafer surface.

【００１６】この実験から、Ｈ2 ガス雰囲気下における
熱処理により酸化誘起積層欠陥の発生が抑制されること
が明らかになった。From this experiment, it was clarified that the heat treatment under the H 2 gas atmosphere suppresses the generation of the oxidation-induced stacking fault.

【００１７】第１図および第２図から明らかなように、
熱処理時間は３０分間以上が適切である。好ましくは９
０分間から４時間が生産性やコストの面から好ましい。
また、熱処理温度は１０００℃〜１３５０℃までの温度
範囲が適当である。好ましくは１１００℃以上が良い。As is apparent from FIGS. 1 and 2,
A heat treatment time of 30 minutes or more is suitable. Preferably 9
0 minutes to 4 hours is preferable in terms of productivity and cost.
Further, the heat treatment temperature is appropriately in the temperature range of 1000 ° C to 1350 ° C. It is preferably 1100 ° C. or higher.

【００１８】実施例２ Ｐタイプ、１０Ωcm程度でチョコラルスキー法により引
き上げた方位〔１００〕のシリコン単結晶の隣接する２
つのブロックを取出した。これらのブロックは直径１２
５mmで、長さが５cmであった。これら２つのブロックの
一方をＨ2 １００％ガスの雰囲気下で１２００℃にて４
８時間熱処理した。このブロックともう１つのブロック
とを通常のミラーウエーハに加工した後、前述の実施例
１と同じ酸化誘起積層欠陥密度の検査を実施した。その
結果、Ｈ2 ガス雰囲気で熱処理したブロックから切出し
たウエーハの酸化誘起積層欠陥密度は平均１０個／ｃｍ
2であった。これに対し、Ｈ2 ガスで熱処理しなかった
方のブロックから切出したウエーハの酸化誘起積層欠陥
密度は平均８０個／ｃｍ2 であり、Ｈ2 雰囲気下におけ
る熱処理による酸化誘起積層欠陥の発生の抑制効果が確
認された。 Example 2 Adjacent two silicon single crystals of P type having a direction of [100] pulled by the Czochralski method at about 10 Ωcm.
I took out two blocks. These blocks have a diameter of 12
The length was 5 mm and the length was 5 cm. One of these two blocks is heated at 1200 ° C. in an atmosphere of 100% H 2 gas for 4 hours.
Heat treated for 8 hours. After processing this block and another block into an ordinary mirror wafer, the same inspection for the oxidation-induced stacking fault density as in the above-described Example 1 was performed. As a result, the average number of oxidation-induced stacking fault densities of the wafers cut from the blocks heat-treated in the H 2 gas atmosphere was 10 / cm.
Was 2 . On the other hand, the density of the oxidation-induced stacking faults of the wafer cut out from the block not heat-treated with H 2 gas is 80 / cm 2 on average, and the generation of the oxidation-induced stacking faults due to the heat treatment in the H 2 atmosphere is suppressed. The effect was confirmed.

【００１９】実施例３ 同一のＣＺ―シリコン単結晶インゴットの同一領域から
切り出したn タイプ、２０Ωcm程度で面方位（１００）
のミラーウエーハを、表３に示すように、Ｈ2１００％
ガスの雰囲気下において１０００℃あるいは１１００℃
にて３０分間熱処理を行ない、さらに一部のサンプルに
ついてミラー表面を鏡面研磨して厚さ５μ分除去した。
これらのウエーハについて前述の実施例１と同じ酸化誘
起積層欠陥密度の検査を実施した。その結果、Ｈ2 ガス
雰囲気で熱処理したままのウエーハとＨ2 ガス雰囲気で
熱処理したのち５μ除去したウエーハとでは、酸化誘起
積層欠陥密度はほぼ同じであり、１０００℃でのＨ2 ア
ニールでは平均５０個／ｃｍ2 であり、１１００℃では
平均３０個／ｃｍ2 であった。一方、Ｈ2 ガス雰囲気で
熱処理しなかったウエーハの酸化誘起積層欠陥密度は平
均３００個／ｃｍ2であった。 Example 3 n-type cut from the same region of the same CZ-silicon single crystal ingot, plane orientation (100) at about 20 Ωcm.
As shown in Table 3, H 2 100%
1000 ℃ or 1100 ℃ under gas atmosphere
Was heat-treated for 30 minutes, and the mirror surface of some of the samples was mirror-polished to remove the thickness of 5 μm.
These wafers were tested for the same oxidation-induced stacking fault density as in Example 1 above. As a result, in the 5μ removed the wafer after heat-treated at wafer and H 2 gas atmosphere while subjected to heat treatment in a H 2 gas atmosphere, oxidation induced stacking fault density is substantially the same, the average of H 2 anneal at 1000 ° C. 50 The number of particles / cm 2 was 30 / cm 2 on average at 1100 ° C. On the other hand, the oxidation-induced stacking fault density of the wafer that was not heat-treated in the H 2 gas atmosphere was 300 on average / cm 2 .

【００２０】この実験により、Ｈ2 ガス雰囲気下におけ
る熱処理による酸化誘起積層欠陥の低減効果は、さらに
５μ程度ミラー表面を研磨により除去しても、失われな
いことが明らかになった。From this experiment, it was revealed that the effect of reducing the oxidation-induced stacking faults by the heat treatment in the H 2 gas atmosphere is not lost even if the mirror surface is further removed by polishing by about 5 μm.

【００２１】実施例４ 同一のＣＺ―シリコン単結晶インゴットの同一領域から
切り出したn タイプ、２０Ωcm程度で面方位（１００）
のミラーウエーハを、Ｈ2 ガスとＡr ガスとを混合した
雰囲気下において、１１００℃にて３０分間熱処理し
た。これらのウエーハについて前述の実施例１と同じ酸
化誘起積層欠陥密度の検査を実施した。 Example 4 n-type cut from the same region of the same CZ-silicon single crystal ingot, plane orientation (100) at about 20 Ωcm
The mirror wafer of 1 was heat-treated at 1100 ° C. for 30 minutes in an atmosphere in which H 2 gas and Ar gas were mixed. These wafers were tested for the same oxidation-induced stacking fault density as in Example 1 above.

【００２２】その結果、第３図に示すように、混合ガス
中のＨ2 の割合が減少するにつれ、酸化誘起積層欠陥が
発生しやすくなる傾向があることが示され、Ｈ2 ガスの
割合が１０％以下の場合には、この熱処理による酸化誘
起積層欠陥の抑制効果はみられない。[0022] As a result, as shown in FIG. 3, as the ratio of H 2 mixed gas is reduced, oxidation induced stacking faults indicated that tend to be easily generated, the ratio of H 2 gas When it is 10% or less, the effect of suppressing the oxidation-induced stacking fault by this heat treatment is not observed.

【００２３】この実験結果から明らかなように、Ｈ2 と
Ｎ2 または不活性ガスを混合する場合、Ｈ2 ガスの含有
割合を１０％以上にするのが適当である。As is clear from the results of this experiment, when H 2 and N 2 or an inert gas is mixed, it is appropriate that the content ratio of H 2 gas be 10% or more.

【００２４】[0024]

【発明の効果】この発明によれば、結晶欠陥密度の低減
効果が極めて顕著であり、しかも短時間の処理であって
も有効な結果が得られる。特に酸化誘起積層欠陥の密度
の点で歩留まりの悪かったn タイプにあっては、高抵抗
品であっても、本発明によれば、平均酸化誘起積層欠陥
密度が約１／５に減少した。According to the present invention, the effect of reducing the crystal defect density is extremely remarkable, and moreover, effective results can be obtained even by a short-time treatment. Particularly in the case of the n-type, which has a poor yield in terms of the density of oxidation-induced stacking faults, the average oxidation-induced stacking fault density is reduced to about ⅕ according to the present invention even if it is a high resistance product.

【００２５】なお、無欠陥層（Ｄenuded Ｚone ）処理
とＨ2 ガスの熱処理とは全く別の処理であり、例えば、
Ｈ2 ガスの熱処理と無欠陥層処理を組み合わせることも
可能である。一般的にいって、この無欠陥層処理は特殊
な用途に限られており、通常、ウエーハには施さない。The defect-free layer treatment and the H 2 gas heat treatment are completely different treatments.
It is also possible to combine the heat treatment of H 2 gas and the defect-free layer treatment. Generally speaking, this defect-free layer treatment is limited to special applications and is not usually applied to wafers.

【００２６】なお、本願発明は前述の実施例に限定され
ず次の実施態様も含むものである。The invention of the present application is not limited to the above-mentioned embodiments and includes the following embodiments.

【００２７】温度範囲が１１００℃から１３５０℃であ
ることを特徴とする特許請求の範囲に記載のシリコンウ
エーハの製造方法。The method for producing a silicon wafer according to the claims, characterized in that the temperature range is from 1100 ° C to 1350 ° C.

【００２８】滞留温度が９０分から４時間であることを
特徴とする特許請求の範囲に記載のシリコンウエーハの
製造方法。The method for producing a silicon wafer according to claim 1, wherein the residence temperature is 90 minutes to 4 hours.

【００２９】Ｈ2 ガスがＨ2 ガス１００％である特許請
求の範囲に記載のシリコンウエーハの製造方法。The method for producing a silicon wafer according to the claims, wherein the H 2 gas is 100% H 2 gas.

【００３０】Ｈ2 ガスがＮ2 ガス、不活性ガスまたはこ
れらの混合ガスで希釈されたものである特許請求の範囲
に記載のシリコンウエーハの製造方法。The method for producing a silicon wafer according to claim 1, wherein the H 2 gas is diluted with N 2 gas, an inert gas or a mixed gas thereof.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の効果を示すためのグラフ。FIG. 1 is a graph showing the effect of the present invention.

【図２】本発明の効果を示すためのグラフ。FIG. 2 is a graph showing the effect of the present invention.

【図３】本発明の効果を示すためのグラフ。FIG. 3 is a graph showing the effect of the present invention.

【符号の説明】[Explanation of symbols]

なし None

───────────────────────────────────────────────────── フロントページの続き (72)発明者 赤井 賢二 山形県西置賜郡小国町大字小国町378番地 東芝セラミックス株式会社小国製造所内 (72)発明者 今 武志 山形県西置賜郡小国町大字小国町378番地 東芝セラミックス株式会社小国製造所内 (72)発明者 中西 宏円 山形県西置賜郡小国町大字小国町378番地 東芝セラミックス株式会社小国製造所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Akai 378, Oguni-machi, Oguni-cho, Nishikitama-gun, Yamagata Prefecture Inside the Oguni Factory, Toshiba Ceramics Co., Ltd. (72) Inventor Hiromichi Nakanishi 378, Oguni Town, Oguni Town, Nishiokitama District, Yamagata Prefecture

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 水素ガスの雰囲気下においてシリコンウ
エーハを１０００℃から１３５０℃の温度範囲に少なく
とも３０分間滞留させて熱処理を施し、平均酸化誘起積
層欠陥密度を熱処理前に比較して約１／５以下にするこ
とを特徴とするシリコンウエーハの製造方法。1. A silicon wafer is retained in a temperature range of 1000 ° C. to 1350 ° C. for at least 30 minutes in a hydrogen gas atmosphere for heat treatment, and the average oxidation-induced stacking fault density is about 1/5 of that before heat treatment. A method for manufacturing a silicon wafer, including the following:
JP6234476A 1994-09-05 1994-09-05 Manufacturing method of silicon wafer Expired - Lifetime JP2652346B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6234476A JP2652346B2 (en) 1994-09-05 1994-09-05 Manufacturing method of silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6234476A JP2652346B2 (en) 1994-09-05 1994-09-05 Manufacturing method of silicon wafer

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP26135185A Division JPS62123098A (en) 1985-11-22 1985-11-22 Silicon single crystal

Publications (2)

Publication Number Publication Date
JPH07165496A true JPH07165496A (en) 1995-06-27
JP2652346B2 JP2652346B2 (en) 1997-09-10

Family

ID=16971621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6234476A Expired - Lifetime JP2652346B2 (en) 1994-09-05 1994-09-05 Manufacturing method of silicon wafer

Country Status (1)

Country Link
JP (1) JP2652346B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030052464A (en) * 2001-12-21 2003-06-27 주식회사 실트론 A method for heat-treatment of silicon wafer in high temperature

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134071A (en) * 1975-05-16 1976-11-20 Nippon Denshi Kinzoku Kk Method to eliminate crystal defects of silicon
JPS5885534A (en) * 1981-11-18 1983-05-21 Komatsu Denshi Kinzoku Kk Manufacture of semiconductor silicon

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134071A (en) * 1975-05-16 1976-11-20 Nippon Denshi Kinzoku Kk Method to eliminate crystal defects of silicon
JPS5885534A (en) * 1981-11-18 1983-05-21 Komatsu Denshi Kinzoku Kk Manufacture of semiconductor silicon

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030052464A (en) * 2001-12-21 2003-06-27 주식회사 실트론 A method for heat-treatment of silicon wafer in high temperature

Also Published As

Publication number Publication date
JP2652346B2 (en) 1997-09-10

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