JPH07162676A - Picture data processor, picture reduction device and picture magnification device - Google Patents

Abstract

PURPOSE:To process picture data so as to perform normal gradation expression without being accompanied by the degradation of picture quality. CONSTITUTION:A controller 1 outputs picture element read clocks (a) to a CCD line sensor 2 and a pattern selection signal generator 3 and outputs magnification setting input (c) to the pattern selection signal generator 3. The pattern signal generator 3 outputs pattern selection signals (f) to a 4-to-1 selector 6 in a cycle corresponding to the magnification setting input (c). A pattern memory 5 utilizes a dither method and successively stores the threshold value data of one row among the threshold value data constituted of a 4X4 matrix. The four pieces of the threshold value data constituting one row are successively and selectively outputted from the 4-to-1 selector 6 operated in response to the input of the pattern selection signals (f). A comparator 4 binarizes analog picture data by comparing the analog picture data (b) from the CCD line sensor 2 with analog threshold value data (g) from a D/A converter 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus for performing processing necessary for reducing or enlarging an image on serially input image data, and an image enlarging apparatus using this image data processing apparatus. Regarding a reduction device.

[0002]

2. Description of the Related Art As a conventional image data processing apparatus, the one shown in FIG. 9 is known. That is, the CCD line sensor 31 outputs the analog image data to the comparator 33 in synchronization with the read clock output from the controller 32. The pattern memory 34 configured by the memories 1 to 4 stores four threshold value data forming one row among the threshold value data configured by the 4 × 4 matrix using the dither method. The four threshold value data stored in the pattern memory 34 are input to the comparator 33 via the D / A converter 35 in synchronization with the pattern selection signal output from the controller 32 at the same timing as the read clock. The comparator 33 is
As shown in FIG. 10, analog image data from the CCD line sensor 31 and a threshold value input via the D / A converter 35 (hereinafter, the threshold values are corresponding memory numbers 1 to 1).
4 is shown. ) Are compared with each other to binarize the analog image data. The binarized data is stored in the pixel memory 36 with data for one screen, and then output to an external printer or the like via the controller 32.

Further, when reducing the image, the controller 32 thins out the inputted binarized data at a frequency according to the reduction ratio and then stores it in the pixel memory 36. That is, as shown in FIG. 11, when the image is reduced by a factor of 1/2, every other pixel of the binarized data is thinned out and then stored in the pixel memory 36, as indicated by the mark x. Therefore, 1 after the pixel thinning stored in the pixel memory 36
By operating the printer based on the binarized data for the screen, it is possible to print out the image reduced to 1/2.

[0004]

In such a conventional apparatus, when pixel thinning is not performed, as shown in FIG. 10, all data binarized by a plurality of different thresholds are used. , Can perform normal grayscale expression. However, as shown in FIG.
If compressed to 2, the data binarized by the thresholds “2” and “4” will be lost, and only the data binarized by the thresholds “1” and “3” will be lost, so normal grayscale expression cannot be performed. Will end up. That is, since the periodicity of the dither pattern is destroyed, the halftone due to the dither pattern cannot be reproduced.

Therefore, as shown in FIG. 12, pixel thinning is performed so that binarized data using the threshold values "1", "2", "3" and "4" are sequentially arranged in the thinned data sequence. A device for performing the above has also appeared, and such a device can perform normal grayscale expression. However, when such pixel thinning is performed, the data after thinning has a deviation of pixels from the original image, so that the image quality deteriorates even if normal grayscale expression is possible.

The present invention has been made in view of such conventional problems, and an image data processing apparatus and an image enlarging / reducing apparatus for processing image data so that normal gradation expression can be performed without deterioration in image quality. The purpose is to provide a device.

[0007]

In order to solve the above problems, according to the present invention, an image data input means for inputting image data at a predetermined cycle and a storage means for storing a plurality of threshold values forming a dither pattern. A threshold output means for sequentially outputting the plurality of threshold values stored in the storage means, and an output cycle variable for changing an output cycle of the threshold output means with respect to the input cycle according to an enlargement / reduction ratio of an image. Means and
The gist of the present invention is to have a binarizing unit that binarizes the image data based on a threshold value sequentially output from the threshold value output unit at a cycle corresponding to the magnification.

[0008]

In the above structure, when the image is reduced to 1/2, for example, the output cycle changing means changes the output cycle of the threshold output means to be twice as large as that at the same size.
Then, when binarizing the image data input from the input unit, the binarizing unit binarizes the doubled image data using the same threshold value. Therefore, with the same threshold, 2
1/2 of the binarized image data is sequentially thinned out, and by using the binarized data after thinning out the pixels,
It is possible to display or print the image reduced in size.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. That is, as shown in FIG.
The pixel read clock a output from the above is input to the CCD line sensor 2 and the pattern selection signal generator 3. The CCD line sensor 2 uses the pixel read clock a
In synchronism with the above, the analog image data b corresponding to one pixel is sequentially input to the comparator 4. Also, the controller 1
From, a magnification setting input c, a reset input d, which will be described later, and a 1/2 phase shift read clock e (both see FIG. 2).
Is output to the pattern selection signal generator 3, and the pattern selection signal generator 3 outputs the pattern selection signal f to the 4to1 selector 6.

On the other hand, the pattern memory 5 sequentially stores one row of threshold data among the threshold data composed of a 4 × 4 matrix using the dither method. The four threshold value data forming one row are sequentially and selectively output from the 4to1 selector 6 that operates in response to the input of the pattern selection signal f. This selectively output threshold data g
Is converted into analog data by the D / A converter 7 and input to the comparator 4. Comparator 4
Is analog image data b from the CCD line sensor 2.
And the analog threshold value data g from the D / A converter 7 are compared to binarize the analog image data and input the binarized data h to the controller 1. The binarized data h is stored in the pixel memory 8 with data for one screen, and then sent as image data i to an external printer or the like via the controller 32.

FIG. 2 shows the details of the pattern selection signal generator 3. The shift register 8 has an n-stage configuration, and the data fed back to the first register is the scale setting input c. A given nto1 selector 9 selects from the 1st to nth shift registers 8. The output of the shift register 8 takes the count valid / invalid selection output j from the first, and this count valid / invalid selection output j is input to the AND gate 10 together with the pixel read clock a.

Therefore, the AND gate 10 sets the pattern selection clock k to 2b at the timing when the count valid / invalid selection output j and the pixel read clock a match.
It is output to the it counter 11. 2 bit counter 11
Is the input timing of the pattern selection clock k, 0,
The pattern selection signal f that changes as 1, 2, 3 is input to the 4to1 selector 6, and the 4to1 selector 6 selects one of the four threshold value data (1 data, 2 data, 3 data, 4 data) forming one row. , The input value 0, 1, 2, 3
The threshold data g (0: 1 data, 1: 2 data, 2: 3 data, 3: 4 data) corresponding to is output to the D / A converter 7.

Next, the operation of this embodiment having the above configuration will be described with reference to the timing chart shown in FIG.
That is, the analog image data b is output from the CCD line sensor 2 to the comparator 4 in synchronization with the pixel read clock a from the controller 1. On the other hand, when the reset input d is set to “L”, only the first shift register 8 is in the state “1”, and the other n−1 pieces are all “0”.
Becomes Then, in the case of halving the image, the selection output “2” of the nto1 selector 9 is input by the magnification setting input c.
Is selected (SELECT2), and the reset input is set to "H".

Then, the AND gate 10 calculates the logical product of the count valid / invalid selection output j and the read clock a and outputs the pattern signal selection clock k only once for every two read clocks a. Therefore, 2
The bit counter 11 advances in a cycle twice as long as the cycle of the read clock to output the pattern selection signal f of “0” to “3”, and the 4to1 selector 6 synchronizes with the pattern selection signal f. Out of the four threshold data (1 data, 2 data, 3 data, 4 data) that make up one row,
Data corresponding to the input value (0: 1 data, 1: 2
Data, 2: 3 data, 3: 4 data) is output to the D / A converter 7.

Therefore, the comparator 4 is supplied with threshold value data that changes at a cycle twice as long as the cycle of the pixel read clock a, and at the same time, the analog image data b for one pixel is output at the timing of the pixel read clock a. Is entered. Therefore, in the comparator 4, each image data corresponding to two adjacent pixels is binarized with the same threshold value data, and this binarized image data is input to the controller 1. Then, the controller 1 thins out only the image data corresponding to one pixel from the image data corresponding to two adjacent pixels binarized with the same threshold value data, and then sets the pixel data in the pixel memory 8.

Therefore, 1 stored in the pixel memory 8
For screen image data, 1/2 for one screen
Pixels are thinned out and compressed to 1/2. Therefore, the binarized data compressed to ½ is read from the pixel memory 8 and the LCD or the printer is driven to obtain an image reduced to ½ of the normal size. be able to. Further, the compressed image data for displaying this image is configured by thinning out one of the image data corresponding to two adjacent pixels binarized with the same threshold value data as described above. Therefore, the image data binarized by all the threshold data is included (has the periodicity of the dither pattern), and the data after thinning has a deviation of pixels from the original image. Absent. Therefore, by including the image data binarized by all the threshold value data, normal grayscale expression is possible, and the image quality is deteriorated because the data after thinning does not have a pixel deviation with respect to the original image. You can get images without.

The magnification setting input is 1/2 (SELECT
If T2) is left as it is, the output image is completely halved, but as shown in FIG. 3, the magnification can be sequentially changed.

FIG. 4 shows a second embodiment of the present invention, which is different from the first embodiment described above only in that a frequency variable device 13 is used in place of the pattern selection signal generator 3. There is. The frequency varying device 13 changes the cycle of the pixel read clock a output from the controller 1 according to the value of the magnification setting input c, and outputs it as a threshold sending clock m to the 4to1 selector 6.

That is, the value of the magnification setting input c is set to "1 /
In the case of 2 ″ times, the frequency variable device 13 outputs the threshold sending clock m to the 4to1 selector 6 at a cycle of ½ times the pixel read clock a. Therefore, the D / A converter 7 outputs the comparator. As shown in FIG. 5, the threshold value data g sent to 4 changes at a cycle 1/2 times that of the analog image data b for one pixel input at the cycle of the pixel read clock a. Therefore, in the comparator 4, each image data “D1, D2” “D2, D3” ... Corresponding to two adjacent pixels.
Will be binarized with the same threshold value data.
The binarized data h is input to the controller 1. Then,
Of the image data corresponding to two adjacent pixels binarized with the same threshold value data, the controller 1 thins out only the image data corresponding to one pixel,
It is stored in the pixel memory 8.

Therefore, in the compressed data n stored in the pixel memory 8, 1/2 pixels for one screen are thinned and compressed to 1/2. Since the compressed data n for displaying this image is configured by thinning out one of the image data corresponding to two adjacent pixels binarized with the same threshold value data, as shown in FIG. The image data including the image data binarized by the threshold data (1, 2, 3, 4) is included, and the data after thinning does not have a pixel deviation with respect to the original image. Therefore, by including the image data binarized by all the threshold value data, normal grayscale expression is possible, and the image quality is deteriorated because the data after thinning does not have a pixel deviation with respect to the original image. Can be avoided.

Further, when the value of the magnification setting input c is set to "1/4", the frequency variable device 13 sends the threshold transmission clock to the 4to1 selector 6 at a cycle four times as long as the cycle of the pixel read clock a. Output m. Therefore, D /
The threshold value data g sent from the A converter 7 to the comparator 4 is, as shown in FIG. 6, analog image data b for one pixel input at the cycle of the pixel read clock a.
However, it changes in a cycle of four times. Therefore, in the comparator 4, each image data “D1, D2, D3, D4” ... Corresponding to four adjacent pixels is binarized with the same threshold data, and this binarized image The data is input to the controller 1. Then, the controller 1 binarizes four adjacent fours with this same threshold value data.
Of the image data corresponding to one pixel, for example, the image data corresponding to three pixels other than the image data corresponding to the first pixel are thinned out, and then stored in the pixel memory 8.

Therefore, in the compressed data n stored in the pixel memory 8, 3/4 pixels for one screen are thinned and compressed to 1/4. The compressed data n for displaying this image is formed by thinning out the pixel data corresponding to three pixels from the image data corresponding to four adjacent pixels binarized with the same threshold value data. Therefore, all threshold data (1, 2, 3,
4) The image data binarized is included, and the data after thinning does not have a pixel deviation with respect to the original image.

When the value of the magnification setting input c is set to "2" times, the frequency variable device 13 sends the threshold transmission clock to the 4to1 selector 6 at a cycle 1/2 times the cycle of the pixel read clock a. Output m. Therefore, as shown in FIG. 7, the threshold value data g sent from the D / A converter 7 to the comparator 4 is 1 with respect to the analog image data b for one pixel input in the cycle of the pixel read clock a. It changes in a cycle of / 2. Therefore, in the comparator 4, each image data “D” corresponding to one pixel is
1 "" D2 "... Is binarized twice with different threshold data, and the binarized image data is input to the controller 1. Then, the controller 1 The binarized image data is stored as it is in the pixel memory 8. Therefore, by reading the binarized data from the pixel memory 8 and driving the LCD or the printer, the binarized image data is set to 2 at the same magnification. A double magnified image can be obtained.

Further, when the value of the magnification setting input c is set to "4" times, the frequency variable device 13 sends the threshold sending clock to the 4to1 selector 6 at a cycle of 1/4 times the cycle of the pixel read clock a. Output m. Therefore, D / A
The threshold value data g sent from the converter 7 to the comparator 4 is, as shown in FIG.
With respect to the analog image data b for one pixel which is input in the cycle of, the change is made in the cycle of 1/4. Therefore, in the comparator 4, each image data “D” corresponding to one pixel is
1 "" D2 "... is binarized four times in succession with different threshold data, and the binarized image data is input to the controller 1. Then, the controller 1 The binarized image data is stored as it is in the pixel memory 8. Therefore, by reading this binarized data from the pixel memory 8 and driving the LCD or the printer, the binarized image data is 4 times as large as that at the same magnification. A double magnified image can be obtained.

In the second embodiment, the case where the image is multiplied by an integer or multiplied by an integer is shown. However, even if the magnification is a fraction of a fraction or a magnification including a fraction, the reciprocal of this magnification is used. By changing the frequency of the threshold transmission clock m, an enlarged or reduced image can be obtained.

[0026]

As described above, according to the present invention, the threshold value is changed in a cycle corresponding to the enlargement / reduction ratio of the image, and the image data is binarized based on the threshold value changed in this cycle. Therefore, the binarized image data can be thinned out without causing pixel deviation with respect to the original image, and as a result, the image data can be reduced and reduced so that normal grayscale expression can be performed without deterioration in image quality. It can be enlarged.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a pattern selection signal generator of the same embodiment.

FIG. 3 is a timing chart showing the operation of the embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a timing chart showing an operation at 1/2 time of the embodiment.

FIG. 6 is a timing chart showing an operation at 1/4 times of the embodiment.

FIG. 7 is a timing chart showing an operation of the embodiment at the time of doubling.

FIG. 8 is a timing chart showing an operation at a time of 4 times that of the embodiment.

FIG. 9 is a block diagram showing a conventional device.

FIG. 10 is an explanatory diagram of a binarization process of the apparatus.

FIG. 11 is an explanatory diagram of processing performed by the same device at the time of ½ times.

FIG. 12 is an explanatory diagram of another process of the apparatus at the time of ½ times.

[Explanation of symbols]

 1 controller 2 CCD line sensor 3 pattern selection signal generator 4 comparator 5 pattern memory 13 frequency variable device

Claims (3)

[Claims] 1. An image data input means for inputting image data at a predetermined cycle, a storage means for storing a plurality of threshold values forming a dither pattern, and a plurality of threshold values stored in the storage means are sequentially output. Threshold output means, output cycle changing means for changing the output cycle of the threshold output means with respect to the input cycle in accordance with the enlargement / reduction ratio of the image, and sequentially output from the threshold output means in a cycle according to the magnification. And a binarizing unit that binarizes the image data based on a threshold value. 2. An image data input means for inputting image data at a predetermined cycle, a storage means for storing a plurality of threshold values forming a dither pattern, and a plurality of threshold values stored in the storage means are sequentially output. Threshold output means, output cycle changing means for changing the output cycle of the threshold output means with respect to the input cycle in accordance with the reduction ratio of the image, and the image data input means sequentially outputting the cycle in accordance with the scale. A binarizing unit that binarizes the image data based on a threshold value, and image data that thins out the image data binarized by the binarizing unit at a frequency according to the reduction ratio of the image and outputs the thinned image data. An image reducing device comprising: an output unit. 3. An image data input means for inputting image data at a predetermined cycle, a storage means for storing a plurality of threshold values forming a dither pattern, and a plurality of threshold values stored in the storage means are sequentially output. Threshold output means, output cycle varying means for changing the output cycle of the threshold output means with respect to the input cycle in accordance with the enlargement ratio of the image, and the image data input means sequentially outputting the cycle in accordance with the magnification. An image enlarging means for binarizing the image data on the basis of a threshold value, and an image data output means for outputting the image data binarized by the binarizing means. apparatus.