JPH0267092A - Signal processing circuit for video printer - Google Patents

Abstract

PURPOSE:To segment the specific part of an input image and to print it on photographic paper as plural same pictures by performing control on the sampling timing of a video signal, address control on a line memory, and input control to a thermal head. CONSTITUTION:A signal inputted as a still picture is written on a storage means 1002, and is inputted to a head driving means 1003, then, drives a head 1004. At this time, an offset value is inputted from an offset means 1006 to a write/ readout means 1005, which designates the print area of the input image. The readout/write means 1005 controls write and readout on the storage means 1002 based on the print area, and also, controls the head driving means 1003, and the head 1004 performs the multipicture print of an image in the print area of the input image. Thereby, the multipicture print can be performed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a signal processing circuit for a video printer that obtains a print image from a video signal. The present invention relates to a signal processing circuit capable of processing signals.

[Prior Art] Conventionally, as a signal processing circuit for a video printer that obtains a print image from a video signal, for example, Japanese Patent Laid-Open No. 61-18
As described in Publication No. 286, the input video signal (input image) is stored in a memory based on a synchronization signal, and when printing, it is read out from the memory in the same order as the writing order and sent to the thermal head. , to obtain a printed image on photographic paper.

[Problems to be Solved by the Invention] In the above-mentioned existing proposed examples, a technique for printing the entire screen as a print image was described;
There was no disclosure of a multi-screen printing technique in which a portion corresponding to one-fourth or one-half of the screen is cut out and printed on photographic paper as the same four screens or two screens.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a signal processing circuit for a video printer capable of multi-screen printing in which a specific portion of an input image is cut out and printed on the same multiple screens.

[Means to solve the problem]

A video printer sequentially samples an analog video signal input as a still image in units of one vertical line of the still image using an analog/digital conversion means, converts it into digital image data, and stores the image data in a line memory. After that, the image data is read out from the line memory, 0N-OFF data is generated from the image data by the halftone control circuit, and the thermal head reads the 0N-OFF data based on the generated 0N-OFF data. multiple heating elements lined up in a row to generate heat,
The still image is printed vertically one line at a time on photographic paper.

Therefore, in the present invention, in order to achieve the above-mentioned object,
A sampling position determining means that counts each time the thermal head prints one vertical line, and determines the position of one vertical line to be sampled in the still image in the analog/digital conversion means based on the counted value, Loading an offset value from the first offset means at the start of printing, starting counting from the offset value, and when the thermal head prints a desired number of lines, loading the offset value from the first offset means again; Counting is started again from the offset value, and in the address means for outputting the address of the line memory, counting is started from the offset value input from the second offset means, and the counted value is stored in the line memory. 0N-O generated by the halftone control circuit in the thermal head.
A plurality of identical ON-OFF data obtained by branching the FF data is manually generated, and a plurality of heating elements arranged in a line are made to generate heat based on the ON-OFF data.

[Effect]

The sampling position determining means loads an offset value from the first offset means at the start of printing, starts counting from the offset value, and when the thermal head prints a desired number of lines, the sampling position determining means loads the offset value from the first offset means again when the thermal head prints a desired number of lines. Then, the offset value is loaded and counting is started again from the offset value. As a result, the position of one vertical line to be sampled in the still image determined by the sampling position determining means is sequentially shifted from the sampling position corresponding to the offset value every time one line is printed, and the desired line is After several prints, the sample will return to the sampling position corresponding to the offset value. In this way, printing will start from any part of the input image, and after printing the desired number of lines,
The same part of the input image as previously printed is printed, and the same image can be printed multiple times in the horizontal direction.

Furthermore, by changing the offset value output from the first offset means, the position of the print start portion of the input image can be varied.

On the other hand, the address means starts counting from the offset value manually entered by the second offset means, and outputs the counted value as an address of the line memory. As a result, the image data is read from any part of the input image from the line memory. Moreover,
By changing the offset value output from the second offset means, the position of the read portion of the input image can be varied.

Further, the thermal head is configured to output a plurality of identical 0N-OF signals outputted from the halftone control circuit and then branched.
F data is input, and a plurality of heating elements arranged in a line are made to generate heat based on the 0NOFF data. As a result,
The same image can be printed multiple times in the vertical direction.

By simultaneously performing the horizontal multi-screen printing and the vertical multi-screen printing as described above, it is possible to obtain a multi-screen print in which a human image is cut out and printed on the same multiple screens.

〔Example〕

The outline of the present invention will be explained below with reference to FIG.

In FIG. 1, 1001 is an input terminal, 1002 is a storage means, 1003 is a head drive means, 1004 is a head,
1005 is a write/read means, and 1006 is an offset means.

The present invention provides write/read means 1005. The offset means LOO6 and the head drive means 1003 cut out a desired portion of the input image and perform multi-screen printing.

The operation will be explained below.

A signal input as a still image from the input terminal 1001 is stored in the storage means 10 by the writing/reading means 1005.
Written to 02. The signals written in the storage means 1002 are also read out by the writing/reading means 1005 and input to the head driving means 1003. Head driving means 1003 drives head 1004 according to the input signal.

At this time, the writing/reading means 1005 receives an offset value from the offset means 1006, thereby specifying an area of the input image to be printed (hereinafter referred to as print area).

The writing/reading means 1005 controls writing to and reading from the storage means 1002 based on the designated print area, and also controls the head driving means 1003. As a result, the head 1004
Prints the image in the print area part of the input image on multiple screens.

As described above, the writing/reading means 1005, the offset means 1006. The head driving means 1003 can perform multi-screen printing in which a desired portion of the input image is cut out and a plurality of (MXN) identical images are printed.

In this way, the present invention divides into M×N by M vertically and N horizontally.
In the following explanation, M=2. With N=2, the same screen is 4
The explanation will be based on the assumption that each item is printed.

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

In Fig. 2, 1 is an input terminal for inputting the N1'SC video signal a, and 2 is a decoder for decoding the input NTSC system O signal a into RGB signals representing red, green, and blue. 3 is a synchronization separation circuit that separates a synchronization signal from the input NTSC video signal a; 4 is a sampling clock generation circuit that generates sampling clock b; and 5 is an analog/digital (hereinafter referred to as A/D) A/D converter to convert, 6 is 1
A line memory that stores a line's worth of image data (hereinafter simply referred to as data), 7 a write address circuit that outputs a write address of the line memory 6, 8 a read address circuit that outputs a read address of the line memory 6, 9 1 is a halftone control circuit that creates ON-OFF data for driving the thermal head 15 from the data read out from the line memory 6; 10 is a comparator;
13° and 14 are latches. Further, 15 is a thermal head, and this thermal head 15 has a shift register of 16° and 17°.
, a latch group 18.19 connected to this shift register 16.17, a gate group 20.21 connected to this latch group 18.19, and a heating element group 22 connected to this gate group 20.21. , 23. Also, 2
4 is photographic paper, 25 is a platen for wrapping photographic paper 24,
26 is a motor that rotates the platen 25, 27 is a servo that drives the motor 26, 28 is an energization control circuit that controls energization of the thermal head 15, and 29 is a system controller (hereinafter abbreviated as system controller) that controls the operation of the entire circuit. ,3
0 is the RGB signal output from the decoder circuit 2.
an encoder circuit that encodes a C format video signal;
31 is a clamp circuit that generates a black level or white level signal; 32 is a switch that changes the monitor output; 3
3 is an output terminal for monitor output; 34 is a selector for selecting one of the decoded ROB signals; 35 is an offset circuit for offsetting the sampling position; 3
6 is a print line counter for counting the number of print lines; 37 is a decoding circuit; 40 is a switching signal circuit for switching the switch 32 to display the horizontal print area on a monitor (not shown); 41 is a readout circuit; 42 is a switching signal circuit for switching the switch 32 to display the vertical print area on the monitor; 43 is the thermal head 1
This is a switch that changes the input of No. 5. Also, 44.
45 constitutes the sampling clock generation circuit 4; 44 is a print position counter, and 45 is a clock generation circuit. Further, 54 to 58 are input/output signal lines of the read address circuit 8.

The operation during normal printing will be described below with reference to FIG.

NTSC video signal a input from input terminal +1
is a video signal representing a still image, and the decoder circuit 2
After being decoded into ROB signals, the selector 34 selects one color signal from among the ROB signals. The selected signal is sampled and A/D converted in the A/D converter 5 according to the sampling clock b from the sampling clock generation circuit 4. The data obtained by A/D conversion is stored in the line memory 6 at an address specified by the write address circuit 7.

During printing, the read address circuit 8 reads out the data stored in the line memory 6 in the order in which it was stored.

The data read from the line memory 6 is compared with the value of the gradation counter 11 in the halftone control circuit 9 by a comparator 10 to generate ON-OFF data for the thermal head 15. The 0N-OF created by the halftone control circuit 9 in this way
Based on the F data, the thermal head 15 generates heat for each dot, and deposits ink on the photographic paper 24 in accordance with the signal level.

As explained above, when printing for 1947 minutes is completed, the sampling clock generation circuit 4 shifts the generation position (that is, the generation timing) of the sampling clock b by one pixel, and thereafter, in the same manner, for the next one line. Print.

By repeating the above operations, one screen of one color is printed, then the selector 34 is switched to print the next color in the same way, and the three colors are superimposed to obtain a full color print.

Multi-screen printing of the same image will be explained based on the above printing operation.

There are two types of multi-screen printing: vertical direction (perpendicular to the printing direction) as shown in Figure 3(i), and horizontal direction (printing direction) as shown in Figure 3(ii). Multi-screen printing and Figure 3 (iii)
4-screen multi-printing as shown in ) is available.

First, vertical multi-screen printing shown in FIG. 3(i) will be described.

Vertical multi-screen printing requires inputting the same data to multiple inputs of the thermal head 15 and line memory 6.
This is achieved by offsetting the read address of .

In FIG. 2, the operation will be explained first.

During vertical multi-screen printing, the system controller 29 switches the switch 43 to close the latch 1 in the halftone control circuit 9.
3 and the shift register 17 in the thermal head 15 so that the same data is input to the shift registers 16 and 17 in the thermal head 15. Further, during reading, the read address circuit 8 receives an offset value from the offset circuit 41, and increases the address from this value.

The above operation will be explained in more detail using FIGS. 2 to 8.

In FIG. 2, the thermal head 15 is constructed by two people in order to speed up data transfer, and operates to simultaneously receive two inputs using the clock HCK from the energization control circuit 28.

On the other hand, as shown in FIG. 5, data for one line of the input image is stored in the line memory 6 in the same order (ie, 0,
1. ..., 511).

Therefore, when reading from the line memory 6, 0.25
6,1,257,2,258. . . . and read them out alternately, (0, 256), N257), (
2258L... is applied simultaneously to the shift registers 16 and 17 in the thermal head 15.

Further, as shown in FIG. 6, the read address circuit 8 calculates the logical sum of the read clocks CKA and CKB using an OR circuit 53, and calculates the least significant bit (LSB) of the output of the counter 51 that counts the result. As shown in FIG. Further, an adder 52 adds the offset value from the offset circuit 41 and supplies it to the line memory 6 as a read address.

As a result, as shown in FIG. 7, the read address circuit 8
is nm, ni+256. n, +l, nm+257
・・・・・・ n, +255. The read addresses are output in the order of n, +511.

The data read out in this way is latched into latches 13 and 14 in the halftone control circuit 9 by the read clocks CKA and CKB. Here, if the switch 43 is switched to the latch 13 side as described above, the shift registers 16 and 17 in the thermal head 15 have N3. na+1.・・・・・・
, n, l+255 data are input, and a multi-screen divided into two vertically can be printed.

As described above, by giving an arbitrary offset value to the read address by the offset circuit 41, instead of printing two images at the top of the screen as shown in FIG. 4(i), the image shown in FIG. As shown in , it is possible to cut out and print an arbitrary part of the image in the vertical direction of the screen, such as the center of the screen.

Also, when obtaining an input image from a model that outputs separate RGB signals and synchronization signals, such as a computer or an RGB camera,
Each signal may be connected to the RGB output of the decoder circuit 2 and the output of the synchronous separation circuit 3, respectively. Furthermore, for devices that output display signals of 1 and 0, such as a personal computer, a latch may be used in place of the A/D converter 5. In addition, in the case of personal computer input, etc., the halftone control circuit 9 only needs to control whether or not to energize, so the comparator 10 and the tone counter 11 can be deleted and the output from the line memory 6 can be directly latched. It may be connected to 13°14.

Also, input the initial value of the read address from the offset circuit 41 to the switching signal circuit 42, and input the horizontal synchronization signal H and vertical synchronization signal ■ from the synchronization separation circuit 3.
The switching signal circuit 42 generates gate signals corresponding to the horizontal scanning lines at the top and bottom edges of the print, and uses these gate signals to switch the output of the encoder 30 and the black level or white level signal generated by the clamp circuit 31. By switching at 32, the print head position is displayed as a white line or a black line on the monitor, and the print head position can be confirmed.

As described above, according to this embodiment, vertical two-screen printing can be realized.

In this embodiment, the print position offset is performed using the read address, but the same effect can be obtained even if the offset is performed using the write address circuit 7 during writing.

Next, the horizontal multi-screen printing shown in FIG. 3(ii) will be explained with reference to FIG.

Horizontal multi-screen printing is achieved by re-inputting the initial value of the sampling position counter 44 in the sampling clock generation circuit 4 during printing to return the sampling position to the position at the start of printing.

First, at the start of printing, an offset value is loaded from the offset circuit 35 to the sampling position counter 44 in the sampling clock generation circuit 4, and the clock generation circuit 45 in the sampling clock generation circuit 4 uses the sampling clock at the position corresponding to the offset value. generate b. Thereafter, each time one line is printed, the value of the sampling position counter 44 is incremented by one, and the generation position of the sampling clock b is shifted by one pixel.

At this time, the print line counter 36 receives a print start signal for one color and a print start signal for one line from the system controller 29, and counts the number of print lines. When the count reaches a predetermined number, the decode circuit 37 ,
Generate the initial value load signal again as shown in FIG. 8(i),
The signal is input to the sampling clock generation circuit 4. Figure 8 (
In i), the number of print lines per screen is 512. When the initial value load signal is input, the sampling clock generation circuit 4 loads the offset value again, aligns the generation position of the generated sampling clock b with the sampling start point as shown in FIG. 8(ii), and thereafter operates in the same manner as described above. Then, the generation position of sampling clock b is shifted one pixel at a time.

Through the above operations, horizontal multi-screen printing is realized.

Furthermore, if different offset values are loaded at initial value load timing A and initial value load timing B shown in FIG. 8 (1), multi-screen printing of two images with different cutout portions in the horizontal direction of the screen can be obtained. It will be done.

Also, the sampling clock b is input to the switching signal circuit 40, and the output of the switching signal circuit 40 causes the encoder 30 to
By switching the output of the output and the black level or white level signal generated by the clamp circuit 31 using the switch 32, the print start position can be shown as a white line or a black line on the monitor, and the print start position can be confirmed. can.

Next, four-screen multi-printing (FIG. 3 (iii)) will be explained.

Four-screen multi-printing is a method of cutting out arbitrary positions on the screen and performing multi-printing of the same four screens by combining the techniques of vertical multi-screen printing and horizontal multi-screen printing described above.

FIG. 9 is a block diagram showing a second embodiment of the present invention.

In this embodiment, multi-screen printing in the horizontal direction is performed in exactly the same manner as in the embodiment shown in FIG. 2, and multi-screen printing in the vertical direction is performed by controlling the read address of the line memory 6.

The configuration of this embodiment differs from the configuration of the embodiment shown in FIG. 2 by removing the switch 43 and placing the read address circuit 8 in the first
The configuration is as shown in FIG. In FIG. 9, parts having the same reference numerals as those in FIG. 2 have the same functions as those in FIG. Additionally, 62 is a signal line.

The operation during horizontal multi-screen printing is the same as that of the embodiment shown in FIG. 2, so its explanation will be omitted.

Read address circuit 8 during vertical multi-screen printing
The operation will be explained using FIG.

In FIG. 10, parts having the same reference numerals as those in FIG. 6 have the same functions as those in FIG. Additionally, 61 is a switch for switching between normal printing and vertical multi-screen printing.

During vertical multi-screen printing, a switching signal between normal printing and multi-screen printing is manually input from the system controller 29, and this signal switches the switch 61 to fix the most significant bit (MSB) of the input to the adder 52 at a low level. . Then, the adder 52 adds an offset value to the value input to the adder 52, and the resulting value is given as the read address of the line memory 6.

With the above operation, the read address given to the line memory 6 during vertical multi-screen printing is the 11th
As shown in the figure, n,,n,+l.

ni+2. ni+3. ni+4. ......, n*
+255, and the same address value is given twice in succession.

As explained above, according to this embodiment, the line memory 6
By controlling the readout address, vertical multi-screen printing can be obtained.

FIG. 12 is a block diagram showing a third embodiment of the present invention.

In this embodiment, horizontal multi-screen printing is achieved by the same operation as in the embodiment shown in FIG. It is something that will be realized.

The configuration of this embodiment is such that the switch 43 is removed from the configuration of the embodiment shown in FIG. 2, and the halftone control circuit 9 is configured as shown in FIG. 13.

In FIG. 12, parts having the same reference numerals as those in FIG. 2 have the same functions as those in FIG. Others, 701-706
are input/output signal lines of the halftone control circuit 9.

The operation during horizontal multi-screen printing is the same as that of the embodiment shown in FIG. 2, so its explanation will be omitted.

The operation of the halftone control circuit 9 during vertical multi-screen printing will be explained using FIG. 13.

In FIG. 13, parts having the same reference numerals as those in FIG. 2 have the same functions as those in FIG. In addition, 707 is a changeover switch for switching between using the read clock CKA or CKB as the clock for the latch 14.

During normal printing, the halftone control circuit 9 compares the output of the line memory 6 and the output of the gradation counter 11 in magnitude with the comparator 10, as explained in the embodiment of FIG.
-Generate OFF data, and use the 0N-OFF data as
The data is latched into the latch 13 and the latch 14 using the read clocks CKA and CKB, respectively.

During vertical multi-screen printing, the switch 707 is switched by a normal print/multi-screen print switching signal from the system controller 29, and the latch 13 and latch 1
A read clock CKA is input to both of the clocks 4 and 4 as a clock. As a result, the same data is latched to the latch 13 and the latch 14, and the same data is input to the two manual inputs of the thermal head 15.

As described above, according to this embodiment, longitudinal multi-duplex printing can be realized by controlling the latch clock of the halftone control circuit 9.

FIG. 14 is a block diagram showing a fourth embodiment of the present invention.

In this embodiment, a line memory using a dual port memory is used as the line memory to perform vertical multi-screen printing.

First, the configuration of this embodiment will be explained.

The configuration of this embodiment is such that, in the configuration of the embodiment shown in FIG. 2, the line memory 6 and halftone control circuit 9 are replaced by a line memory 1101 (consisting of an RA section and a SAM section) using a dual port memory. - Replace the write address circuit 7 and read address circuit 8 that control the address of the line memory with the OR circuits 102 and 103, and replace the write address circuit 7 and read address circuit 8 with the write vertical address circuit 106 and the write horizontal address circuit 1.
04 and read horizontal address circuit 105. In FIG. 14, parts having the same reference numerals as those in FIG. 2 have the same functions as those in FIG. Others, 1
21 to 126 are input/output signal lines of the write vertical address circuit 106.

First, referring to FIG. 14, the operation during normal printing will be explained.

The write vertical address circuit 106 advances the vertical address in accordance with the horizontal synchronization signal H.

The write horizontal address circuit 104 supplies the data A/D converted by the A/D converter 5 to the line memory 101 as a horizontal address. The line memory 101 writes “1” to the address designated by the write vertical address circuit 106 and the write horizontal address circuit 104.

FIG. 15 is an explanatory diagram schematically showing data writing in the line memory 101.

When one line of data is written to the line memory 101, the read horizontal address circuit 105 first specifies "0" as the horizontal address, and the line memory 101 writes 512 pieces of data at the horizontal address "0" to the RAM. from the unit to the SAM unit. The data for one line and one gradation transferred to the SAM section is serially read out by the clock HCK from the energization control circuit 28, and
Input on 02.103. In addition, in the shift registers 16 and 17 of the thermal head 15, data of '1' is initially written in all registers, and the clock HC
K is read out sequentially.

The Ex-OR circuits 102 and 103 are connected to the shift register 16
．． 17 and the output of the line memory 101 to generate ON-OFF data, which is sent to the heat sensitive RAD 15. The thermal head 15 is
When the N-0FF data is input, electricity is applied for one gradation based on the N-0FF data. Thereafter, the read horizontal address circuit 105 reads the horizontal addresses one by one as "63".
The number of gradations is increased to J (here, printing is performed at 64 gradations), and one line is printed.

After printing for one line is completed, a full color print for one screen is obtained by the same operation as in the embodiment shown in FIG.

Next, multi-screen printing will be explained.

In this example, horizontal multi-screen printing is performed in the second
As in the embodiment shown in the figure, this is achieved by returning the sampling position to the start of printing after printing to the center.

On the other hand, in this embodiment, vertical multi-screen printing is realized by the system controller 29 switching the switch 43 to input the same data to multiple inputs of the thermal head 15, and by giving an offset to the write vertical address. Ru.

Now, the operation of the write vertical address circuit 106 for giving an offset to the write vertical address will be explained using FIGS. 16 and 17.

FIG. 16 shows the write vertical address circuit 10 of FIG.
FIG. 6 is a block diagram showing the configuration of No. 6;

In FIG. 16, 111 is a field discrimination circuit for discriminating fields, 112 is a counter, 113 is a decoding circuit, 114 is a counter, 115 is a timer, and 116 is N
An AND circuit, 117 is an adder.

The counter 112 counts the horizontal synchronization signal I] using the vertical synchronization signal ■ as a reset signal. The decoding circuit 113 decodes this count value and generates a VBLK signal indicating the write area as shown in FIG. 17.

Using this VBLK signal as a reset signal, the counter 11
4 counts the horizontal synchronizing signal H.

The adder 117 sets the 0th bit to the 7th bit of the output of the counter 114 as the 1st bit to the 8th bit, and sets the output of the field discrimination circuit 111 as the 0th bit from the offset circuit 41. The offset value is added to generate a write vertical address as shown in FIG. 17 (in FIG. 17, the offset value is n).

The write control signal WE is generated by delaying the sampling clock b from the sampling clock generation circuit 4 by a timer 115 and then gated by the VBLK signal.

In this way, by offsetting the write vertical address of the line memory 101, the print image is shifted in advance at the time of writing, and the switch 43
It is possible to obtain multi-screen printing by switching between

FIG. 18 is a block diagram showing a fifth embodiment of the present invention.

In this embodiment, horizontal multi-screen printing is realized by exactly the same operation as in the embodiment shown in FIG. 14, and vertical multi-screen printing is performed by writing two pieces of the same data into the line memory 101 by controlling the fortune-telling vertical address. This is achieved by

In Figure 18, the same numbers as in Figure 14 are numbered 14.
It has the same function as the one shown in the figure. Additionally, 202 is a write vertical address circuit, which has a configuration as shown in FIG. Further, 205 is a signal line.

The operation during horizontal multi-screen printing is the same as that in the embodiment shown in FIG. 14, so its explanation will be omitted.

Now, the operation during vertical multi-screen printing will be explained with reference to FIGS. 19 and 20, focusing on the operation of the write vertical address circuit 202.

In Figure 19, the same numbers as in Figure 16 are numbered 16.
It has the same function as the one shown in the figure. In addition, 210 is a selector, 211 and 212 are timers, 213 is a NAND circuit, 214 is a timer, 215 is a latch, 216 is a coincidence detection circuit, 217 is a counter, 218 is a decoding circuit, 2
19 is an OR circuit, and 220 is a selector.

One input of the selector 210 is the same as the write vertical address in the embodiment of FIG. 14, that is, the output of the adder 117. Further, as shown in FIG. 20, the other input is manually entered with a write vertical address that allows the same data to be written twice. Then, the selector 210 switches the write vertical address between normal printing and multi-screen printing in response to a normal print/multi-screen print switching signal from the system controller 29.

A write vertical address during vertical multi-screen printing, that is, a write vertical address as shown in FIG. 20 is generated as follows.

- The number output circuit 216 detects coincidence between the output of the counter 114 and the output from the offset circuit 41. Using this coincidence signal as a reset signal, the counter 217 counts the horizontal synchronization signal H.

Further, the latch 215 operates using a signal obtained by delaying the sampling clock b by a predetermined time by the timer 214 as a clock. Therefore, for the write vertical address, the 1st to 7th bits of the output of the counter 217 are taken as the 1st bit to the 7th bit, the output of the field discrimination circuit 111 is taken as the 0th bit, and is also generated using the Q output of the latch 215, which is switched after a delay of the timer 214, as its 8th bit.

Next, the write control signal WE during vertical multi-screen printing will be explained.

During vertical multi-screen printing, write control signal WE
needs to go to Low level twice during one data period in response to changes in the write vertical address. Therefore, in synchronization with sampling clock b, timer 21
1 and timer 212, two types of pulses are generated. These two types of pulses are connected to the NAND circuit 213.
D and write control signal WE as shown in FIG.
to occur.

The above write operation allows the same data to be written into the line memory 101 twice at different addresses.

As described above, according to this embodiment, vertical multi-screen printing can be performed by controlling the write vertical address using a line memory using a dual port memory as the line memory.

FIG. 21 is a block diagram showing a sixth embodiment of the present invention.

In FIG. 21, components having the same reference numerals as those in FIG. 2 have the same functions as those in FIG. Additionally, 401 is a switch for switching input to the thermal head 15, and 402 is a decoding circuit for decoding a read address.

In this embodiment, a gate is applied to the input of the thermal head 15 to add a white frame to the boundary of each image during multi-screen printing.

During vertical multi-screen printing, the output of the read address circuit 8 is decoded by the decoding circuit 402, and a white frame can be inserted at the border by switching the switch 401 using the decoded output.

Further, during horizontal multi-screen printing, the output of the print line counter 36 is decoded by the decoding circuit 37, and a white frame can be inserted at the border by switching the switch 401 using the output.

As described above, according to this embodiment, a white frame can be provided at the boundary of each image during multi-screen printing.

〔Effect of the invention〕

As described above, according to the present invention, by controlling the sampling timing of the video signal, controlling the address of the line memory, controlling the input to the thermal head, etc., a specific part of the input image can be cut out, and the same It can be made into a screen and printed on photographic paper.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining the present invention in detail, FIG. 2 is a block diagram showing the first embodiment of the present invention, and FIG. 3 is an explanatory diagram for explaining multi-screen printing according to the present invention. , Fig. 4 is an explanatory diagram showing the difference in print obtained when the read address of the line memory in Fig. 2 is not offset and when it is offset in a vertical multi-screen print, and Fig. 5 is an explanatory diagram showing the difference in print obtained when the read address of the line memory in Fig. 2 is offset. FIG. 6 is a block diagram showing the configuration of the read address circuit of FIG. 2, and FIG. 7 is an explanatory diagram showing the contents stored in the line memory of the embodiment and the shift register in the thermal head. FIG. 8 is a timing chart showing the timing of main signals during vertical multi-screen printing, FIG. 8 is a timing chart showing the timing of main signals during horizontal multi-screen printing in the embodiment shown in FIG. A block diagram showing the second embodiment of the invention, FIG. 10 is a block diagram showing the configuration of the read address circuit in FIG. 9, and FIG. 11 shows the read address of the line memory in the ninth embodiment when normally printed. 12 is a block diagram showing a third embodiment of the present invention, and FIG. 13 shows the configuration of the halftone control circuit in FIG. 12. 14 is a block diagram showing a fourth embodiment of the present invention, FIG. 15 is an explanatory diagram for explaining the operation of the line memory in FIG. 14, and FIG. 16 is a write vertical diagram in FIG. 14. Block diagram showing the configuration of the address circuit, 1st
7 is a timing chart showing the timing of main signals during vertical multi-screen printing in the embodiment shown in FIG. 14, FIG. 18 is a block diagram showing the fifth embodiment of the present invention, and FIG. FIG. 20 is a block diagram showing the configuration of the writing vertical address circuit shown in FIG.
FIG. 2 is a block diagram showing an embodiment of the invention. Explanation of symbols 4...Sampling clock generation circuit, 5...A/
D converter, 6... line memory, 7... write address circuit, 8... read address circuit, 9...
Halftone control circuit, 15... Thermal head, 29... System controller, 35.41... Offset circuit, 37...
Decode circuit, 36...Print line counter,
43...Switch. Figure Figure Figure Figure RAM Ichigi SAM Iku

Claims (1)

[Scope of Claims] 1. Analog/digital conversion means for sequentially sampling an analog video signal input as a still image in units of one vertical line or one horizontal line of the still image and outputting the sample as digital image data; A line memory that stores one vertical line or one horizontal line of image data output from the analog/digital conversion means, and control data generation means that generates control data from the image data read from the line memory. and a thermal head that inputs the generated control data and prints the still image on photographic paper one vertical line or one horizontal line at a time by causing a plurality of heating elements arranged in a line to generate heat based on the control data. In the signal processing circuit of the video printer, a count is performed each time the thermal head prints one vertical line or one horizontal line, and based on the counted value, the analog/digital conversion means determines the vertical line to be sampled in the still image. The sampling position determining means determines the position of one line or one horizontal line, and the first offset means outputs a desired offset value.
Load an offset value from the first offset means, start counting from the offset value, and when the thermal head prints the desired number of lines, load the offset value from the first offset means again, and start counting from the offset value. A signal processing circuit for a video printer, characterized in that it starts counting. 2. The signal processing circuit according to claim 1, wherein read address means outputs a read address of the line memory, second offset means outputs a desired offset value, and control data generated by the control data generation means. branching means for branching the control data into a plurality of parts, and the read address means starts counting from the offset value input from the second offset means, and outputs the counted value as the read address. At the same time, the thermal head inputs a plurality of identical control data obtained by branching by the branching means, and causes the plurality of heating elements arranged in a row to generate heat based on the control data. A video printer signal processing circuit characterized by: 3. The signal processing circuit according to claim 1, further comprising read address means for outputting a read address of the line memory and second offset means for outputting a desired offset value, the read address means comprising: counting means that starts counting from the offset value input from the second offset means, and starts counting again from the offset value when the counted value reaches a desired value;
Alternatively, the counting means starts counting from the offset value inputted from the second offset means and continuously counts the same value a plurality of times, and the values counted by the counting means are read out. A signal processing circuit for a video printer, characterized in that the signal processing circuit outputs the signal as an address. 4. The signal processing circuit according to claim 1, wherein write address means outputs a write address of the line memory, second offset means outputs a desired offset value, and a signal generated by the control data generation means. branching means for branching the control data into a plurality of parts, and the write address means starts counting from the offset value input from the second offset means, and outputs the counted value as the write address. At the same time, the thermal head inputs a plurality of identical control data obtained by branching by the branching means, and causes the plurality of heating elements arranged in a row to generate heat based on the control data. A video printer signal processing circuit characterized by: 5. The signal processing circuit according to claim 1, further comprising a write address means for outputting a write address of the line memory and a second offset means for outputting a desired offset value, the write address means comprising: Counting is started from the offset value input from the second offset means, the counted value is set as the first value, the value obtained by adding a desired number to the counted value is set as the second value, and at least the above-mentioned offset value is set as the second value. The value 1 and the second value are outputted as the write address in a time-sharing manner, and the line memory outputs the first value and the second value output as the write address, Of the image data output from the analog/digital conversion means,
A signal processing circuit for a video printer, characterized in that the same data is stored.