JPH07162055A - Hall element - Google Patents
Hall elementInfo
- Publication number
- JPH07162055A JPH07162055A JP5302002A JP30200293A JPH07162055A JP H07162055 A JPH07162055 A JP H07162055A JP 5302002 A JP5302002 A JP 5302002A JP 30200293 A JP30200293 A JP 30200293A JP H07162055 A JPH07162055 A JP H07162055A
- Authority
- JP
- Japan
- Prior art keywords
- region
- holes
- hole
- heterojunction
- hall element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229920005989 resin Polymers 0.000 abstract description 12
- 239000011347 resin Substances 0.000 abstract description 12
- 239000013078 crystal Substances 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 230000001747 exhibiting effect Effects 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- -1 oxygen ions Chemical class 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 14
- 230000035882 stress Effects 0.000 description 9
- 230000035945 sensitivity Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Hall/Mr Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】III−Ｖ族化合物半導体ホール素
子に関する。BACKGROUND OF THE INVENTION The present invention relates to a III-V compound semiconductor Hall device.
【０００２】[0002]
【従来の技術】磁電変換素子の一つとしてホール素子が
知られている。ホール素子は一種の磁気センサーであ
り、回転検出センサーや電流センサー等として利用され
ている。最近では、ホール素子の高性能化の要望に対応
してＧａＩｎＡｓとＩｎＰとのヘテロ接合からなる高感
度ホール素子が開発されている（奥山 忍他、１９９２
年秋季第５３回応用物理学会学術講演会予稿集Ｎｏ．３
（応用物理学会発行）、講演番号１６ａ−ＳＺＣ−１
６、１０７８頁）。このＧａＩｎＡｓヘテロ接合ホール
素子は温度特性も良く、感度特性に優れる。2. Description of the Related Art A Hall element is known as one of magnetoelectric conversion elements. The Hall element is a kind of magnetic sensor and is used as a rotation detection sensor, a current sensor, or the like. Recently, a high-sensitivity Hall element composed of a heterojunction of GaInAs and InP has been developed to meet the demand for higher performance of the Hall element (Okuyama Shinobu, 1992).
Of the 53rd Autumn Meeting of the Japan Society of Applied Physics Three
(Published by Japan Society of Applied Physics), Lecture No. 16a-SZC-1
6, pages 1078). This GaInAs heterojunction Hall element has good temperature characteristics and excellent sensitivity characteristics.
【０００３】ＧａＩｎＡｓ／ＩｎＰヘテロ接合ホール素
子も従来のＧａＡｓホール素子等と同じく、素子機能部
以外の領域は平坦となっている。素子機能部とは感磁層
からなる感磁領域及び電極形成領域を言う。感磁部は従
来から感磁層が互いに直交したホールクロスからなって
いる。従来からの素子構造を図４に示す。The GaInAs / InP heterojunction Hall element is also flat in the region other than the element functional portion, like the conventional GaAs Hall element and the like. The element functional section refers to a magnetic sensitive area and an electrode forming area made of a magnetic sensitive layer. The magnetically sensitive portion has conventionally been formed of a hole cross in which the magnetically sensitive layers are orthogonal to each other. A conventional element structure is shown in FIG.
【０００４】従来からチップ化されたホール素子はフレ
ーム上にマウントされ、封止用のエポキシ樹脂等で外囲
しモールド品とする。チップの平坦表面は樹脂により被
覆される。一般に封止用樹脂とホール素子の半導体材料
との熱膨張率は異なる。外囲工程では樹脂は加熱され、
成型される。成型時には、樹脂は伸縮し、それに伴う応
力がホール素子チップに掛かる。Conventionally, a Hall element which has been made into a chip is mounted on a frame and is surrounded by an epoxy resin or the like for sealing to form a molded product. The flat surface of the chip is coated with resin. Generally, the coefficient of thermal expansion of the sealing resin and the semiconductor material of the Hall element are different. The resin is heated in the surrounding process,
Molded. During molding, the resin expands and contracts, and the resulting stress is applied to the Hall element chip.
【０００５】接合界面の物性が素子特性を左右するヘテ
ロ接合ホール素子では、樹脂で素子を外囲する際に特性
に変化を来すことが知られている。この特性変化は不平
衡電圧（片岡 照栄著「磁電変換素子」（昭和４６年２
月１日４版 日本工業新聞社発行、６１頁）の増大や感
度の劣化となって現れる。これは、樹脂の変形に伴う応
力がヘテロ接合界面に波及し、ヘテロ界面を乱すからで
ある。ヘテロ界面が外的要因に依って無秩序化されると
高い電子移動度などが発現されない。It is known that in a heterojunction Hall element in which the physical properties of the junction interface influence the element characteristics, the characteristics change when the element is surrounded by a resin. This change in characteristics is caused by an unbalanced voltage ("Terei Kataoka," Magnetic-electric conversion element "(1969, 2
1st edition, 4th edition, published by Nihon Kogyo Shimbun, page 61) This is because the stress accompanying the deformation of the resin spreads to the heterojunction interface and disturbs the heterointerface. If the hetero interface is disordered due to external factors, high electron mobility will not be exhibited.
【０００６】樹脂の変形応力を緩和する一つの方法は、
樹脂が被覆される領域の表面積を増大させることであ
る。表面積が増えると単位面積に印加される応力が減少
する従来の様な表面が平坦である素子では、外囲成型工
程での応力を緩和するに充分でない。ヘテロ接合界面に
水平で平坦な表面は界面に垂直に掛かる変形応力を分散
できない。応力を分散できる表面加工等を施せば良い
が、従来から実施されていない。従って、ヘテロ接合特
性を充分に発揮できる高性能のヘテロ接合ホール素子を
安定して得るのは困難であった。One method for relaxing the deformation stress of the resin is
Increasing the surface area of the area covered by the resin. As the surface area increases, the stress applied to the unit area decreases. In the conventional device having a flat surface, it is not enough to relax the stress in the envelope molding process. A flat surface horizontal to the heterojunction interface cannot disperse the deformation stress applied vertically to the interface. A surface treatment or the like that can disperse the stress may be applied, but it has not been performed conventionally. Therefore, it has been difficult to stably obtain a high-performance heterojunction Hall element capable of sufficiently exhibiting the heterojunction characteristics.
【０００７】[0007]
【発明が解決しようとする課題】外囲樹脂の熱変形応力
に因るヘテロ接合界面の破壊を回避する。The destruction of the heterojunction interface due to the thermal deformation stress of the surrounding resin is avoided.
【０００８】[0008]
【課題を解決するための手段】ＧａＩｎＡｓ／ＩｎＰ若
しくはＧａＩｎＡｓ／ＡｌＩｎＡｓヘテロ接合ホール素
子に於いて、感磁部、電極部からなる素子機能部以外の
領域に孔を設ける。孔は基板を貫通させても良い。これ
により、母体材料表面の表面積を増加し、ヘテロ接合界
面に掛かる応力を分散させる。In a GaInAs / InP or GaInAs / AlInAs heterojunction Hall element, a hole is provided in a region other than the element function section including a magnetic sensitive section and an electrode section. The holes may penetrate the substrate. This increases the surface area of the surface of the base material and disperses the stress applied to the heterojunction interface.
【０００９】ＧａＩｎＡｓ／ＩｎＰ若しくはＧａＩｎＡ
ｓ／ＡｌＩｎＡｓヘテロ接合は半導体単結晶基板上に形
成する。格子の整合性からＩｎＰ単結晶を基板とするの
が良い。積層の順序には制限はないが、通常はＧａＩｎ
Ａｓ感磁層の電子移動度を向上させるためにＩｎＰやＡ
ｌＩｎＡｓを緩衝層として先ず堆積するのが一般的であ
る。GaInAs / InP or GaInA
The s / AlInAs heterojunction is formed on a semiconductor single crystal substrate. InP single crystal is preferably used as the substrate because of the lattice matching. There is no limitation on the stacking order, but normally GaIn
InP and A in order to improve the electron mobility of the As magnetosensitive layer.
It is common to first deposit lInAs as a buffer layer.
【００１０】ヘテロ接合層の成長方法には制限はない。
分子線エピタキシャル成長（ＭＢＥ）法や有機金属熱分
解気相成長（ＭＯＣＶＤ）法が適用できる。ＭＯＣＶＤ
とＭＢＥを複合させたＭＯ・ＭＢＥ法なども適用でき
る。また、層毎に成長方法を異にしても支障は無い。There is no limitation on the method of growing the heterojunction layer.
A molecular beam epitaxial growth (MBE) method or a metal organic pyrolysis vapor deposition (MOCVD) method can be applied. MOCVD
The MO / MBE method that combines MBE and MBE can also be applied. Further, there is no problem even if the growth method is different for each layer.
【００１１】感磁部と電極部からなる素子機能部領域以
外の領域に孔若しくは貫通孔を設ける。一般的なホール
素子のチップサイズは３００μｍ〜４００μｍ□程度で
ある。また、このチップサイズでの素子機能部以外の領
域の面積を考慮すると、孔の開口径は最大５０μｍ程度
である。孔は素子機能部以外の領域にホールクロスの中
央部を中心に対象に配置すると良い。対象の位置に複数
個設けると効果的である。しかも、直交するホールクロ
スと４５度の位置に設けると良い。好ましい孔の配置の
一例を図５に示す。A hole or a through hole is provided in a region other than the element function region including the magnetic sensing portion and the electrode portion. The chip size of a general Hall element is about 300 μm to 400 μm □. Further, considering the area of the region other than the element function part in this chip size, the maximum opening diameter of the holes is about 50 μm. It is preferable that the holes are arranged in areas other than the element function portion with the center of the hole cross as the center. It is effective to provide a plurality at the target position. Moreover, it is preferable to provide it at a position of 45 degrees with the orthogonal hole cross. An example of a preferable hole arrangement is shown in FIG.
【００１２】孔はエッチングにより形成する。孔を設け
る位置を選択的にエッチングする様に公知のフォトリソ
グラフィー技術によりパターニングする。無機酸でエッ
チングすれば孔は形成される。ドライエッチング法に依
っても構わない。エッチング時間を調節すれば孔の深さ
を調整できる。孔はヘテロ接合層の表面から裏面へ貫通
させても良い。エッチングにより感磁層が除去されない
様にする。感磁層の不規則な除去は不平衡電圧の増大を
もたらすからである。不平衡電圧とは無磁界下で発生す
る電圧である（例えば片岡 照栄著「磁電変換素子」
（昭和４６年第４版発行：日刊工業新聞社）、６１
頁）。ホール出力電圧に占める不平衡電圧の割合が大き
くなると不平衡率は増大し、素子特性の向上が果たせな
い。The holes are formed by etching. Patterning is performed by a known photolithography technique so that the positions where the holes are provided are selectively etched. The holes are formed by etching with an inorganic acid. A dry etching method may be used. The depth of the holes can be adjusted by adjusting the etching time. The holes may penetrate from the front surface to the back surface of the heterojunction layer. Prevent the magnetosensitive layer from being removed by etching. This is because the irregular removal of the magnetosensitive layer causes an increase in the unbalanced voltage. An unbalanced voltage is a voltage generated in the absence of a magnetic field (for example, Teruei Kataoka "Magnetic-electric conversion element").
(Published in 1972, 4th edition: Nikkan Kogyo Shimbun), 61
page). When the proportion of the unbalanced voltage in the Hall output voltage increases, the unbalanced ratio increases, and the element characteristics cannot be improved.
【００１３】孔を設けたＧａＩｎＡｓ／ＩｎＰヘテロ接
合ホール素子の電気特性を評価した。素子の外囲前後で
積感度、不平衡率共に変化を生じなかった。これは孔が
封止用樹脂の伸縮変形に伴う熱応力を緩和し、ヘテロ界
面の乱雑化を回避できたためである。The electrical characteristics of the GaInAs / InP heterojunction Hall element having holes were evaluated. The product sensitivity and the unbalance ratio did not change before and after the surrounding of the device. This is because the holes alleviated the thermal stress caused by the expansion and contraction of the sealing resin, and the disorder of the hetero interface could be avoided.
【００１４】[0014]
【作用】外囲樹脂の熱変形に伴って誘引される積感度、
不平衡率の劣化を回避する作用を有する。[Function] Product sensitivity induced by thermal deformation of the surrounding resin,
It has the effect of avoiding deterioration of the unbalance rate.
【００１５】[0015]
【実施例】以下、本発明をＧａＩｎＡｓ／ＩｎＰヘテロ
接合ホール素子の実施例を基に具体的に説明する。図１
はＧａＩｎＡｓ／ＩｎＰヘテロ接合ホール素子の平面模
式図である。図２及び図３は図１の破線Ａ−Ａ’並びに
Ｂ−Ｂ’に沿う断面模式図である。基板にはＦｅドープ
の半絶縁性ＩｎＰ単結晶（１０１）を使用した。基板結
晶（１０１）の比抵抗は１×１０7 Ω・ｃｍであった。
厚さは約３５０μｍであった。EXAMPLES The present invention will be specifically described below based on examples of GaInAs / InP heterojunction Hall devices. Figure 1
FIG. 3 is a schematic plan view of a GaInAs / InP heterojunction Hall element. 2 and 3 are schematic cross-sectional views taken along broken lines AA 'and BB' of FIG. A Fe-doped semi-insulating InP single crystal (101) was used for the substrate. The specific resistance of the substrate crystal (101) was 1 × 10 7 Ω · cm.
The thickness was about 350 μm.
【００１６】基板（１０１）上にはアンドープのＩｎＰ
緩衝層（１０２）を堆積した。膜厚は約２００ｎｍとし
た。緩衝層（１０２）は温度６１０℃で成長させた。緩
衝層（１０２）上に厚さが約４００ｎｍのｎ形Ｇａ0.47
Ｉｎ0.53Ａｓ感磁層（１０３）をヘテロ接合させた。両
層は常圧ＭＯＶＰＥ法で成長させた。感磁層（１０３）
も６１０℃で成長させた。緩衝層（１０２）、感磁層
（１０３）のキャリア濃度は各々、２×１０15ｃｍ-3、
２×１０16ｃｍ-3であった。感磁層（１０３）のキャリ
ア濃度は硫黄（Ｓ）のドーピングにより得た。ｎ形のド
ーパントとしては、セレン（Ｓｅ）やＳｉなどが使用で
きる。Undoped InP is formed on the substrate (101).
A buffer layer (102) was deposited. The film thickness was about 200 nm. The buffer layer (102) was grown at a temperature of 610 ° C. An n-type Ga 0.47 having a thickness of about 400 nm is formed on the buffer layer (102).
The In 0.53 As magnetosensitive layer (103) was heterojunctioned. Both layers were grown by atmospheric pressure MOVPE method. Magnetosensitive layer (103)
Was also grown at 610 ° C. The carrier concentration of the buffer layer (102) and the magnetosensitive layer (103) is 2 × 10 15 cm −3 ,
It was 2 × 10 16 cm −3 . The carrier concentration of the magnetosensitive layer (103) was obtained by doping with sulfur (S). Selenium (Se) or Si can be used as the n-type dopant.
【００１７】公知のフォトリソグラフィー技術を駆使し
て先ず、感磁機能を発揮する感磁部と電極部に相当する
領域をパターニングした。この領域に限りフォトレジス
ト材を残存させた。次に全面に質量数が３２である酸素
イオンを加速電圧２００ＫＶで３×１０13ｃｍ-2のドー
ズ量で注入した。これにより素子機能領域を絶縁化した
（図１〜３に番号（１０４）で示す。）。First, by making full use of a known photolithography technique, a region corresponding to a magnetic sensitive portion exhibiting a magnetic sensitive function and an electrode portion was patterned. The photoresist material was left only in this region. Next, oxygen ions having a mass number of 32 were implanted over the entire surface at an acceleration voltage of 200 KV and a dose of 3 × 10 13 cm -2 . As a result, the element functional region was insulated (shown by number (104) in FIGS. 1 to 3).
【００１８】フォトレジスト材で表面を再び被覆した。
公知技術を利用して孔を形成する領域をパターニングし
た。湿式エッチングにより開口直径が３０μｍの孔（１
０５）を形成した。孔（１０５）は感磁層（１０３）表
面から基板（１０１）の裏面へ貫通している。孔（１０
５）はホールクロスを［０１１］結晶方位に形成したた
め、［１００］方向に在る素子機能部以外の領域に合計
４個設けた。孔（１０５）はホールクロスの中央を中心
に対象に配置されている。また、孔（１０５）はホール
クロスの中心線から４５゜の方向に形成した。The surface was recoated with a photoresist material.
The area in which the holes are to be formed is patterned by using a known technique. Wet etching has a hole (1
05) was formed. The hole (105) penetrates from the surface of the magnetic sensing layer (103) to the back surface of the substrate (101). Hole (10
In 5), since hole crossings were formed in the [011] crystal orientation, a total of four hole crossings were provided in the region other than the element functional portion in the [100] direction. The holes (105) are arranged symmetrically around the center of the hole cross. The holes (105) were formed in the direction of 45 ° from the center line of the hole cross.
【００１９】ダイシングライン（１０６）を利用しスク
ライブし、チップにした。チップは一般的な外囲用エポ
キシ樹脂で外囲した。外囲プロセスの最高の温度は１９
０℃であった。A dicing line (106) was used to scribe and form chips. The chip was surrounded by a general surrounding epoxy resin. The maximum temperature of the surrounding process is 19
It was 0 ° C.
【００２０】外囲後、電気特性を評価した。表１に結果
を掲げる。本発明のホール素子では、積感度はモールド
の前後で約７７０Ｖ・Ａ／Ｔと殆ど変化が認められなか
った。従来例ではモールド後、積感度は６０１Ｖ・Ａ／
Ｔと約２２％低下した。従来例とは孔を設けてないＧａ
ＩｎＡｓ／ＩｎＰヘテロ接合ホール素子を言う。また、
不平衡率は本発明の場合、モルード前後に於いて±４％
程度とほぼ一定であった。従来例のそれは±１１％と劣
化した。After the surrounding, the electrical characteristics were evaluated. The results are shown in Table 1. In the Hall element of the present invention, the product sensitivity before and after molding was about 770 V · A / T, which was hardly changed. In the conventional example, the product sensitivity after molding is 601 V · A /
It was about 22% lower than T. Ga with no holes compared to the conventional example
This is an InAs / InP heterojunction Hall element. Also,
In the case of the present invention, the unbalance rate is ± 4% before and after molding.
It was almost constant with the degree. That of the conventional example deteriorated to ± 11%.
【００２１】[0021]
【表１】 [Table 1]
【００２２】[0022]
【発明の効果】感度、不平衡率の悪化を抑制する効果が
ある。The present invention has an effect of suppressing deterioration of sensitivity and unbalance ratio.
【図１】本発明のＧａＩｎＡｓ／ＩｎＰヘテロ接合ホー
ル素子の平面模式図である。FIG. 1 is a schematic plan view of a GaInAs / InP heterojunction Hall element of the present invention.
【図２】図１の破線Ａ−Ａ’に沿う断面模式図である。FIG. 2 is a schematic cross-sectional view taken along the broken line A-A ′ in FIG.
【図３】図１の破線Ｂ−Ｂ’に沿う断面模式図である。FIG. 3 is a schematic cross-sectional view taken along the broken line B-B ′ of FIG.
【図４】従来のヘテロ接合ホール素子の概略図である。FIG. 4 is a schematic view of a conventional heterojunction Hall element.
【図５】好ましい孔の配置を示す図である。FIG. 5 is a diagram showing a preferred hole arrangement.
（１） ホール素子 （１−１） 素子機能部 （１−２） 機能部以外の領域 （１−３） ホールクロスの中心 （１０１） ＩｎＰ単結晶基板 （１０２） ＩｎＰ緩衝層 （１０３） Ｇａ0.47Ｉｎ0.53Ａｓ感磁層 （１０４） イオン注入による絶縁化領域 （１０５） 孔 （１０６） ダイシングライン （１０７） オーミック入・出力電極 （１０８） ＳｉＯ2 絶縁膜 （１０９） ホールクロス(1) Hall element (1-1) Element functional part (1-2) Area other than functional part (1-3) Center of hole cross (101) InP single crystal substrate (102) InP buffer layer (103) Ga 0.47 In 0.53 As Magnetosensitive layer (104) Insulation region by ion implantation (105) Hole (106) Dicing line (107) Ohmic input / output electrode (108) SiO 2 insulating film (109) Hole cross
Claims (4)
Ｖ族化合物半導体ヘテロ接合を使用した感磁層を設けた
ホール素子において、該ヘテロ接合の素子機能部以外の
領域に孔を設けてなることを特徴とするホール素子。1. A III-V compound semiconductor substrate on a III-V compound semiconductor substrate.
A Hall element provided with a magneto-sensitive layer using a Group V compound semiconductor heterojunction, wherein holes are provided in a region other than the element function part of the heterojunction.
項１に記載のホール素子。2. The hall element according to claim 1, wherein the hole is a through hole.
らなることを特徴とする請求項１又は２に記載のホール
素子。3. The Hall element according to claim 1, wherein the heterojunction is made of GaInAs and InP.
ｓとからなることを特徴とする請求項１又は２に記載の
ホール素子。4. The heterojunction is GaInAs and AlInA.
3. The hall element according to claim 1, wherein the hall element is s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5302002A JPH07162055A (en) | 1993-12-01 | 1993-12-01 | Hall element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5302002A JPH07162055A (en) | 1993-12-01 | 1993-12-01 | Hall element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07162055A true JPH07162055A (en) | 1995-06-23 |
Family
ID=17903706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5302002A Pending JPH07162055A (en) | 1993-12-01 | 1993-12-01 | Hall element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07162055A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7391207B2 (en) | 2004-08-06 | 2008-06-24 | Denso Corporation | Rotation angle detector |
| US8704375B2 (en) | 2009-02-04 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier structures and methods for through substrate vias |
| CN106416065A (en) * | 2013-11-29 | 2017-02-15 | 于利奇研究中心有限公司 | Capacitively coupled hall effect gyrator |
-
1993
- 1993-12-01 JP JP5302002A patent/JPH07162055A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7391207B2 (en) | 2004-08-06 | 2008-06-24 | Denso Corporation | Rotation angle detector |
| US8704375B2 (en) | 2009-02-04 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier structures and methods for through substrate vias |
| CN106416065A (en) * | 2013-11-29 | 2017-02-15 | 于利奇研究中心有限公司 | Capacitively coupled hall effect gyrator |
| JP2017512387A (en) * | 2013-11-29 | 2017-05-18 | フォルシュングスツェントルム・ユーリッヒ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング | Capacitively coupled gyrator based on Hall effect |
| CN106416065B (en) * | 2013-11-29 | 2020-05-08 | 于利奇研究中心有限公司 | Hall effect based capacitively coupled gyrator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4978938A (en) | Magnetoresistor | |
| US4926154A (en) | Indium arsenide magnetoresistor | |
| JPS61107758A (en) | Gaas integrated circuit and manufacture thereof | |
| EP0092643B1 (en) | Ballistic conduction transistor | |
| JPH07162055A (en) | Hall element | |
| EP0375107A2 (en) | Improved magnetoresistors | |
| JP3399053B2 (en) | Heterojunction Hall element | |
| EP0472262B1 (en) | Heterojunction bipolar transistor | |
| JP3172958B2 (en) | Method for manufacturing compound semiconductor thin film | |
| US4922314A (en) | Hot charge-carrier transistors | |
| JP3456254B2 (en) | Epitaxial wafer for Hall element and method of manufacturing the same | |
| JP2768184B2 (en) | Manufacturing method of magnetoelectric conversion element | |
| JPH10125973A (en) | Gaas hall element and its manufacture | |
| JPH07193296A (en) | Heterojunction hall element | |
| JP2597774Y2 (en) | Hall element | |
| JPH03240281A (en) | Gaas hall element | |
| JP2597105Y2 (en) | Hall element | |
| JP3438294B2 (en) | Hall element | |
| JP3417014B2 (en) | Heterojunction Hall element | |
| JP3531206B2 (en) | Electrode structure of Hall element | |
| Kalingamudali et al. | Perimeter and bulk recombination currents in GaAs homojunction diodes and GaAsAlGaAs heterojunction bipolar transistors after surface processing | |
| JPH077194A (en) | Hall element | |
| JPS63102257A (en) | Manufacture of heterojunction bipolar semiconductor device | |
| JPH0779033A (en) | Magneto-electric transducer | |
| JP3399044B2 (en) | Hall element and method of manufacturing the same |