JPH07162012A - Static induction transistor and manufacture of static induction transistor - Google Patents

Abstract

PURPOSE:To prevent the generation of a gate contact failure and to increase the yield of the manufacture of a static induction transistor without using a complicated process by a method wherein a taper having a specified angle is provided on the sidewall of a groove encircling at least one part of a source region. CONSTITUTION:An N<-> epitaxial layer 2 is formed on an N<+> semiconductor substrate 1. A groove 4 is formed in the side of the surface of the layer 2 and the angle A of a sidewall 4a, on which a nitride film 5 is formed, of the groove 4 is set at 60 to 80 degrees. Moreover, oxide films 6 consisting of a silicon oxide are respectively formed under the bottom of the groove 4 and on the side of the surface of the film 2 and a gate diffusion window 7 is provided from the sidewall 4a of the groove 4 to the layer 2 and makes ohmic contact with a gate electrode 9. When the groove 4 is formed by dry etching, an etching is performed using SF6+CCl4 gas. Whereupon, as the etching is performed while a polymer is applied the sidewall 4a, a taper is formed on the sidewall 4a. As a result, a reduction in the yield of the manufacture of a static induction transistor, which is caused by a gate contact failure or the like, can be prevented from being generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static induction transistor and a method of manufacturing the static induction transistor, which are configured to reduce stray capacitance of a gate and improve high frequency characteristics.

[0002]

2. Description of the Related Art A conventional electrostatic induction transistor for electric power used in a high frequency band is manufactured in each step shown in FIGS.

That is, an "N-minus" epitaxial layer 2 is formed on an "N-plus" semiconductor substrate 1 made of silicon, and a resist 3 is patterned by photolithography (FIG. 3 (a)).

Next, after the groove 4 is formed by dry etching and the nitride film 5 is formed, the entire surface is dry-etched to leave the nitride film 5 only on the side wall of the groove 4 (FIG. 3B).

After removing the resist 3, selective oxidation is performed to form an oxide film 6 on the surface and the bottom of the groove 4. Next, after removing the nitride film 5, boron is thermally diffused to form the gate region 7 (FIG. 3C).

Next, a source diffusion window is opened in the oxide film 6 on the surface by photolithography to diffuse arsenic to form a source region 8 (FIG. 3 (d)), and then the gate electrode 9 is made of Al (aluminum). And pattern the source electrode 10.
(Fig. 3 (e)).

The characteristic of the static induction transistor thus manufactured is that the gate portion facing the drain (not shown) formed on the back surface of the semiconductor substrate 1 in a known manner is formed of the oxide film 6. The depletion layer does not extend in the drain direction so that the capacitance between the gate and the drain is reduced, and high frequency operation can be performed.

[0008]

However, in the conventional structure described above, when the Al electrode and the gate region are contacted with each other, the shape of the groove 4 after oxidation is the oxide film as shown in FIG. When strained by Al and Al sputtering is performed,
Since the eaves (overhang) can be formed as shown in (c), the gate may not be contacted in some cases, which may increase the gate resistance or complicate the manufacturing process, resulting in poor yield.

An object of the present invention is to provide a static induction transistor without a gate contact defect and a method for manufacturing a static induction transistor capable of increasing the yield without using complicated steps.

[0010]

In order to achieve the above object, the present invention provides a drain electrode formed on the back side of a low resistance first conductivity type semiconductor substrate, and a high resistance first electrode on the upper surface of the semiconductor substrate. A first conductivity type semiconductor layer is formed, and a low resistance first conductivity type source region is formed on the semiconductor layer;
A groove is formed so as to surround at least a part of the source region, and a silicon oxide layer is formed below the groove,
In an electrostatic induction transistor in which a gate region of a second conductivity type opposite to the first conductivity type is formed on a side wall of the groove, the side wall of the groove has an angle within a range of 60 degrees to 80 degrees. It is characterized by the provision of a taper.

Further, a drain electrode is formed on the back side of the low resistance first conductivity type semiconductor substrate, and a high resistance first conductivity type semiconductor layer is formed on the upper surface of the semiconductor substrate. A source region of the first conductivity type having a low resistance is formed thereon, a groove is formed so as to surround at least a part of the source region, and a silicon oxide layer is formed below the groove. A method of manufacturing an electrostatic induction transistor in which a gate region of a second conductivity type opposite to the first conductivity type is formed on a side wall of the semiconductor device, wherein a groove is cut in the high resistance first conductivity type semiconductor layer. After that, the entire surface is oxidized, and a step of patterning the resist by a photographic process is performed. A gate diffusion window is formed by removing the oxide film on the sidewall portion of the groove by wet etching using the resist as a mask, and by thermal diffusion. Forming a over preparative area, and characterized in that ohmic contact with the gate electrode on the gate region.

[0012]

According to the above means, the side wall of the trench for gate diffusion is formed.
By forming an angle of 60 to 80 degrees, the overhang shape as shown in Fig. 4 is improved when forming the Al film by sputtering, which was a problem in the past, and the contact between the gate electrode and the gate region is easy. Moreover, it is possible to manufacture by almost the same process as the conventional manufacturing process without adopting a more complicated process.

Further, the resist is patterned by a step of oxidizing the entire surface after cutting the groove in the high resistance first semiconductor layer and a photographic step, and the oxide film on the side wall portion of the groove is wet-etched by using the resist as a mask. After the removal, the step is simplified by forming a gate region by thermal diffusion and ohmic-bonding the gate electrode to the gate region. Since it does not occur, and the shape is less likely to cause overhang when the Al film is formed by sputtering, it is easy to make contact between the gate electrode and the gate region, which leads to high yield.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. The members corresponding to those described with reference to FIGS. 3 and 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

1 (a) to 1 (c) show the structure of a first embodiment of a static induction transistor according to the present invention and the manufacturing process thereof.

In the first embodiment, as shown in the figure, "N plus"
An “N-minus” epitaxial layer 2 is formed on the semiconductor substrate 1. Then, the groove 4 is formed on the surface side of the epitaxial layer 2, and the angle A of the side wall 4a of the groove 4 in which the nitride film 5 is formed is 60 degrees to 80 degrees (FIG. 1).
(a)). Further, an oxide film 6 made of silicon oxide is formed on the bottom and the surface side of the groove 4 (FIG. 1 (b)), and there is a gate diffusion window (gate region) 7 in the epitaxial layer 2 from the side wall 4a of the groove 4, It is in ohmic contact with the gate electrode 9 (Fig. 1
(c)).

When the groove 4 is formed by dry etching, vertical etching is usually performed, but in this embodiment, when etching is performed using SF ₆ + CCl ₄ type gas, the polymer is attached to the side wall 4a. However, since the etching is performed, the taper is attached.

When the taper angle is 60 degrees or less, the sidewall 4a of the groove 4 is formed when the nitride film 5 is etched in the next step.
Since the nitride film 5 in a part is also etched, it must be 60 degrees or more. Further, if the taper angle is 80 degrees or more, an overhang is formed on both sides of the groove 4 when Al is sputtered, and the step cover does not work well, and contact with the gate region 7 cannot be made.

For the adjustment of the taper angle, SF ₆ :
The taper angle can be freely adjusted by changing the flow rate ratio of CCl ₄ . The taper angle becomes smaller as the flow rate of CCl ₄ is increased.

2 (a) to 2 (e) show the structure of the second embodiment of the static induction transistor according to the present invention and the manufacturing process thereof.

In the second embodiment, as shown in the figure, "N plus"
Using the semiconductor substrate 1 in which the "N-minus" epitaxial layer 2 is formed on the semiconductor substrate 1, first, the resist 3 is patterned by photolithography to form a mask for cutting the groove 4. Next, dry etching of silicon is performed using SF ₆ type gas to form the groove 4. At this time, the thickness of the resist 3 is about 1 μm, the width of the groove 4 is 5 μm, and the depth is 1 μm (FIG. 2 (a)).

After removing the resist 3, the entire surface is oxidized, the field oxide film (silicon oxide layer) 6 is patterned by photolithography to form the resist 3, and a mask for etching the oxide film 6 is formed (see FIG. 2 (b)).

Next, the oxide film 6 is wet-etched with buffer hydrofluoric acid to open a window for gate diffusion. After removing the resist, diffuse the boron by thermal diffusion,
The gate region 7 is formed (FIG. 2 (c)).

Next, resist patterning for window formation for source diffusion is performed by photolithography, and C
The oxide film 6 is dry-etched with an F ₄ -based gas to form a source diffusion window, arsenic is implanted by implantation, and a source region 8 is completed through a diffusion process (FIG. 2).
(d)).

Next, after Al sputtering is performed, the resist 3 is patterned by photolithography to serve as a mask for forming the gate electrode 9 and the source electrode 10. Next, Al is dry-etched with a SiCl ₄ system gas and the resist 3 is removed to complete the device (FIG. 2).
(e)).

[0026]

As described above, according to the first aspect of the invention, the taper of the side wall of the groove formed so as to surround at least a part of the source region is in the range of 60 to 80 degrees. Thus, it is possible to provide the static induction transistor in which the yield reduction due to defective gate contact is prevented.

According to the second aspect of the present invention, the element can be formed without using complicated steps, and the shape change due to the oxide film at the time of forming the gate contact, which has been a problem in the related art, is caused. Therefore, it is possible to provide a method for manufacturing an electrostatic induction transistor that can improve the yield reduction due to a defective gate contact or the like.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration and a manufacturing process of a first embodiment of a static induction transistor of the present invention.

FIG. 2 is a diagram showing a configuration and a manufacturing process of a second embodiment of the static induction transistor of the present invention.

FIG. 3 is a diagram showing a configuration and a manufacturing process of a conventional static induction transistor.

FIG. 4 is an explanatory diagram for explaining a defect of a conventional static induction transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 3 ... Resist, 4 ... Trench, 4a ... Side wall, 7 ... Gate region,
8 ... Source region, 9 ... Gate electrode, 10 ... Source electrode.

Claims (2)

[Claims] 1. A drain electrode is formed on the back side of a low resistance first conductivity type semiconductor substrate, and a high resistance first conductivity type semiconductor layer is formed on the upper surface of the semiconductor substrate. A source region of the first conductivity type having a low resistance is formed thereon,
A groove is formed so as to surround at least a part of the source region, and a silicon oxide layer is formed below the groove,
In an electrostatic induction transistor in which a gate region of a second conductivity type opposite to the first conductivity type is formed on a side wall of the groove, the side wall of the groove has an angle within a range of 60 degrees to 80 degrees. An electrostatic induction transistor characterized by having a taper. 2. A drain electrode is formed on the back side of a low resistance first conductivity type semiconductor substrate, and a high resistance first conductivity type semiconductor layer is formed on the upper surface of the semiconductor substrate. A source region of the first conductivity type having a low resistance is formed thereon,
A groove is formed so as to surround at least a part of the source region, and a silicon oxide layer is formed below the groove,
A method of manufacturing an electrostatic induction transistor, wherein a gate region of a second conductivity type opposite to the first conductivity type is formed on a sidewall of the groove, wherein a groove is formed in the high resistance first conductivity type semiconductor layer. After oxidizing, the whole surface is oxidized, and there is a step of patterning the resist by a photographic step, and the gate diffusion window is formed by removing the oxide film on the sidewall portion of the groove by wet etching using the resist as a mask,
A method of manufacturing an electrostatic induction transistor, characterized in that a gate region is formed by thermal diffusion, and a gate electrode is brought into ohmic contact with the gate region.