JPH07160629A - Microprocessor - Google Patents

Abstract

PURPOSE:To provide a microprocessor which can set the optimum recovery time according to the peripheral device to be accessed. CONSTITUTION:A microprocessor has a function to insert the idel status for recovery time and is provided with a recovery time setting register 105 which can change the number of clocks of the idle status, an address holding register 107 which holds the I/O address of the precedent access, a comparator 109 which compares an I/O address with the one held in the register 107, a counter circuit 103 which counts the value equal to the,number of clocks of the set idle status when the coincidence is decided by the comparator 109 between both I/O addresses, and a flip-flop 119 which outputs the waist signals for the next access in a period when an access is started to a peripheral device and the circuit 103 counts the value equal to the number of clocks of the idle status.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a cycle for a recovery time (idle status) in a bus cycle when accessing a peripheral device.
The present invention relates to a microprocessor having a function of automatically inserting

[0002]

2. Description of the Related Art When a processor continuously accesses the same peripheral device, it is necessary to insert a recovery time interval in a bus cycle for each access. Conventionally, in order to simplify the hardware design, I
A configuration has been adopted in which an idle status for a recovery time of several clocks is automatically inserted in the bus cycle at the time of / O access.

FIG. 5 is a block diagram showing a structure of a microprocessor having a function of automatically inserting the above-mentioned idle status. A counter circuit 403, a zero detection circuit 405, and a flip-flop 407 are connected to the central processing unit 401. The central processing unit 401 outputs a status signal 402 indicating that I / O access is made when the peripheral device is I / O accessed.
The status signal 402 is input to the set inputs of the counter circuit 403 and the flip-flop 407.
When the status signal 402 is output, the counter circuit 4
The count value of 03 is initialized and the flip-flop 407 is set.

The count value 404 output from the counter circuit 403 is input to the zero detection circuit 405. The zero detection circuit 405 detects that the count value 404 from the counter circuit 403 has become zero, and activates the output 406 when zero is detected. The output 406 of the zero detection circuit 405 is input to the reset input of the flip-flop 407.

A wait request signal 408 is output from the flip-flop 407 to the central processing unit 401. This wait request signal 408 is output 40 of the zero detection circuit 405 after the status signal 402 is output.
It becomes active until 6 becomes active. Then, when the wait request signal 408 is active, the central processing unit 401 inserts an idle status of a predetermined number of clocks into the bus cycle.

In the above microprocessor, I
An example of idle status insertion operation at the time of / O access is shown in the timing chart of FIG. Note that the example of FIG. 6 shows a case where the initial value of the counter circuit 403 is set to “2”, that is, a case where the idle status for two clocks is set to be inserted.

When the status signal 402 becomes low due to the I / O access of the central processing unit 401, the counter circuit 403 is initialized at the fall of the status signal 402.
2 "is set and the down count is started. Further, the flip-flop 407 is set and the wait request signal 408 becomes active, and the central processing unit 401 is activated.
Then, the weight processing is performed.

The active state of the wait request signal 408 continues until the count value 404 of the counter circuit 403 becomes zero and the flip-flop 407 is reset by the output 406 of the zero detection circuit 406. When the weight request signal 408 is active, the central processing unit 4
By 01, the idle status Ti for two clocks is inserted after the bus cycle T2. From the above, I / O
Each time access is made, the idle status is automatically inserted by the number of clocks set in the counter circuit 403.

[0009]

As described above, in the conventional microprocessor, it is used as the recovery time corresponding to the number of idle status clocks set in the counter circuit, but the recovery time depends on the operating frequency. Therefore, when operating at high speed, the recovery time becomes short, and when operating at low speed, the recovery time becomes long. If the number of idle statuses to be inserted is set to be large so that it can be used even with low-speed I / O when operating at high speed, the recovery time becomes unnecessarily long when operating at low speed, and the system performance is increased. It goes down.

On the other hand, if the number of inserted idle statuses is set to be small, the recovery time becomes short when operated at a high speed, so that the recovery time required by the low speed I / O cannot be satisfied. In that case, costly and fast I / O must be used.

The recovery time is necessary when the same I / O is continuously accessed. When a certain I / O is accessed and then a different I / O is accessed next. Requires no recovery time,
In the conventional configuration, the idle status is automatically inserted even when the access is switched to a different I / O, and the overall system performance is reduced.

The present invention has been made to solve such a conventional problem, and improves the system performance by setting an optimum number of clocks (recovery time) according to the peripheral device to be accessed. Along with trying, I /
An object of the present invention is to provide a microprocessor capable of avoiding a reduction in system performance by eliminating unnecessary insertion of idle status when switching access from O to a different I / O.

Another object of the present invention is to provide a plurality of I / Os.
An object of the present invention is to provide a microprocessor capable of setting an optimum recovery time for each, maximizing the I / O performance, and improving the system capability.

[0014]

In order to achieve the above-mentioned object, according to the present invention, when an external peripheral device is accessed,
In a microprocessor having a function of automatically inserting an idle status for a recovery time in a bus cycle, idle state storage means for storing the number of clocks of the idle status to be inserted in the bus cycle in a changeable manner, and a previous access I / of the peripheral device
An address holding means for holding an O address, a comparing means for comparing the I / O address of the peripheral device with the I / O address held in the address holding means when the peripheral device is accessed, and the comparing means. As a result of the comparison, when the I / O addresses are the same, the counting means counts the number of clocks of the idle status stored in the idle state storage means, and the counting means operates from the start of access to the peripheral device. A means for outputting a wait signal for waiting for the next access to the peripheral device until counting the number of clocks in the idle state is provided.

In another preferred aspect, the idle state storage means stores a plurality of I / O addresses corresponding to a plurality of the peripheral devices and the number of idle status clocks to be inserted for each of the plurality of I / O addresses. However, at the time of accessing the peripheral device, the clock number of the idle status corresponding to the I / O address is read from the idle state storage means and counted by the counting means.

Further, according to the present invention, in a microprocessor having a function of automatically inserting an idle status for a recovery time into a bus cycle when accessing an external peripheral device, the idle inserted into the bus cycle. Idle state storage means for changingably storing the number of status clocks, address holding means for holding the I / O address of the previously accessed peripheral device, and I of the peripheral device at the time of access to the peripheral device.
I / O address held in the address holding means
Comparing means for comparing with the O address, and counting means for down-counting the number of clocks of the idle status stored in the idle state storing means when the I / O address is the same as a result of the comparison by the comparing means. From the start of access to the peripheral device until the count value by the counting means becomes zero, there is provided means for outputting a wait signal for waiting for the next access to the peripheral device.

Further, in a preferred mode, when the zero storage means for storing zero as a set value for the counting means and the I / O address are the same as a result of the comparison by the comparison means, they are stored in the idle state storage means. If the I / O address is different, the selected value is selectively set in the counting means as the value in the zero storage means.

Further, in a preferred mode, a zero detection means for detecting that the count value of the counting means has become zero and stopping the output of the weight signal to the weight signal output means is provided.

Further, in another preferred aspect, the idle state storage means inserts a plurality of I / O addresses corresponding to the plurality of peripheral devices and a clock of the idle status inserted for each of the plurality of I / O addresses. A number is stored, and when the peripheral device is accessed, the clock number of the idle status corresponding to the I / O address is read from the idle state storage means and counted by the counting means.

[0020]

In the present invention, when an I / O access is made,
The comparing means compares the I / O address accessed in the previous bus cycle, which is the value of the address holding means, with the I / O address currently to be accessed.
When the I / O addresses match, the value of the idle state storage means is set in the counter means. At the same time, a wait signal is output from the wait signal output means, and wait processing for waiting for the next access is performed. Also, the counter means starts counting. When the counter means counts the number of clocks in the idle state, the wait signal is released. Then, while the wait signal is being output, the idle status is inserted in the bus cycle. When the comparison result of the comparison means does not match, the counter means does not count and the idle status is not inserted.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a microprocessor according to the first embodiment of the present invention.
In FIG. 1, the microprocessor of this embodiment includes a central processing unit 101, a counter circuit 103, a recovery time setting register 105, an address holding register 107, a comparator 109, a zero register 110, a selector 112, a zero detection circuit 117, a flip-flop 117. 119.

From the central processing unit 101, I
When the I / O access is made, the status signal 102 indicating that the I / O access is made is output. The status signal 102 is generated by the counter circuit 103 and the flip-flop 11.
It is input to the set input of 9. Status signal 10
When 2 is output, the count value for the counter circuit 403 is set and the flip-flop 119 is set.

Data bus 104 of central processing unit 101
Is connected to the recovery time setting register 105. The address bus 106 of the central processing unit 101 is connected to the address holding register 107 and the comparator 109. The recovery time setting register 105 stores the number of idle status clocks from the central processing unit 101 via the data bus 104.

The number of idle status clocks stored in the recovery time setting register 105 can be set to an arbitrary value according to the performance of the peripheral device for each peripheral device accessed by the central processing unit 101. is there. The set value of the recovery time setting register 105 is read out to the counter circuit 103 and set as a count value. The output 113 of the recovery time setting register 105 is input to the selector 112.

The address holding register 107 stores the I / O of the peripheral device previously accessed by the central processing unit 101.
The address is stored via the address bus 106. That is, the I accessed in the previous bus cycle
/ O address is held. Address holding register 10
The output 108 of No. 7 is input to the comparator 109.

When an access to the peripheral device occurs, the comparator 9 compares the accessed I / O address with the previous I / O address stored in the address holding register 107. The zero register 110 is a register that stores the value zero. The output 111 of this zero register 110
Is input to the selector 112.

The gate input of the selector 112 is
The comparison signal 114 which is the output of the comparator 109 is input. The selector 112 receives the recovery time setting register 105 or the zero register 1 according to the comparison signal 114.
The value of 10 is selected and read out and set as the output 115 in the counter circuit 103.

The count value 116, which is the output of the counter circuit 103, is input to the zero detection circuit 117. The zero detection circuit 117 detects whether or not the count value of the counter 103 has become zero, and when the zero is detected, activates its output 118.

The output 118 of the zero detection circuit 117 is input to the reset input of the flip-flop 119.
A weight request signal 120 is output from the flip-flop 119 to the central processing unit 101. Then, when the wait request signal 120 is active, the central processing unit 101 inserts an idle status of a predetermined number of clocks into the bus cycle.

The idle status insertion operation at the time of I / O access in the microprocessor of this embodiment will be described with reference to the timing chart of FIG. In the example of FIG. 2, the recovery time setting register 105
Indicates that the value "2" is set, that is, the idle status for two clocks is set to be inserted. It goes without saying that the value of the recovery time setting register 105 can be arbitrarily changed.

First, the recovery time setting register 105
A predetermined value is written to the central processing unit 101 via the data bus 104. Further, the address holding register 107 stores the I / O address accessed in the previous bus cycle. Here, for the sake of explanation, the I / O address 0100h has
Is stored.

When I / O access is performed by the central processing unit 401, the I / O address accessed by the comparator 109 in the previous bus cycle, which is the value of the address holding register 107, and the value on the address bus 106, That is, the I / O address currently being accessed is compared.

In this case, the I / O address of the address bus 106 is 0100h, and the address holding register 10
7, the comparison signal 114 (“low”) indicating the coincidence is input from the comparator 109 to the selector 112, which causes the selector 112 to select the output 113 of the recovery time setting register 105. As a result, the value “2” of the recovery time setting register 105 is written and set in the counter circuit 103 at the falling edge of the status signal 102 from the central processing unit 101.

At the same time, the status signal 102 from the central processing unit 101 sets the flip-flop 119, and the wait request signal 120 becomes "high". As a result, a wait process for waiting for the next access from the central processing unit 101 to the peripheral device is performed.

The counter circuit 103 also starts down counting. Count value 116 of the counter circuit 103
When the value becomes "0", the zero detection circuit 117 becomes "0".
Is detected, the output 118 of the zero detection circuit 117 is "high".
become. As a result, the flip-flop 119 is reset, the wait request signal 120 becomes "low", and the wait is released.

The "high" state of the wait request signal 120 continues until the count value 116 of the counter circuit 103 becomes "0" and the flip-flop 119 is reset. Then, while the wait request signal 120 is "high",
The central processing unit 101 inserts the idle status Ti for two clocks after the bus cycle T2. Therefore, the bus cycle is extended by the value of the recovery time setting register 105.

In the next bus cycle, the I / O address (01
02h) is accessed, the I / O address (0102h) accessed is the previous I / O address (01
00h), the comparison result of the comparator 109 does not match, and the comparison signal 11 indicating the mismatch is output from the comparator 109.
4 (“high”) is input to the selector 112, which causes the selector 112 to select the output 111 of the zero register 110.

As a result, the value "0" of the zero register 110 is written and set in the counter circuit 103 at the falling edge of the status signal 102 from the central processing unit 101.

In this case, since the value of the counter circuit 103 is "0" from the beginning, counting is not performed, and the flip-flop 119 set by the status signal 102 from the central processing unit 101 causes the zero detection circuit 117 to operate. Immediately reset by output 118. Therefore, the idle status is not inserted and the next access is performed. Furthermore, in the next bus cycle, I /
Since the O address (0102h) is being accessed,
Similarly to the above, the recovery time setting register 105
The bus cycle is extended by the value of.

FIG. 3 shows the configuration of a microprocessor according to the second embodiment of the present invention. Here, the first shown in FIG.
The same components as those in the embodiment of FIG. Therefore, the description of the components denoted by the common reference numerals is omitted.

Recovery time setting register 3 of this embodiment
A data bus 104 and an address bus 106 are connected to 05. This recovery time setting register 305
In the table, a plurality of I / O addresses and recovery times (clock numbers of idle status) for each peripheral device designated by the I / O addresses are set and stored. FIG. 4 shows an example of contents set in the recovery time setting register 305. As shown in FIG. 4, a recovery time is set for each of a plurality of different I / O addresses.

Such a recovery time setting register 3
By including 05, the recovery time allocated to the I / O address corresponding to the I / O address specified by the address bus 106 can be set in the counter circuit 103 when the value is read by the selector 112. .

Therefore, I / Os having different recovery times
When multiple (peripheral devices) are used, each I
The optimum recovery time is selected for / O, and the system performance is improved. Regarding the insertion operation of the idle status at the time of I / O access of the second embodiment, I
Except that the recovery time is set for each / O address
Since the operation is the same as that of the first embodiment shown in FIGS. 1 and 2, description thereof will be omitted.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments. For example, in the embodiment, the example in which the recovery time is down-counted by the counter circuit 103 is shown, but it is also possible to up-count to the value of the recovery time. In that case, instead of the zero detection circuit 117, a detection circuit that detects that the count value of the counter circuit 103 becomes equal to the recovery time set value and resets the flip-flop 119 is provided.

[0045]

As described above, according to the microprocessor of the present invention, the number of idle status clocks to be inserted when the peripheral device is accessed is variable.
The optimum number of clocks (recovery time) can be set according to the peripheral device to be accessed, and the system capability can be improved. Further, when the access is switched from one I / O to another I / O, the idle status for the recovery time is not inserted, so that the system performance can be prevented from being lowered by the unnecessary insertion of the idle status. .

Further, since the optimum recovery time is stored for each of a plurality of I / Os and the recovery time is switched every time it is accessed, the optimum recovery time can be set for the accessed I / O. . Therefore, it is possible to maximize the I / O performance, and it is possible to improve the system capability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microprocessor according to a first embodiment of the present invention.

2 is a timing chart showing an idle status insertion operation at the time of I / O access in the microprocessor of FIG. 1. FIG.

FIG. 3 is a block diagram showing a configuration of a microprocessor according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an example of setting contents of a recovery time setting register.

FIG. 5 is a block diagram showing an example of a conventional microprocessor.

6 is a timing chart showing an idle status insertion operation at the time of I / O access in the conventional microprocessor shown in FIG.

[Explanation of symbols]

 101 Central Processing Unit 102 Status Signal 103 Counter Circuit 104 Data Bus 105, 305 Recovery Time Setting Register 106 Address Bus 107 Address Holding Register 109 Comparator 110 Zero Register 112 Selector 117 Zero Detection Circuit 119 Flip Flop 120 Wait Request Signal

Claims (6)

[Claims] 1. A microprocessor having a function of automatically inserting an idle status for a recovery time into a bus cycle when accessing an external peripheral device, wherein the number of clocks of the idle status to be inserted into the bus cycle Of the peripheral device that has been accessed last time, and an I / O of the peripheral device at the time of accessing the peripheral device.
Comparing means for comparing the address with the I / O address held in the address holding means; and the idle stored in the idle state storing means when the I / O address is the same as a result of the comparison by the comparing means. Counting means for counting the number of status clocks, and a wait signal for waiting for the next access to the peripheral device from the start of access to the peripheral device until the counting means counts the number of clocks in the idle state A microprocessor comprising: 2. The idle state storage means stores a plurality of I / O addresses corresponding to a plurality of the peripheral devices and the number of idle status clocks to be inserted for each of the plurality of I / O addresses, 2. The microprocessor according to claim 1, wherein the number of clocks of the idle status corresponding to the I / O address is read from the idle state storage means and counted by the counting means when the device is accessed. 3. A microprocessor having a function of automatically inserting an idle status for a recovery time into a bus cycle when accessing an external peripheral device, wherein the number of clocks of the idle status to be inserted into the bus cycle Of the peripheral device that has been accessed last time, and an I / O of the peripheral device at the time of accessing the peripheral device.
Comparing means for comparing the address with the I / O address held in the address holding means; and the idle stored in the idle state storing means when the I / O address is the same as a result of the comparison by the comparing means. Counting means for down-counting the number of status clocks; and means for outputting a wait signal for waiting for the next access to the peripheral device from the start of access to the peripheral device until the count value by the counting means becomes zero. A microprocessor comprising: 4. A value stored in the idle state storage means when the I / O address is the same as a result of comparison by the zero storage means for storing zero as a set value for the counting means. 4. The microprocessor according to claim 3, further comprising selection means for selectively setting the value of the zero storage means in the count means when the I / O addresses are different. 5. The zero detection means for detecting that the count value of the counting means has become zero and stopping the output of the weight signal to the weight signal output means is provided. The microprocessor according to claim 4. 6. The idle state storage means stores a plurality of I / O addresses corresponding to a plurality of the peripheral devices and the number of idle status clocks to be inserted for each of the plurality of I / O addresses, 4. The microprocessor according to claim 3, wherein the number of clocks of the idle status corresponding to the I / O address is read from the idle state storage means and counted by the counting means when the device is accessed.