JPH0744491A - Contention arbitration device - Google Patents

Abstract

PURPOSE:To reduce the cost by facilitating timing control of arbitration operation. CONSTITUTION:Each of logic modules 10a-10d has a different arbitration logic. A succeeding phase designation section 10e designates a logic module of an arbitration logic taking a bus right request whose priority is lower by one rank than a bus right request in the arbitration logic next when any of the logic modules 10a-10d makes arbitration. For example, when the priority of the logic module 10a is in the order of request signals 1, 2 and the module makes arbitration providing a bus right to the request signal 1 in this state, a succeeding logic module places the higher priority on the request signal 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contention arbitration device which arbitrates a plurality of bus requests in an information processing device.

[0002]

2. Description of the Related Art In an information processing apparatus, for example, a DMA
In some cases, a plurality of (direct memory access) control circuits are provided, and these circuits respectively perform data DMA transfer. In such a case, if the respective DMA control circuits perform data transfer at the same time, data will collide on the system bus.
A competitive arbitration device is used.

FIG. 2 is a block diagram showing a main part of an information processing apparatus having a conventional competitive arbitration device. The device shown is
Memory 1, 2, processor 3, DMA control circuit (hereinafter,
DMAC) 4 (4-1 to 4-4), logic gate 5
a (5a-1 to 5a-5), 5b (5b-1 to 5b-
5) Competing arbitration circuits 6a and 6b and buses 7a and 7b. The memories 1 and 2 are connected via buses 7a and 7b, which are common buses, and the processor 3 and the DMAC 4 are configured to transfer data between the memories 1 and 2.

The processor 3 is a control unit for controlling the information processing apparatus, and the DMAC 4 is a control circuit for direct memory access transfer of data between the memories 1 and 2, respectively. Also, logic gate 5
a and 5b are controlled by the contention arbitration circuits 6a and 6b, respectively, and the opening and closing operations thereof cause the processor 3 and the DMA.
The right to use the buses 7a and 7b is given to either C4. The contention arbitration circuits 6a and 6b include logic gates 5a and
It is a circuit that controls 5b to arbitrate the buses 7a and 7b, which will be described in detail later.

FIG. 3 is a diagram showing the configuration of the contention arbitration circuits 6a and 6b. The circuit shown in the figure includes a ROM (Read Only Memory) 101, synchronous circuits 102 and 103, timing control circuits 104 and 105, a delay circuit 106, an execution control circuit 107, and OR circuits 108 and 109. RO
M101 is a read-only memory that incorporates arbitration logic, and the synchronization circuit 102 is a circuit that outputs request signals RQ1 to 5 to the ROM 101 in response to the sample clock signal S1 from the timing control circuit 105, and the synchronization circuit 1
Reference numeral 03 is a circuit that outputs execution signals ACT1 to ACT5, which are arbitration results of the ROM 101, in response to the sample clock signal S2 from the timing control circuit 104.

Further, the delay circuit 106 and the execution control circuit 10
Reference numeral 7 is a circuit for generating the sample clocks of the synchronization circuits 102 and 103. Further, the OR circuit 108 performs a logical sum operation of the request signals RQ1 to RQ5 and inputs it to the timing control circuit 105 as RQI.
The R circuit 109 is a circuit that performs a logical sum operation of the execution signals ACT1 to ACT5 and inputs the result as ACTI to the execution control circuit 107. Then, MR1 is the execution control circuit 107.
MR2 signal that indicates whether or not there is an arbitration result
Is a delay signal of MR1, AE is a data transmission end signal, C
L is a basic clock signal.

Next, the operation of the contention arbitration circuit will be described. The request for data transfer is made by request signals RQ1 to RQ1.
Received by RQ5, the arbitration result is the execution signal ACT1.
~ Output as ACT5. The request signals RQ1 to RQ5 and the execution signals ACT1 to ACT5 are
It corresponds to the processor 3 and the DMACs 4-1 to 4-4 shown in FIG. 2, respectively. Then, the arbitration is logically realized on the ROM 101 by a signal obtained by sampling the request signals 1 to 5 and the previous execution signals ACT 1 to 5 sampled by the synchronizing circuit 103 by the synchronizing circuit 102.

In the logical configuration of the ROM 101, the order is predetermined for the request signals RQ1 to RQ issued from the processor 5 and the DMAC 4 in total. For example, request signals RQ1 to RQ
When the order is determined in the order of 5 (returning to RQ1 after RQ5), when RQ2 and RQ4 make a transmission request in the initial state, RQ2 is selected and the execution signal ACT2 becomes "1". . Then, from the next time onward, arbitration is performed in consideration of the previous execution state so that the same signal will not be selected despite the presence of other signals. For example, RQ2, RQ
4 and RQ5 request transmission, and last time execution signal A
When CT2 becomes "1", RQ4 is selected.

When the arbitration processing is performed by the logic of the ROM 101 as described above, a special circuit is required for sampling the synchronizing circuits 102 and 103. That is, the configuration of the timing control circuits 104 and 105, the delay circuit 106, and the execution control circuit 107 in FIG. 3 is a circuit for generating this sample clock.

FIG. 4 shows the timing control circuits 104 to 104.
6 is a timing chart of the OR circuit 109. First, the signal RQI becomes "0" by the OR circuit 108 when a request for transmission is issued to the request signals RQ1 to RQ5. When the data transmission is completed, the signal AE is externally input by one pulse. Then, the signal RQI becomes "1" when the signal AE is input, and the signal ACTI becomes "0" when the signal AE is input. The signal MR1 is the signal ACTI.
Becomes "1", and becomes "0" when the signal AE is input. The signal MR2 is obtained by delaying the signal MR1 by the delay circuit 106, and is input to the timing control circuit 105.

The timing control circuit 105 uses the signal RQI.
When both the signal MR2 and the signal MR2 are "0", "1" is output to the sample clock S1 at the rising of the basic clock CL,
It operates as a flip-flop that outputs "0" to the sample clock S1 at the next basic clock. Further, the timing control circuit 104 is an AND circuit of the sample clock S1 and the signal MR1, and the sample clock S1
When both the signal MR1 and the signal MR1 are "1", it becomes "1".

By the operations of the competing arbitration circuits 6a and 6b, the arbitration processing of the request signals RQ1 to RQ5 is performed, and the processing of the processor 3 or the DMAC 4 is performed.
The DMA transfer processing of -1 to 4-4 is performed.

[0013]

However, the above-mentioned conventional competitive arbitration device has the following problems. (1) The timing control is complicated and the circuit configuration is complicated. Therefore, the amount of hardware is large and the cost is high.

(2) The memories 1 and 2 contain instruction codes and data to be executed by the processor 3, and if the bus request levels of the processor 3 and the other DMAC 4 are the same, the processor 3 will The bus waiting time for accessing becomes long. However, in the conventional contention arbitration device, since all the bus request levels are the same, there arises a problem that the waiting time of the processor 3 becomes long, and as a result, the processing capability of the processor 3 becomes low. It was

(3) If the bus transfer end signal is not input for some reason, the arbitration operation is stopped and locked. As a result, the competition arbitration apparatus will stop operating completely.

The present invention has been made to solve the above-mentioned conventional problems, and is competitive at a low cost, capable of improving the performance of the processor, and capable of preventing the arbitration operation from reaching the locked state. An object is to provide an arbitration device.

[0017]

According to a first aspect of the present invention, there is provided a contention arbitration device for arbitrating bus right requests generated from a plurality of bus right request sources, wherein the request signals for the plurality of bus right requests are provided. On the other hand, when arbitration is performed by a plurality of logic modules that execute arbitration processing with different arbitration logics and an arbitrary logic module, a request signal with a lower priority than the request signal in the arbitration logic of the logic module. And a next-phase designating unit for designating the logic module of the arbitration logic having the highest level as the next stage.

In the contention arbitration device of the second invention, in the first invention, a special level request signal having the highest arbitration priority is provided in each request signal generated from a plurality of bus right request sources, and each logic module is provided. Includes a normal arbitration logic having a request signal other than the special level request signal as the highest priority, and a priority logic change arbitration logic having the special level request signal as the highest priority. When a request signal is input, in the next arbitration process, the priority logic change arbitration logic is configured to be executed, and the next phase designating unit causes an arbitrary logic module to execute the arbitration process with the priority logic change arbitration logic. Then, the next logical module is configured to specify the same logical module as the logical module that performed the arbitration process. It is characterized in that there.

In the contention arbitration device of the third invention, in the first or second invention, the logic module simultaneously executes a process of accepting a request signal from an arbitrary bus right request source and a process of ending the arbitration being executed. It is characterized by doing.

The competitive arbitration device of the fourth invention is the competing arbitration device according to any one of the first to third inventions, further comprising a monitoring timer for transmitting a time-out signal when a predetermined time has elapsed from the start of arbitration execution in an arbitrary logic module. It is characterized by having.

In the competitive arbitration device of the fifth invention, in the fourth invention, an end signal indicating that the processing of the arbitration destination to which the bus right is given is completed, a time-out signal generated from the monitoring timer, and an arbitrary logic module are provided. If all of the running display signals indicating that arbitration processing is being executed are off,
And when the end signal or the timeout signal is on and the running display signal is on, an operation timing signal for performing the arbitration is output, and both the end signal and the timeout signal are off and the running When the display signal is on, a timing control unit for stopping the output of the operation timing signal is provided.

[0022]

In the competitive arbitration device of the first invention, for example,
The priority order of the first logic module is in the order of request signals 1, 2, 3, and 4, and the priority order of the second logic module is in the order of 2, 3, 4, 1. now,
When the request signal 1 is generated and the arbitration is performed by the first logic module, the next phase specifying unit specifies the second logic module having the request signal 2 as the highest priority in the priority order as the next logic module. To do. After that, similarly, when arbitration is performed in a certain logic module, the logic module whose highest priority is the bus right request having one lower priority in the logic module becomes the next logic module.

In the contention arbitration apparatus of the second invention, for example, the request signal 5 is designated as a special level request signal having a different priority from the other request signals among the request signals 1 to 5. And request signal 5
And the request signals other than this occur simultaneously, the logic module performs arbitration by the priority logic change arbitration logic.
Further, the next phase designation unit designates the next logic module as the same logic module as the arbitrated logic module. For example, when the first logic module arbitrates with the priority logic change arbitration logic, the next logic module also becomes the first logic module and arbitrates another request signal generated simultaneously with the request signal 5.

In the competitive arbitration apparatus of the third invention, for example, when the special level request signal 5 and the request signal 3 are generated while the arbitration processing of the request signal 1 is being performed, the logic module ends the request signal 1. The request signal 5 is received as well as being processed.
After that, the request signal 5 is terminated, the request signal 3 is accepted, and the request signal 3 is arbitrated.

In the competitive arbitration device of the fourth aspect of the invention, the monitoring timer starts counting when the running display signal is turned on and counts up while the running display signal is on. Then, since the running display signal is normally turned off within the set time, the turning off resets the count. On the other hand, if the running display signal remains on for some reason, that is, if the arbitration operation is locked, the monitoring timer sends a time-out signal.

In the contention arbitration apparatus of the fifth aspect of the invention, the timing control section sends out the program operation timing signal when both the end signal and the time-out signal are off and the running display signal is off. When the arbitration process for a certain request signal is performed and the execution display signal is turned on, the timing control unit stops the output of the program operation timing signal, the arbitration process is terminated, and the execution display signal is turned off. To continue. On the other hand, when the running display signal is on and the time-out signal is input, the timing control unit outputs the program operation timing signal again. As a result, the arbitration operation remaining in the locked state is released, and the process can proceed to the next step.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a competitive arbitration device of the present invention. The device shown in the figure comprises a logic module storage unit 10, a receiving circuit 11, an instruction register 12, a timing control unit 13, and a monitoring timer 14.

The logic module storage unit 10 comprises a read only memory (ROM), and the logic module 10
a, 10b, 10c, 10d and the next phase designation unit 10
Store e. Each of the logic modules 10a to 10d is composed of a program and has different arbitration logic. Further, the next phase designation unit 10e
When the arbitration is performed by any of the logic modules 10a to 10d, a request signal having a lower priority than the request signal in the arbitration logic of the logic module is designated as the highest one, and the logic module of the arbitration logic is designated next. ,
When the arbitration processing is executed by the priority logic change arbitration logic, it has a function of designating the next logic module as the same logic module as the logic module that has performed the arbitration processing.
The details of these logic modules 10a to 10d and the next phase designation unit 10e will be described later.

The receiving circuit 11 receives the request signal i (i =
1 to 4), a special level request signal 5, a phase designation signal, a priority logic change signal, a display signal during selection, a display signal during execution, and an end signal, and the output synchronized in the program operation timing is used as a program address. The data is output to the modules 10a to 10d and the next phase designation unit 10e. The instruction register 12 synchronizes the code outputs of the logic modules 10a to 10d and the next phase designating section 10e with the program operation timing and outputs them.

The timing control section 13 has a function of outputting a program operation timing signal to the receiving circuit 11 and the instruction register 12 to control the program execution timing. That is, it has a function of intermittently stopping the timing output based on the input condition, and the detailed description of the input condition and the like will be described later. The monitoring timer 14 monitors the execution state of the program, and outputs an instruction to forcibly terminate the program to the timing control unit 13 when the program stops for a certain time or longer.

Next, the configuration of the logic modules 10a to 10d will be described. FIG. 5 is an explanatory diagram of the configuration.
First, the address input to the logic module storage unit 10 is
As mentioned above, it is divided into six fields. That is, phase designation, request reception, priority logic change reception, execution display reception, selection display, and end reception.

Here, 2 bits of the phase designation select each of the logic modules 10a to 10d. In addition, each of the logic modules 10a to 10d has a built-in program that executes four stages of request reception, request selection, execution, and end, and simultaneously executes the arbitration end processing being executed and the next request reception processing. It is configured to run. Further, request reception is a 5-bit field for five request signals i, and hereinafter, priority logic change reception, execution display reception, selection display, and end reception are 1-bit fields, respectively.

The output from the logic module storage unit 10 is
It is divided into five fields: next phase designation, selection output, priority logic change, execution display, and selection display. Here, the next phase designation is to determine the jump destination to the next logic module 10a to 10d according to the priority order determination logic described later. Further, the selection output is a 5-bit field indicating the selection output for the request signal i. Hereinafter, priority logic change, execution indication, and selection indication are 1-bit fields respectively, and priority logic change reception of the input address is received. , The display during execution is received, and the display during selection is supported.

Next, the decision logic of the logic modules 10a to 10d will be described. Request signal 1 shown in FIG. 1 is represented by A, request signal 2 by B, request signal 3 by C, request signal 4 by D, and request signal 5 by α. Here, the request signal 5 is a special level request signal, and is a special bus right request signal corresponding to a program memory access request by the processor in the information processing apparatus incorporating the contention arbitration apparatus.

This is as described in the section of the prior art.
When the request signal of the processor is assigned to the same level as other request signals, the processor waits long for access, and it takes a lot of time to access the program memory, resulting in a decrease in the processing capability of the microprocessor device. Therefore, it is assigned to a special level, and its character representation is changed to show that it is different from other levels.

Further, each logic module 10a-10d
Is a normal arbitration logic in which a request signal (= request A, B, C, D) other than the special level request signal (request α) is the highest priority, and the special level request signal is the highest priority. Has priority logic change arbitration logic,
When the special level request signal is input, the same logic module is configured to execute the priority logic change arbitration logic in the next arbitration processing. In addition, the next phase designation unit 10e is used to select any of the logic modules 10a to 1
When 0d executes the arbitration process by the priority logic change arbitration logic, the next logic module 10a to 10d is configured to specify the same logic module as the logic module that performed the arbitration process.

Specifically, each logic module 10a-1
The priority of 0d is as follows. First, the priority order of the logic module 10a is “A, α, B, C, D” in the descending order in the case of the normal arbitration logic which is not the priority logic change state, and in the order of “α, α in the priority logic change state”. A, B,
C, D ". Hereinafter, in the logic module 10b, when the priority logic change state is not set, “B, α, C,
D, A ”, and in the priority logic change state,
“Α, B, C, D, A”. Further, in the logic module 10c, if the priority logic change state is not set,
“C, α, D, A, B”, and in the priority logic change state, “α, C, D, A, B” in order. Further, in the logic module 10d, when the priority logic change state is not set,
“D, α, A, B, C” in descending order, and “α, D, A, B, C” in order of priority logic change state.

Next, the phase transition in the logic modules 10a to 10d will be specifically described. First, the case of normal arbitration logic will be described. FIG. 6 is an example of phase transition. Now, the logic module 10a is running (phase 0). When the request of A is received in this state, the process of A is executed. Then, the next phase in this case is the phase 1 in which B, which is the next rank of A, is the highest rank, so this is designated.

Then, when the request of D is received in the state where the vehicle is traveling in the phase 1 state this time, the process of D is executed unless there is another request of higher priority. Further, the next phase is phase 0 in which A, which is the next rank to D, is the highest rank, so this is designated.

FIG. 7 is a timing chart of such a state. First, when the phase is “0”, there is an A request (request signal 1), and when this is selected, the selected display signal is turned on. Next, when the stage under execution is entered, the display signal during selection is turned off, the display signal under execution is turned on, and the selection signal 1 corresponding to the A request is turned on. Further, here, the phase 1 is designated as the designation of the next phase.

When the selection signal 1 is turned on, the request signal 1 is automatically turned off externally. That is, since the request signal generated from the bus right request source is configured to be transmitted for a predetermined time, the request signal to the contention arbitration device is turned off after the elapse of this time.

A bus right is given to the bus right request source that generated the request signal 1, processing such as data transfer is performed, and then an end signal indicating that the processing is completed is sent from the data transfer destination. When input, the next phase designation unit 10e designates phase 1 as the next phase designation, the termination processing is performed in the state of this phase 1, and the selection signal 1 is turned off. Then, after that, the request signal 4 is processed in the same manner as in the case of the request signal 1 in the phase 1 state. After this phase, phase 0
Therefore, after that, the phase 0 is executed.

Next, the case of the priority logic change state will be described. That is, every time the phase shifts, if the highest level request in that phase exists, the second special level α in the phase will not be selected, and as a result, the performance of the processor will deteriorate. In order to avoid such a decrease in the capacity of the processor, each logic module 10a to 10d has the priority logic change arbitration logic as described above.

FIGS. 8 and 9 are a phase transition explanatory diagram and a timing chart in such a case, respectively.
The examples of these figures show the case where the request A is accepted and selected and executed in phase 0, and the requests C and α are accepted at the same time during the termination processing.

First, in the case where the arbitration process of the request A is performed in the phase 0, if the special level request α exists during the termination / acceptance process of the request A, the logic module 10a turns on the priority logic change bit. . As a result, the logic module that performs the next arbitration is the logic module 1 in the same phase.
0a, which is the priority logic change arbitration logic. Here, in the phase 0, in the case of the priority logic change state, the priority is “α, A, B, C, D”. Therefore, even if the request C and the special level request α exist, the special level request α is selectively executed, and the priority logic change bit is turned off when the execution is completed.

When the special level request α is arbitrated, the next phase also becomes the same phase, so the next phase designating section 10e designates phase 0. As a result, the priority returns to “A, α, B, C, D”. Here, since the request C remains, the request C is processed next.

Next, the detailed structure and operation of the timing controller 13 will be described. FIG. 10 is a diagram for explaining the configuration and timing of the timing control unit 13,
(A) is the circuit diagram, (b) is a timing chart.

The timing controller 13 includes an OR circuit 20,
21 and AND circuits 22, 23 and NOT circuit 24. The end signal and the timeout signal are input to the OR circuit 20, and the output thereof is input to the AND circuit 22.
The execution display signal is input to the other input terminal of the AND circuit 22, and the output of the AND circuit 22 is input to the OR circuit 21. Further, a running display signal is connected to the other input terminal of the OR circuit 21 via a NOT circuit 24. The output of the OR circuit 21 is input to the AND circuit 23,
A basic timing is input to the other input terminal of the AND circuit 23. The output of the AND circuit 23 is the output of the timing control unit 13.

The timing control unit 1 thus configured
3 normally outputs a program operation timing signal. That is, the end signal of the bus right request generated from the bus right request source, the time-out signal generated from the monitoring timer 14, and the in-progress display signal indicating that the arbitrary logic modules 10a to 10d are executing the arbitration processing are turned off. If it is, the program operation timing signal is output.

In this state, when the execution display signal is turned on, the timing controller 13 stops outputting the program operation timing signal. As a result, the states of the receiving circuit 11 and the instruction register 12 of the timing supply destination do not change,
Therefore, arbitration processing such as phase shift or priority logic change of each logic module 10a-10d does not occur. After that, when the running display signal is turned off, the program operation timing signal is output, and each logic module 10a is output.
10 to 10d carry out processing such as transition to the next program stage.

On the other hand, when the end signal indicating the end of the process or the time-out signal from the monitoring timer 14 is turned on,
As shown in 0 (b), the program operation timing signal is output. As a result, the execution waiting state of the program is released.

Next, the structure and operation of the monitoring timer 14 will be described. FIG. 11 is a diagram showing its configuration and operation timing. The monitoring timer 14 is composed of a frequency dividing circuit having a basic timing signal as a clock input, and is reset when the execution display signal is in the off state. And
When a predetermined count number is reached, a time-out signal is sent out. That is, as shown in FIG. 11B, when the running display signal is in the off state, the frequency dividing circuit is in the timer reset state, and therefore the time-out signal is not output. Then, when the running display signal is turned on, the frequency dividing circuit counts the clock at the basic timing, and while the running display signal is on, the counting is continued. In addition, since the display signal during execution is normally turned off before the counter becomes full, no timeout occurs.

On the other hand, when the on-state of the running display signal exceeds the specified value, the frequency dividing circuit sends out a time-out signal.
When this time-out signal is output from the monitoring timer 14, as described above, the program operation timing is output from the timing control unit 13, the program execution waiting state is canceled, and the arbitration process can return to the idle state. . Therefore, even if the end signal is not input for some reason, it is possible to prevent the arbitration operation from being locked while being stopped.

In the above embodiment, the case where there are five bus right requesting sources has been described, but the number of bus right requesting sources is not limited to this number. Play.

[0055]

As described above, according to the contention arbitration apparatus of the first invention, a plurality of logic modules each having different arbitration logic are provided, and when arbitration is performed by an arbitrary logic module, Since the logic module is configured such that one lower request signal is the highest arbitration logic, the arbitration operation is simplified, the device configuration is simplified, and the cost can be reduced.

According to the contention arbitration apparatus of the second invention, the special level request signal having the highest priority among the request signals is provided, and when this special level request signal is generated, the logic module makes the special level request signal. Since the arbitration is performed by the priority logic change arbitration logic with the highest priority as a priority, and the next logic module is configured to specify the same logic module as the logic module that has performed the arbitration processing, for example, a processor, Even if there is a bus right request whose bus request level is different from that of another bus right request source, the bus right can be given the highest priority to that bus right request, and therefore multiple bus right requests have occurred. Even in this case, it is possible to minimize the deterioration of the processing capability of the processor or the like.

According to the contention arbitration apparatus of the third aspect of the invention, since the logic module simultaneously executes the process of accepting a request signal from an arbitrary bus right request source and the process of ending the arbitration being executed, Even if a plurality of request signals are consecutive, the arbitration process can be quickly performed.

According to the competitive arbitration apparatus of the fourth aspect of the invention, since the monitoring timer for sending the time-out signal when a predetermined time has elapsed from the start of arbitration execution in the logic module is provided, the time monitoring of the arbitration processing can be performed. This can be performed and, for example, when the arbitration process does not end for a long time, it can be determined that some abnormality has occurred.

According to the competitive arbitration device of the fifth aspect of the present invention, the end signal indicating that the arbitration processing has ended and the time-out signal from the monitoring timer are off, and the logic module is executing the arbitration processing. When the running display signal is ON, the operation timing signal is stopped, and even if the running display signal is ON, the operation timing signal is output when the end signal or the timeout signal is turned ON. Since the timing control unit is provided, it is possible to prevent the device from reaching the locked state even if the end signal is not input for some reason.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a competitive arbitration device of the present invention.

FIG. 2 is a block diagram of an information processing apparatus including a conventional competitive arbitration circuit.

FIG. 3 is a configuration diagram of a conventional competitive arbitration circuit.

FIG. 4 is a conventional main part timing chart.

FIG. 5 is an explanatory diagram of a configuration of a logic module in the contention arbitration device of the present invention.

FIG. 6 is an explanatory diagram of phase transition of normal arbitration logic in the contention arbitration device of the present invention.

FIG. 7 is a timing chart in the case of normal arbitration logic in the contention arbitration device of the present invention.

FIG. 8 is an explanatory diagram of phase transition of priority logic change arbitration logic in the contention arbitration device of the present invention.

FIG. 9 is a timing chart in the case of priority logic change arbitration logic in the contention arbitration device of the present invention.

FIG. 10 is an explanatory diagram of a timing control unit in the competitive arbitration device of the present invention.

FIG. 11 is an explanatory diagram of a monitoring timer in the contention arbitration device of the present invention.

[Explanation of symbols]

 10a-10d Logic module 10e Next phase designation | designated part 13 Timing control part 14 Monitoring timer

Claims (5)

[Claims] 1. A contention arbitration device for arbitrating bus right requests generated from a plurality of bus right request sources, wherein arbitration processing is executed with different arbitration logic for request signals for the plurality of bus right requests. When arbitration is performed between a plurality of logic modules and an arbitrary logic module, the arbitration logic logic module whose priority is one request signal lower than the request signal in the arbitration logic of the logic module A competitive arbitration device comprising a next-phase designating unit for designating. 2. A special level request signal having the highest arbitration priority among the request signals generated from a plurality of bus right request sources is provided, and each logic module sends a request signal other than the special level request signal. A normal arbitration logic having the highest priority and a priority logic change arbitration logic having the special level request signal as the highest priority are provided, and when the special level request signal is input, the next arbitration is performed. In the processing, it is configured to execute the priority logic change arbitration logic, and the next phase designating unit, when an arbitrary logic module executes the arbitration processing by the priority logic change arbitration logic, executes the arbitration processing on the next logic module. The contention method according to claim 1, wherein the logic module is configured to specify the same logic module as the executed logic module. Apparatus. 3. The contention arbitration according to claim 1, wherein the logic module simultaneously executes a process of accepting a request signal from an arbitrary bus right request source and a process of ending the arbitration being executed. apparatus. 4. The monitoring timer according to claim 1, further comprising a monitoring timer that sends a time-out signal when a predetermined time has elapsed from the start of execution of arbitration in any logic module. Competitive arbitration device. 5. An end signal indicating that the processing of the arbitration destination to which the bus right has been given is completed, a time-out signal generated from a monitoring timer, and an execution indicating that an arbitrary logic module is executing the arbitration processing. When all the display signals are off, and when the end signal or the timeout signal is on and the running display signal is on, the operation timing signal for performing the arbitration is output, and the end signal is output. 5. The contention arbitration apparatus according to claim 4, further comprising a timing control unit that stops the output of the operation timing signal when both the time-out signal and the time-out signal are off and the running display signal is on.