JPH0715921B2 - Marking device for simultaneous measurement of multiple chips - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a marking device for marking an integrated circuit determined to be defective by a test of functions and characteristics of an integrated circuit manufactured in a wafer, and more particularly to a marking device. The present invention relates to a multi-chip simultaneous measurement marking device which performs marking when simultaneously testing the integrated circuits of (1) with one marker.

[Conventional technology]

Conventionally, in order to simultaneously test a plurality of integrated circuits (hereinafter referred to as chips) manufactured in a wafer and mark defective products, a mechanism for marking as many chips as simultaneously measured (hereinafter referred to as a marker) Was installed, and the markers and chips were made to correspond one-to-one, and the markers were operated to mark defective products.

[Problems to be solved by the invention]

In the conventional multi-chip simultaneous measurement system described above, if the number of chips for simultaneous measurement increases, it is necessary to increase the number of markers by that number. Therefore, there is a disadvantage in that a space for installing the markers is additionally required. This drawback has been one obstacle to the progress of multi-chip simultaneous measurement.

In contrast to the conventional multi-chip simultaneous measurement marking system described above, the present invention stops the one-to-one correspondence between chips and markers that are measured at the same time, and has a storage device that holds the determination result of multi-chip simultaneous measurement. , Calculate the position of the defective chip and move the stage on which the wafer is placed to position the defective chip so as to correspond to the marker, or move the marker to the position of the defective chip It has a controller for control and has the original content of marking multiple chips simultaneously with one marker.

[Means for solving problems]

The simultaneous measurement marking device of the present invention includes a stage for mounting a wafer, a test device for simultaneously testing a plurality of integrated circuits manufactured on the wafer, and a position corresponding to the head of the integrated circuits. On the wafer of the defective integrated circuit, which is determined as defective by the test device of the integrated circuits, which receives information from the storage device and a marker that marks the test result of the test device. And a controller for determining the position and moving the stage or the head to mark the head so as to correspond to the defective integrated circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In this embodiment, the marker 7 is made of laser,
Laser light from the laser 7 is transmitted through the optical fiber to the head 10
The wafer 6 is irradiated with the laser light and the chip at the irradiation position is destroyed by the laser light. The test apparatus 4 simultaneously measures a plurality of chips on the wafer 6. The test result from the test device 4 is stored in the storage device 2 via the controller 1.
After the test, the controller 1 controls the movement and positioning of the chuck top 5, which is a stage on which the wafer 6 of the probing device 3 is placed, and the defective chip in the wafer 6 is aligned with the irradiation position of the head 10. Destroy.

FIGS. 2 (a) and 2 (b) are flow charts showing the operation of the system shown in FIG.
Prior to the wafer start (step S2) to start the apparatus, the positional relationship of each chip to be measured (hereinafter referred to as DUT) is set (step S1), and the first four chips are moved to the measurement position (step S3). Simultaneous measurement (step S4) is started from the start 4 chips. After the test is completed, the judgment result is fetched from the test device 4 shown in FIG. 1 via the controller 1 and stored in the storage device 2 (step S5).
Test result If all 4 chips are non-defective (step S6), move to the next 4 chips (step S22) and start the test (step S4). Takes in the position of the defective chip (step S7).

Next, the controller 1 determines the pass / fail judgment result from the DUT1 (4 chips for simultaneous measurement are referred to as DUT1 to DUT4, respectively), and if they are defective (step S8), the controller 1 controls the chuck top 5 of the probing device 3. Then, the DUT 1 is moved to the irradiation position of the head 10 of the marker 7 (step S9), and the DUT 1 is destroyed by the marker 7 (step S1).
0). DUT2 to DUT4 take the same sequence (step S11 to step S19) to destroy the defective DUT. Next, if all the chips in the wafer have been measured (step 20), the next wafer is loaded (step S21), and if there are still unmeasured chips (step 20), the next 4 Go to the tip (step 2
3), start the test (step S4).

FIG. 2 shows a flowchart of the operation of the system of FIG. 1 by taking the simultaneous measurement of 4 chips as an example. Is applicable to.

FIG. 3 is a configuration block diagram showing another embodiment of the present invention.

In FIG. 3, a scanning unit 8 for automatically changing the position and angle of the head 10 is added to the embodiment shown in FIG.
The position of the defective chip in the controller 1 is calculated based on the result stored in the storage device 2 via the controller 1 and the test result from the test device 4, and the position and angle of the head 10 are calculated by the scanning unit 8. The irradiation position of the laser light is controlled to the position of the defective chip to destroy the defective chip.

In the above-mentioned embodiment, the case where the laser is used as the marker 7 has been described, but the present invention can also be applied to a marker that uses ink or a marker that scratches with a diamond needle.

〔The invention's effect〕

As described above, the present invention is one of the problems of simultaneous multi-chip measurement because it is possible to mark a defective integrated circuit with one marker by moving the stage on which the wafer is mounted. Since there is no increase in the space for setting markers, simultaneous measurement on multiple chips can be facilitated easily. In addition, the increase in markers associated with the simultaneous measurement of multiple chips is eliminated, so that equipment investment can be reduced.

[Brief description of drawings]

FIGS. 1 and 2 (a) and (b) are a block diagram of an embodiment of the present invention and a portion of steps S1 to S13 and steps S14 to D23 of the flowchart showing the operation, respectively.
FIG. 3 is a block diagram of the second embodiment of the present invention. 1 ... Control controller, 2 ... Storage device, 3 ... Probing device, 4 ... Testing device, 5 ... Chuck top, 6 ... Wafer, 7 ... Marker, 8 ... Marker scanning unit, 10 ……head.

Claims (1)

[Claims] 1. A stage for mounting a wafer, a test device for simultaneously testing a plurality of integrated circuits manufactured on the wafer, and a marker for marking a position of the integrated circuit corresponding to a head. A storage device that stores a test result of the test device; and a stage that obtains a position on the wafer of a defective integrated circuit which is determined to be defective by the test device among the integrated circuits when receiving information from the storage device and the stage. Or a controller for moving the head to mark the head so as to correspond to the defective integrated circuit.