JPS5895271A - Testing device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To automatically and precisely detect marking setting errors by simultaneously testing plural elements to be tested and, when tested result is inconsistent in spite of the retrial of test when accepted and rejected results are mixed, stopping the operation of an IC tester. CONSTITUTION:Plural, 2 paris e.g., elements 31, 32 to be tested in a wafer 3 are simultaneously tested by a measuring circuit 11 in an IC testor 1, and when accepted and rejected results are mixed, these results are stored in a storing and measuring circuit 25 in a wafer prober. When tested results are inconsistent each other even if the test is retired through a control circuit 21 in the prober 2 and the circuit 12, an inhibiting circuit 26 keeps its inhibiting status through a discrimination output from the circuit 25, so that the movement of the wafer 3 by prober 2 is inhibited and an alarm is generated to stop the operation of the testor 1. Thus marking setting errors by markers 22, 23 are automatically and precisely detected, inhibiting the loss accumulation due to incorrect tests.

Description

DETAILED DESCRIPTION OF THE INVENTION Motoaki Moku is concerned with a semiconductor integrated circuit 1cIl test device that simultaneously tests two or more devices under test on a wafer.

As semiconductor integrated circuits become larger and the time required for testing increases, a plurality of devices to be tested are tested simultaneously due to the need to efficiently use expensive test equipment.

So-called parallel measurement methods are becoming more and more popular. Parallel measurements in testing semiconductor integrated circuits can be carried out in various ways depending on the condition of the device under test, the purpose of the test, etc.

FIG. 1 is a diagram showing an example of a conventional semiconductor integrated circuit testing device, in which an IVi1G tester, 2 a wafer prober, and 3
Fi test wafer. The measuring circuit 11 simultaneously
The first test element 31 (hereinafter referred to as the first LIUT) and the second test element 32 (hereinafter referred to as the second LIUT
(referred to as ) shall be fully tested. The tester receives all test start signals from the wafer flowper control circuit 21 (hereinafter referred to as 10-bar control circuit) in charge of city II# of wafer flow bar 2, executes the test, 1st 1 JUT31 and 2nd L) l for Ui'32 (1 foot US and 8tWI!!! End 1g issue 10
- is sent to the bar control circuit 21. First marker 22.
The second marker 23 receives the -1't1 foot result from the entire prober control circuit 21, and only in that case, the first marker 22
J[Ji' 31, the second marker 23 is the second LI
Ll'l'32VC marking.

The wafer control circuit 24 is the flow bar control circuit 2.
Transfer instructions from No. 1 No. 11 After completion of testing and marking, move the position of wafer 3 and place the new No. 1
υU i' 31 and the second IJUT 32 are connected to the measurement circuit 11. In such a semiconductor integrated circuit testing device, the connection between the 1110-bar control circuit 21 and the first and second markers 22, 23, and the
lJLl'l' 31! 32 Correspondence between the first and second markers 22.23 (normal mechanical positional relationship) F
The setting must be done manually each time the type of wafer under test is changed.If there is an error in this setting, the LI U 'r that has passed the test will be marked.
q" is destroyed), rejected JJ [J 'l' is not marked! Dust is generated. Moreover, this setting error causes the tested υUT to be assembled into the i, +it' case, etc. After the product has been removed, it is not discovered until it is retried, and during that time, many defective products are generated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit testing apparatus that overcomes all of the drawbacks of the prior art. That is, the present invention allows a large number of test samples existing on the same wafer w!
Can you select and test multiple elements at the same time and mark the failed test elements? The present invention relates to a semiconductor integrated circuit trial employment device for the purpose of conducting testing.

For such tests, an IC tester that handles the test function and a wafer that handles the wafer under test are required.
10 - out of bar and the device under test.

A semiconductor integrated circuit testing device is used that is combined with a marker to mark those that have failed the test, but the electrical connection and mechanical alignment between the wafer prober and the marker are usually 1. .

Each time the type of wafer to be tested is changed, nine manual steps are required (tt6), so human errors are likely to occur, and conventional semiconductor integrated circuit testing cannot detect the above-mentioned mistakes, so in the unlikely event that a mistake occurs, In addition to completely destroying a large number of devices under test, the device under test must be retested (usually,
Is there a huge loss because it is not possible to know exactly when a mistake has occurred because it is done after mounting it in a case, etc.? Kayane〈It will be a result.

The fourth feature of the present invention is an IC tester that can simultaneously test two or more test elements existing on the same wafer, and an IC tester that can simultaneously test two or more test elements on the same wafer, and multiple markers to mark the
If the result of this test is a mixture of pass and fail, this test result will be temporarily memorized and 1
The semiconductor integrated circuit testing apparatus also includes means for stopping the operation of the IC tester when the test results are unsatisfactory.

Hereinafter, one embodiment of the present invention Q will be described using one drawing.

Figure 2 shows the first step 11 of the present invention, and in Figure 2, 1~3+11+12T21~24,31
ν32 is the same component as in FIG. The basic operational relationship of the example shown in FIG. 2 is the same as that of the conventional example shown in FIG. 31+32
6 tests are carried out, and the results and test completion signals for each are sent to the first and second markers 22 and 23 via the 10-bar control circuit 21.

Mark the failed IJU '1'. Note 1
The tester city 1] control circuit outputs the signal from the tester circuit 25.
If the judgment result for the second "U'L' 31.32 is only a pass or a failure, the prober 1lffI control circuit 21 prohibits it.
Wafer-cry I through 1st route 26! Iit control circuit 24
Prohibition circuit 2 so as not to prohibit the movement instruction signal supplied to
6. If the judgment result is a mixed state of pass and fail, the prohibition IE circuit 26 is instructed to prohibit the transfer of the wafer 3, and the judgment result is temporarily stored. In this case as well, marking is performed as usual, and the prober control circuit 21 generates all test start signals, so the Ic tester l tests the same first and second LILJ'l'31°32 as before and sends out the judgment results. Therefore, this judgment result is compared in the memory judgment circuit 25 with the previous judgment result which has been temporarily stored. If the results match, the inhibition t- of the inhibition circuit 26 is canceled.

Wafer 3 is moved to 4 by allowing the movement instruction signal to pass through.
1 to make it possible to perform the 1st-order 'JUT31+32 test, but if they do not match (for example, if a non-defective LlUT is marked, it will be a mismatch: an alarm etc. will be generated while all Fi moving parts are correct).

In this way, it is possible to automatically and reliably detect marker setting errors that could cause great damage to the present invention.

It should be noted that the operation of the memory determination circuit 1825 need not be constant, but may be performed according to preset conditions (for example, immediately after switching the product type). or.

In the above explanation, 11 U 'l' are tested simultaneously.
Individual.

We have explained the case where there are two markers, but if this is 3
The same applies to cases of more than one. Also, tester.

If the prober has a function of counting measurement results, it goes without saying that this counting function must be fully turned on when re-measuring according to instructions from the storage determination circuit.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a conventional semiconductor integrated circuit testing device, I! FIG. 2 is a block circuit diagram of an embodiment according to the present invention. In the figure, 1...IC tester, 2...
...Wafer blooper, 3...Wafer under test-111...Measurement circuit, 12...
-Tester control circuit, 21...Wafer-prober control circuit, 22...First marker, 2
3... Second marker 124... Wafer position control circuit, 25... Memory determination circuit,
2.6... Prohibited circuit, 31... First device under test Figure 1 t Z diagram

Claims (1)

[Claims] An A'Q IC tester capable of simultaneously testing two or more devices under test on the same wafer. The result of test 4 by the 1c tester was a failure. 7'i: If the test subject's bond was a mixture of successful and unsuccessful results, the 1st revised examination book was temporarily memorized and the previous Have the dpi IU tester perform all the tests again, and if the results from the test store and the test results do not match, the IC
Please use the means to stop the operation of the tester!
Semiconductor integrated circuit testing equipment with # characteristics.