JPS63292639A - Apparatus for measuring and inspecting semiconductor integrated circuit device - Google Patents

Apparatus for measuring and inspecting semiconductor integrated circuit device

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Publication number
JPS63292639A
JPS63292639A JP12895887A JP12895887A JPS63292639A JP S63292639 A JPS63292639 A JP S63292639A JP 12895887 A JP12895887 A JP 12895887A JP 12895887 A JP12895887 A JP 12895887A JP S63292639 A JPS63292639 A JP S63292639A
Authority
JP
Japan
Prior art keywords
marking
chip
wafer
measurement
control mechanism
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12895887A
Other languages
Japanese (ja)
Inventor
Masaru Yamamoto
勝 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12895887A priority Critical patent/JPS63292639A/en
Publication of JPS63292639A publication Critical patent/JPS63292639A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To perform marking based on only one measurement without manipulating the control programs of hardware and a measuring device, in a full- automatic wafer prober, which inspects a semiconductor integrated circuit device in a wafer state, by storing the measured data, which are obtained for every chip, together with the position data of said chip, and generating signals, which are required for marking, with a marking control mechanism. CONSTITUTION:The interface part of a measuring apparatus is made to act as an interface for the measured result of each chip between a measuring device 10 and a full automatic wafer prober 100. The measured result from the interface 101 and the position data of said chip are stored in a storage mechanism 102. An operator inputs marking conditions with a marking condition input mechanism 104 based on the stored measured result. A marking signal control mechanism 105 reads the measured result and the position data for every chip from the storage mechanism 102. A marking signal 301 is inputted into a marking mechanism 106, and a marking position signal 302 is inputted into a wafer position control mechanism 107. Marking is performed on each chip on a wafer 20 with the marking mechanism.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置の測定・検査装置に関し、
特にフルオートウェハプローバのマーキングの方式に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a measurement and inspection device for semiconductor integrated circuit devices.
In particular, it relates to a marking method for a fully automatic wafer prober.

〔従来の技術〕[Conventional technology]

従来、この種のマーキング装置は、ウェハ搬送機構10
9によりウェハ20を搬入し、アライメント機構108
の指令でウェハ位置制御機構107に基づいてそのウェ
ハ20を位置決めし、位置決めされたウェハ20を測定
装置10で測定し、その不良信号305を測定装置イン
ターフェイス101を介してマーキング機構106に入
力させ、該マーキング機構106によりウェハ20上の
チップの一部に不良マークを刻印させていた。110は
上記各機器の駆動制御を行う中央制御機構である。
Conventionally, this type of marking device has a wafer transport mechanism 10.
9, the wafer 20 is carried in, and the alignment mechanism 108
The wafer 20 is positioned based on the wafer position control mechanism 107 according to the command, the positioned wafer 20 is measured by the measuring device 10, and the defect signal 305 is inputted to the marking mechanism 106 via the measuring device interface 101. The marking mechanism 106 imprints a defective mark on a part of the chips on the wafer 20. 110 is a central control mechanism that controls the drive of each of the above-mentioned devices.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した第2図に示す従来のマーキング装置では、ウェ
ハ20上の各チップに対するマーキングは被試験ウェハ
により予め設定された条件に基づき測定とマーキングと
同時に行っていたため、製造工程上の異常や、回路設計
上のミス等によるウェハの異常、測定系の異常や、探針
とチップ上のパラドどのコンタクト不良、測定装置の操
作ミス等の異常が発生した場合、全てのチップに対して
マーキングを行うことになり、再測定や不良解析ができ
ないという欠点があった。
In the conventional marking apparatus shown in FIG. 2 described above, marking of each chip on the wafer 20 was performed simultaneously with measurement and marking based on conditions preset by the wafer under test, so there was no possibility of abnormalities in the manufacturing process or circuitry. In the event that an abnormality occurs in the wafer due to a design error, an abnormality in the measurement system, a contact failure between the probe and the pad on the chip, an operational error in the measurement equipment, etc., all chips must be marked. The disadvantage was that re-measurement and failure analysis were not possible.

そこで、第3図に示すように記憶機構102を装備し、
測定結果を一旦記憶機構102に記憶させた後に、一括
してマーキングを行う方式が考案されている。105は
マーキング信号制御機構である。
Therefore, as shown in FIG. 3, a storage mechanism 102 is installed,
A method has been devised in which the measurement results are once stored in the storage mechanism 102 and then marked all at once. 105 is a marking signal control mechanism.

この方式では、試作品の初めての測定や、良品チップを
能力階層別にカウントし、その個数によりどの階層まで
を良品とするかを決定する方法を取ろうとし場合等のよ
うに一度測定を行わなければマーキングの条件が決定で
きない場合には2回以」1の測定を行わなければならな
かった。これらの場合には、各チップのパッドに探針を
当てる回数が増すことになり、チップのパッドとに損傷
を与え、ひいては組み立て時の歩留りを低下させるとい
う欠点を有した。
This method requires measurement only once, such as when measuring a prototype for the first time, or when trying to count non-defective chips by capability level and decide which level up to which level is considered good based on the number of chips. For example, if the marking conditions could not be determined, measurements had to be carried out two or more times. In these cases, the number of times the probe is applied to the pads of each chip increases, resulting in damage to the pads of the chips, which has the disadvantage of lowering the yield during assembly.

本発明の目的は前記問題点を解消した測定・検査装置を
提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a measurement/inspection device that eliminates the above-mentioned problems.

=3− 〔発明の従来技術に対する相違点〕 に述した従来のマーキング方式に対し、本発明は任意の
条件の下に1回の測定のみで、ハードウェア及び測定装
置の制御プログラムに手を加えることなくウェハ上のチ
ップにマーキングを行うという独創的内容を有する。
=3- [Differences between the invention and the prior art] In contrast to the conventional marking method described above, the present invention makes it possible to modify the hardware and the control program of the measuring device by performing only one measurement under arbitrary conditions. It has an original content of marking chips on a wafer without any marking.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は半導体集積回路装置をウェハ状態で検査するフ
ルオー1−ウェハプローバにおいて、各チップ毎に得ら
れる測定データをそのチップの位置情報とともに記憶さ
せる記憶機構と、該記憶機構に記憶されたS定結果をモ
ニタさせる記録表示機構と、該記憶機構に記憶されてい
るデータ若しくは1チップ測定毎に測定装置より送られ
てくるデータに基づき、マーキング機構によるマーキン
グの実施に必要な信号を発生させるマーキング信号制御
機構と、該マーキング信号制御機構にマーキング条件を
設定するマーキング条件入力機構とを有することを特徴
とする半導体集積回路装置の測定・検査装置である。
The present invention provides a Fluoro 1-wafer prober for testing semiconductor integrated circuit devices in a wafer state, including a memory mechanism for storing measurement data obtained for each chip together with positional information of the chip, and an S constant stored in the memory mechanism. A recording/displaying mechanism for monitoring results, and a marking signal for generating signals necessary for marking by the marking mechanism based on the data stored in the storage mechanism or the data sent from the measuring device every time one chip is measured. This is a measurement/inspection device for semiconductor integrated circuit devices characterized by having a control mechanism and a marking condition input mechanism for setting marking conditions in the marking signal control mechanism.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明のマーキング装置を有するフルオートウ
ェハブローバの構成である。101は測定装置インター
フェイスであり、測定装置10とフルオーl〜ウェハプ
ローバ100との間で各チップごとの4111定結果3
00をインターフェイスする機構である。]02は記憶
機構であり、インターフェイス101からの測定結果3
00とそのチップの位置情報とを合せて記憶する機構で
ある。103は記憶機構102に記憶されたデータをオ
ペレータ200に表示する表示機構であり、表示された
測定結果に基づきオペレータ200はマーキング条件の
入力405をマーキング条件入力機構104より行う。
FIG. 1 shows the configuration of a fully automatic wafer blobber having a marking device according to the present invention. Reference numeral 101 denotes a measuring device interface, which provides 4111 constant results 3 for each chip between the measuring device 10 and the fluoro-wafer prober 100.
This is a mechanism for interfacing 00. ]02 is a storage mechanism, and measurement result 3 from the interface 101
This is a mechanism that stores 00 and the position information of the chip together. A display mechanism 103 displays data stored in the storage mechanism 102 to the operator 200, and based on the displayed measurement results, the operator 200 inputs marking conditions 405 through the marking condition input mechanism 104.

105はマーキング信号制御機構であり、記憶機構10
2より各チップごとの測定結果及び位置情報303を読
み出しマーキング機構106にマーキング信号301を
、またウェハ位置制御機構107にマーキング位置信号
302とをそれぞれ入力させる。106はマーキング機
構であり、ウェハ20上の各チップに対してマーキング
を行う機構である。
105 is a marking signal control mechanism, and a storage mechanism 10
2, the measurement results and position information 303 for each chip are read out, and the marking signal 301 is input to the marking mechanism 106, and the marking position signal 302 is input to the wafer position control mechanism 107, respectively. A marking mechanism 106 is a mechanism for marking each chip on the wafer 20.

107はウェハ位置制御機構であり、測定及びマーキン
グを行う際にウェハ20を正確に移動させる機構である
A wafer position control mechanism 107 is a mechanism for accurately moving the wafer 20 during measurement and marking.

108はアライメント機構であり、測定若しくは÷−キ
ング前にウェハの位置を基準位置に合せる機構である。
Reference numeral 108 denotes an alignment mechanism, which aligns the position of the wafer with the reference position before measurement or ÷-king.

109はウェハの搬送機構であり、測定及びマーキング
を終えたウェハを格納し、未測定若しくは未マーキング
のウェハをウェハ位置制御機構107にセットする機構
である。
Reference numeral 109 denotes a wafer transport mechanism, which stores wafers that have been measured and marked, and sets unmeasured or unmarked wafers in the wafer position control mechanism 107.

110はこれらの機構を統括制御する中央制御機構であ
る。
110 is a central control mechanism that centrally controls these mechanisms.

また、1は各チップの測定結果を記憶機構102にて1
ウ工ハ分記憶する方式の信号の流れであり、上記の動作
を行う。
1 stores the measurement results of each chip in the storage mechanism 102.
This is the signal flow of the method that stores the number of minutes, and the above operation is performed.

2は、1チップ測定ごとにマーキングを行う方式の信号
の流れであり、マーキングの条件はマーキング条件入力
機構104により測定前に設定を行い、マーキング信号
制御機構105にてマーキング信号をマーキング機構1
06に向けて発生する。
2 is a signal flow for a method in which marking is performed for each chip measured; the marking conditions are set before measurement using the marking condition input mechanism 104, and the marking signal is sent to the marking mechanism 1 using the marking signal control mechanism 105.
Occurs towards 06.

すなわち、本発明は記録表示機構103.マーキング条
件入力機構104を設け、記憶機構102に記憶された
測定結果に応じてマーキングすべき項目を決定するため
に表示機構103にてモニタし入力機構104より必要
に応じてマーキングすべき測定項目を入力する。また複
数の項目によりマーキングする場合には、各項目のAN
DやOR等の論理をマーキング信号制御機構105にて
とりマーキング信号の制御を行う。
That is, the present invention provides the recording and display mechanism 103. A marking condition input mechanism 104 is provided, and in order to determine items to be marked according to the measurement results stored in the storage mechanism 102, the display mechanism 103 monitors the items, and the input mechanism 104 selects measurement items to be marked as necessary. input. In addition, when marking with multiple items, the AN of each item
The marking signal control mechanism 105 uses logic such as D and OR to control the marking signal.

また、予めマーキング条件が決定されており、その条件
と測定装置の制御用プログラムにより出力されるマーキ
ング信号が異なる場合は、記憶機構102に一旦記憶せ
ずに直接マーキング信号制御機構105に測定結果を入
力し、マーキング条件入力機構104より入力された条
件によりマーキング信号を発生する。
Furthermore, if the marking conditions are determined in advance and the marking signals output by the control program of the measuring device are different from those conditions, the measurement results are directly sent to the marking signal control mechanism 105 without being stored in the storage mechanism 102. A marking signal is generated according to the conditions input from the marking condition input mechanism 104.

本発明によるマーキング方式の使用例としては、試作品
の測定において、一度1ウェハ上の全チップを測定した
後、その結果によりマーキング項目を決定する場合や、
量産において1ウエハ上の全チップを測定した後、その
ウェハの水準によって良品の水準を決定する場合に有効
である。
An example of the use of the marking method according to the present invention is when all chips on one wafer are measured once in the measurement of a prototype, and marking items are determined based on the results.
This is effective when determining the level of non-defective products based on the level of the wafer after measuring all chips on one wafer in mass production.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、測定装置よりフルオート
ウェハプローバに対して送られる各チップの全ての測定
結果をデータを1ウ工ハ分記憶することにより、若しく
はハードウェア的にマーキング信号を固定せずに、測定
結果によりマーキング信号を発生することにより、1回
の測定のみで任意の条件にてハードウェア及び測定装置
の制御プログラムに手を加えることなく、ウェハ上のチ
ップに対してマーキングを行うことができるという効果
がある。
As explained above, the present invention stores all the measurement results of each chip sent from the measurement device to the fully automatic wafer prober for one process, or fixes the marking signal using hardware. By generating a marking signal based on the measurement result without having to manually mark the chips on the wafer, it is possible to mark the chips on the wafer under any conditions with just one measurement without having to modify the hardware or the control program of the measurement device. The effect is that it can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す構成図、第2図、第3
図は従来例を示す構成図である。 102・・・記憶機構     103・・・記録表示
機構104・・・マーキング条件入力機構  105・
・・マーキング信号制御機構106・・・マーキング機
Fig. 1 is a configuration diagram showing one embodiment of the present invention, Fig. 2, Fig. 3
The figure is a configuration diagram showing a conventional example. 102... Storage mechanism 103... Record display mechanism 104... Marking condition input mechanism 105.
...Marking signal control mechanism 106...Marking mechanism

Claims (1)

【特許請求の範囲】[Claims] (1)半導体集積回路装置をウェハ状態で検査するフル
オートウェハプローバにおいて、各チップ毎に得られる
測定データをそのチップの位置情報とともに記憶させる
記憶機構と、該記憶機構に記憶された測定結果をモニタ
させる記録表示機構と、該記憶機構に記憶されているデ
ータ若しくは1チップ測定毎に測定装置より送られてく
るデータに基づき、マーキング機構によるマーキングの
実施に必要な信号を発生させるマーキング信号制御機構
と、該マーキング信号制御機構にマーキング条件を設定
するマーキング条件入力機構とを有することを特徴とす
る半導体集積回路装置の測定・検査装置。
(1) A fully automatic wafer prober that inspects semiconductor integrated circuit devices in the wafer state includes a storage mechanism that stores measurement data obtained for each chip together with the position information of that chip, and a storage mechanism that stores measurement results stored in the storage mechanism. A recording display mechanism for monitoring, and a marking signal control mechanism for generating signals necessary for marking by the marking mechanism based on the data stored in the storage mechanism or data sent from the measuring device every time one chip is measured. and a marking condition input mechanism for setting marking conditions in the marking signal control mechanism.
JP12895887A 1987-05-26 1987-05-26 Apparatus for measuring and inspecting semiconductor integrated circuit device Pending JPS63292639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12895887A JPS63292639A (en) 1987-05-26 1987-05-26 Apparatus for measuring and inspecting semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12895887A JPS63292639A (en) 1987-05-26 1987-05-26 Apparatus for measuring and inspecting semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS63292639A true JPS63292639A (en) 1988-11-29

Family

ID=14997619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12895887A Pending JPS63292639A (en) 1987-05-26 1987-05-26 Apparatus for measuring and inspecting semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63292639A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086270A (en) * 1988-07-08 1992-02-04 Tokyo Electron Limited Probe apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086270A (en) * 1988-07-08 1992-02-04 Tokyo Electron Limited Probe apparatus

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