JPS63250505A - Wiring pattern inspection device - Google Patents
Wiring pattern inspection deviceInfo
- Publication number
- JPS63250505A JPS63250505A JP8610887A JP8610887A JPS63250505A JP S63250505 A JPS63250505 A JP S63250505A JP 8610887 A JP8610887 A JP 8610887A JP 8610887 A JP8610887 A JP 8610887A JP S63250505 A JPS63250505 A JP S63250505A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- wafer
- inspected
- data
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 title claims description 11
- 230000003287 optical effect Effects 0.000 claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 11
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はLSIテストVC際して自動的に配線パター
ン欠陥を検出する配線パターン検査装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring pattern inspection device that automatically detects wiring pattern defects during LSI test VC.
第2図はLSIのテストの際に使われる検査装置の一例
を示し、図において、(1)は被測定素子、(2)はこ
の被測定素子を測定するために必安な外付回路をプリン
ト基板上に作成したパーフオマンスボード、+31fl
前記の被測定素子(1)にバーフオマンスボード(2)
を通して命令を入力したり、被測定素子fi+より出力
された信号より、被測定素子が正確に動作しているかを
判定する中央演算処理装!(以下CPUと記す)、f4
tはこのCPU +31を外部よりコントロールするた
めのキーボード、(61は前記CPU (31の判定を
出力する等の働きをするCRT 、 (61Itsテス
トプログラムを記憶する記憶手段である。Figure 2 shows an example of an inspection device used in LSI testing. In the figure, (1) is the device under test, and (2) is the external circuit that is necessary to measure the device under test. Performance board made on printed circuit board, +31fl
A barf resistance board (2) is attached to the above-mentioned device under test (1).
A central processing unit that determines whether the device under test is operating accurately based on the signals output from the device under test fi+ by inputting commands through the central processing unit! (hereinafter referred to as CPU), f4
t is a keyboard for controlling this CPU +31 from the outside, (61 is a CRT that functions to output the judgment of the CPU (31), and (61 Its storage means for storing the test program).
被測定素子(1)の種類に合わせて作成したテストプロ
グラムを、記憶手段(6)より(PtJ (3)に入力
し、第2図に示すような検査装置で動作に誤りがないか
を検査する◇
例えば、CPU +31より被測定素子(1)ヘパーフ
オマンスポード(2)を通しである命令を実行するよう
な信号を入力し、CPtJ(31がこの命令が実行され
たことを被測定素子f11より出力された信号から判断
し、良品であるかどうかを判定する。A test program created according to the type of device to be measured (1) is input into the (PtJ (3)) from the storage means (6), and inspected for errors in operation using an inspection device as shown in Figure 2. ◇ For example, a signal to execute a certain command is input from the CPU +31 through the device under test (1) and the performance port (2), and the CPtJ (31) sends a signal to the device under test that this command has been executed. Judging from the signal output from f11, it is determined whether the product is good or not.
例えばメモリー内戚のマイコンの検査に際しである命令
をX行した時、ウェハプロセスによるパターンの欠陥に
より全く関係のないメモリの内容が変化したかどうかの
確認する必要がある。この場合、テストプログラムを作
成し、これにより前記確認を行なう。このようなテスト
プログラムを作成するVci、多くの時間と労力を必要
とする。For example, when inspecting a microcomputer in a memory, it is necessary to check whether completely unrelated memory contents have changed when a certain instruction is executed in X rows due to pattern defects caused by wafer processing. In this case, a test program is created to perform the above-mentioned confirmation. Creating such a test program requires a lot of time and effort.
また、テストプログラムが長くなると、LSIの開発工
期も長くなるという間萌もある。Another problem is that the longer the test program, the longer the LSI development period.
この発明は前記のような問題点を解消するためになされ
たもので、迅速に自動的に配線パターンの欠陥を検出す
ることができる検査装置を得′ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an inspection device that can quickly and automatically detect defects in wiring patterns.
〔問題点を解決するための手段〕
この発明に係る検査装置は、記憶手段に予め基準となる
良品のウェハ表面の配線パターンのデータを記憶してお
き、この配線パターンと検査されるウェハ表面の配線パ
ターンとをCPUで比較し、チップの配線パターンに異
なる置所がないかを検査するものである。[Means for Solving the Problems] The inspection apparatus according to the present invention stores data of a wiring pattern on the surface of a non-defective wafer as a reference in advance in the storage means, and compares this wiring pattern with the surface of the wafer to be inspected. The chip is compared with the wiring pattern by the CPU to check whether there are any different locations in the wiring pattern of the chip.
この発明におけるcpuと記憶手段とで構成した装j逐
は、予め記憶しておいた基準となる良品のウェハ表面の
配線パターンのデータと、検査するウェハ表面の配線パ
ターンのデータを自動的に比較することにより、テスト
プログラムを作成することなくテストを実施することが
できる。The device according to the present invention, which is composed of a CPU and a storage means, automatically compares the data of the wiring pattern on the surface of the wafer to be inspected with the data of the wiring pattern on the surface of the wafer to be inspected, which is a standard stored in advance. By doing so, tests can be performed without creating a test program.
以下、この発明の一実施例を図に従って説明する。第1
図において、(7)は検査されるべきウェハであり、予
め所望の配線パターン(図示しない)が形成されている
。(81ハこのウェハ(7)が載せらn。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (7) is a wafer to be inspected, on which a desired wiring pattern (not shown) has been formed in advance. (This wafer (7) is placed on the wafer 81.)
るステージ、191Uウエハ())の表面の配線パター
ンを光学的に読み取る光学的読み取り手段、1101
fi光学的読み取り手段(9)より得た像を電気信号に
変換する電気イa号変換手段、(6)は基準となる良品
の配線パターンを記憶するための記憶手段、(3’+は
電気信号変換手段(101から出力される配線パターン
のデータと記憶手段(61に記憶された配馴パターンの
データを比較し、良品を判別するcpuである。stage, optical reading means for optically reading the wiring pattern on the surface of the 191U wafer (), 1101
fi electrical conversion means for converting the image obtained from the optical reading means (9) into an electrical signal; It is a CPU that compares the wiring pattern data outputted from the signal conversion means (101) and the distribution pattern data stored in the storage means (61) to determine good products.
検査すべきウェハ(7)をステージ(8)上に載せ、と
のウェハ(7)表面の配線パターンを光学的読み取り手
段(9)により読み取る。この光学的読み取り手段(9
)より得た像のデータを電気信号変換手段(lO)によ
り電気信号に変換して、CPU (31に送り込む。こ
の。A wafer (7) to be inspected is placed on a stage (8), and the wiring pattern on the surface of the wafer (7) is read by an optical reading means (9). This optical reading means (9
) is converted into an electric signal by the electric signal converting means (lO) and sent to the CPU (31).
電気信号と、記憶装置(6)内に予め記憶された基準と
なる良品のウェハ表面の配線パターンのデータをCPU
f61で自動的に比較し、良否を判別する。The electrical signal and data of the wiring pattern on the surface of a good wafer, which serves as a reference and is stored in advance in the storage device (6), are sent to the CPU.
F61 automatically compares and determines whether it is good or bad.
なお、前日己医施例ではウェハ(7)上の配線パターン
の検査について説明したが、チップの検査にも適用する
ことができる。In addition, in the previous medical example, the inspection of the wiring pattern on the wafer (7) was explained, but it can also be applied to the inspection of chips.
以上のように、この発明によれば、記憶手段に予め基準
となる良品のウェハ表面の配線パターンのデータを記憶
しておき、この配線パターンと、検査されるウェハ表面
の配線パターンとをCPUで比較し、チップの配線パタ
ーンに異なる箇所がないかを検査するので、開発工期が
短縮でき、品質も向上することができる〇As described above, according to the present invention, data of the wiring pattern on the surface of a non-defective wafer serving as a reference is stored in advance in the storage means, and this wiring pattern and the wiring pattern on the surface of the wafer to be inspected are stored in the CPU. By comparing and inspecting whether there are any differences in the wiring pattern of the chip, development time can be shortened and quality can be improved.
第1図はこの発明の一実施例による検査装置の構造図、
第2図は従来の検査装置の構造図である。
fllU被測定素子、(2)はバー7オマンスボード、
(3)は中央OIL、、JiE処理装置、(4)はキー
ボード、(6)はCRT、161は記憶手段、(7)は
ウェハ、(8)はステージ、(9)は光学的読み取り手
段、(Lotは電気係号変換手段である。
なお、各図中、同一符号に同一または相当部分を示す。FIG. 1 is a structural diagram of an inspection device according to an embodiment of the present invention;
FIG. 2 is a structural diagram of a conventional inspection device. fllU device under test, (2) is Bar 7 Omance board,
(3) is a central OIL, JiE processing device, (4) is a keyboard, (6) is a CRT, 161 is a storage means, (7) is a wafer, (8) is a stage, (9) is an optical reading means, (Lot is an electrical code conversion means. In each figure, the same reference numerals indicate the same or equivalent parts.
Claims (1)
置の配線パターンを読み取る光学的読み取り手段と、こ
の光学的読み取り手段から読み取られた配線パターンを
電気信号に変換する信号変換手段と、この信号変換手段
から前記配線パターンの信号が入力され、この信号と、
前記記憶手段に記憶された配線パターンとを比較し、差
異の有無を判断する演算手段とを有した配線パターン検
査装置。A storage means for storing a reference wiring pattern, an optical reading means for reading the wiring pattern of a semiconductor device, a signal conversion means for converting the wiring pattern read from the optical reading means into an electrical signal, and the signal conversion means The signal of the wiring pattern is inputted from, and this signal and
A wiring pattern inspection device comprising a calculation means for comparing the wiring pattern stored in the storage means and determining the presence or absence of a difference.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8610887A JPS63250505A (en) | 1987-04-07 | 1987-04-07 | Wiring pattern inspection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8610887A JPS63250505A (en) | 1987-04-07 | 1987-04-07 | Wiring pattern inspection device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63250505A true JPS63250505A (en) | 1988-10-18 |
Family
ID=13877507
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8610887A Pending JPS63250505A (en) | 1987-04-07 | 1987-04-07 | Wiring pattern inspection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63250505A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5820693A (en) * | 1994-01-27 | 1998-10-13 | Patchett; Joseph A. | Process for recovering catalysts supports |
-
1987
- 1987-04-07 JP JP8610887A patent/JPS63250505A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5820693A (en) * | 1994-01-27 | 1998-10-13 | Patchett; Joseph A. | Process for recovering catalysts supports |
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