JPH07154143A - Oscillating circuit - Google Patents

Abstract

PURPOSE:To reduce a current consumption by selecting through switchover an amplifier A or B with a high/low oscillation start voltage and less/much current consumption being a component of an oscillation circuit according to the case when at the time of oscillation start and at the time of a predetermined amplitude or over. CONSTITUTION:An amplitude detection circuit 1 provides an output of a low/ high level (L/H) over/below a predetermined oscillation output amplitude, resulting that a 2-input NAND gate ND1 provides an output of H/L. Thus, transistors(TRs) 0, 3 turned off/on and TRs 4, 6 are turned on/off and power of a CMOS inverter comprising TRs 1, 2 is turned off/on. Then an amplifier comprising a load resistor R0 and a TR 5 is operated with much current but a low voltage just after application of power and a CMOS inverter is operated with a high voltage and a low current after a predetermined time switchingly as an oscillation circuit. Thus, the oscillation start voltage is decreased and current consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit, and more particularly to an oscillator circuit that oscillates at a low voltage to reduce current consumption.

[0002]

2. Description of the Related Art As an oscillator circuit for reducing current consumption,
For example, Japanese Patent Laid-Open No. 163902/1993 proposes an oscillator circuit shown in FIG. In the figure, Rf1 is a feedback resistance, Rd0 and Rd1 are damping resistances, and T
r7 is a switching MOS transistor for switching the damping resistance value (abbreviated as “switch”), CNT is a control signal of the switch Tr7, X1 is a mechanical oscillator,
IV3 is a CMOS inverter as a driving means for applying a voltage between both terminals of the mechanical oscillator X1, and CP2 and CP3 are external capacitors.

In this oscillation circuit, the switch Tr7 is turned off by the control signal CNT when the power is turned on, and the damping resistor Rd1 shifts the phase between points A and B to facilitate oscillation, and a mechanical oscillator when the power is turned on. It acts to suppress the transient current to X1. Then, when a certain period of time elapses after the power is turned on and the oscillation grows, the control signal CNT
Turns on the switch Tr7, connects the damping resistor Rd0, and the resistance values of the node A and the node B are from Rd1 to Rd.
It is reduced to 0 * Rd1 / (Rd0 + Rd1), and therefore the current consumption of the oscillation circuit can be suppressed.

Another example of a conventional oscillator circuit is shown in FIG. In the figure, Rf2 is a feedback resistor, R1 is a load resistor, Tr8 is an N-channel MOS transistor, X2 is a mechanical oscillator, and CP4 and CP5 are external capacitors. This oscillator circuit uses an amplifier circuit instead of a CMOS inverter.
It is composed of a load resistor R1 and an N-channel MOS transistor Tr8.

When the amplifier circuit is composed of a CMOS inverter, the oscillation start voltage of the oscillator circuit is the sum (= V _TEN +) of the threshold voltages of the N-channel MOS transistor and the P-channel MOS transistor (both enhancement types) forming the inverter. It is known that the voltage becomes about | V _TEP |).

On the other hand, when the amplifier circuit having the structure shown in FIG. 4 is used, the oscillation start voltage of the oscillator circuit is the threshold voltage V of the enhancement type N-channel MOS transistor.
It is known that it is about the sum of the voltage drops of _TEN and the load resistance R1. Therefore, the amplifier circuit of FIG.
It is possible to obtain an oscillation starting voltage lower than that in the case of using a MOS inverter.

[0007]

Recently, the operating voltage (power supply voltage) of LSIs (large-scale integrated circuits), especially single-chip microcomputers, is becoming lower, and the current consumption is being further reduced. I'm out. In the following, the problems of the conventional oscillation circuit will be examined from the aspects of both low voltage and low current consumption.

According to the configuration of the conventional oscillator circuit shown in FIG. 3, the current consumption of the oscillator circuit can be reduced. However, in the conventional example of FIG. 3, as described above, the oscillation start voltage is about the sum of the threshold voltages of the P-channel and N-channel MOS transistors forming the CMOS inverter (amplifier), and therefore, the conventional example of FIG. In the example, there is a limit of the threshold voltage of the MOS transistor for lowering the oscillation start voltage.

Further, according to the conventional example shown in FIG. 4, the amplifier includes an N-channel MOS transistor Tr8 and a load resistor R1.
With this configuration, the oscillation start voltage of the oscillation circuit is the threshold voltage of the N-channel MOS transistor and the load resistance R.
It is about the sum of the voltage drops of 1. Therefore, this oscillation circuit can shift the oscillation start voltage to the low voltage side by lowering the resistance value of the load resistor R1.

However, in the oscillator circuit of FIG.
When the S-transistor Tr8 is in the ON state, the power sources are energized via the load resistor R1. At this time, the current I1 flowing through the load resistor R1 has a power source voltage VDD and a resistance value of the on-resistance of the MOS transistor Tr8. Ro
I1 = VDD / (R1 + Ro). Therefore, if the resistance value of the load resistor R1 is reduced in order to reduce the oscillation start voltage of the oscillation circuit, there is a problem that the current increases.

Therefore, an object of the present invention is to provide an oscillation circuit for lowering the oscillation starting voltage and reducing the current consumption.

[0012]

In order to achieve the above object, the present invention provides an oscillator circuit including a mechanical oscillator and a drive circuit for applying a voltage to the mechanical oscillator. The circuit includes a plurality of inverters connected in parallel with each other, a feedback resistor having one end connected to a common connection point of input terminals of the plurality of inverters and the other end connected to a common connection point of output terminals of the plurality of inverters. And an switching circuit configured to switch the plurality of inverters depending on the value of the voltage amplitude of the oscillation circuit.

In the present invention, the switching means detects the amplitude of the output voltage of the oscillation circuit, an amplitude detection circuit, a latch circuit that captures and holds the output of the amplitude detection circuit, and an output of the latch circuit. Based on the above, there is provided an oscillating circuit comprising: a switch circuit that interrupts or conducts a current path of the plurality of inverters between a power supply wiring and a ground wiring.

Further, in the present invention, the plurality of inverters include an inverter having a low oscillation start voltage and an inverter having a low power consumption.

[0015]

SUMMARY OF THE INVENTION An oscillator circuit according to the present invention is provided with a plurality of amplifiers, and these amplifiers have different oscillation starting voltages, and at least one of the plurality of amplifiers is a first inverter composed of a CMOS inverter and a feedback resistor. It is an amplifier. The plurality of amplifiers include a second amplifier that consumes more current but has a lower oscillation starting voltage than the first amplifier when the oscillation circuit is configured.

At the start of oscillation immediately after the power is turned on, an oscillation circuit is configured by using a second amplifier that consumes a large amount of current but has a low oscillation starting voltage, and the output of the oscillation circuit is input to an amplitude detection circuit to monitor the amplitude. Then, after the amplitude exceeds a certain value, the switch is switched, and the current consumption is suppressed by configuring the oscillation circuit using the first amplifier that consumes less current. With this method, the oscillation start voltage can be lowered and the current consumption can be reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

[0018]

[Embodiment 1] FIG. 1 shows a circuit configuration of a first embodiment of the present invention. In FIG. 1, CP0 and CP1 are external capacitors,
The amplitude detection circuit 1 is a detection circuit that changes the output signal from a low level to a high level when the amplitude width of the oscillation stage exceeds a certain value, ND0 and ND1 are 2-input NAND gates,
IV0, IV1, IV2 are inverter gates, Rf0 is a feedback resistor, X0 is a mechanical oscillator, Tr0, T
r1 and Tr4 are P-channel MOS transistors, Tr
2, Tr3, Tr5, Tr6 are N-channel MOS transistors, and R0 is a load resistor.

P-channel MOS transistors Tr1 and N
The CMOS inverter composed of the channel MOS transistor Tr2 and the amplifier composed of the load resistor R0 and the N-channel MOS transistor Tr5 are driving means for applying a voltage between both terminals of the mechanical oscillator X0.

Further, the MOS transistors Tr0, Tr
3 and Tr4 and Tr6 constitute a switch for switching the amplifier.

The 2-input NAND gates ND0 and ND1 are
Configure set / reset latch (S / R latch),
When the output of the amplitude detection circuit 1 is low level, the output of the S / R latch is set to high level, and when the output of the amplitude detection circuit 1 becomes high level, the output of the S / R latch is reset to low level.

Next, the operating principle of this embodiment will be described. Immediately after the power is turned on, the amplitude detection circuit 1 outputs a low level. As a result, the output of the 2-input NAND gate ND1 becomes high level, the MOS transistors Tr0 and Tr3 are turned off, and the transistors Tr4 and Tr6 are turned on. Therefore, MO
The CMOS inverter composed of the S transistors Tr1 and Tr2 is electrically separated from the power supply, and the amplifier composed of the load resistor R0 and the MOS transistor Tr5 is selected.
It operates as an oscillation circuit with a low oscillation start voltage to start oscillation.

After a certain time has passed, the amplitude detection circuit 1 detects that the amplitude has reached a certain value or more, and the amplitude detection circuit 1
When the output of is changed from low level to high level, 2 inputs N
The output of the AND gate ND1 becomes low level, and the MOS
The transistors Tr0 and Tr3 are turned on, and the MOS transistors Tr4 and Tr6 are turned off. Therefore, the amplifier composed of the load resistor R0 and the MOS transistor Tr5 is electrically disconnected from between the power supplies, and instead of this, the MO
CMO composed of S transistors Tr1 and Tr2
The S inverter is electrically connected between the power supplies, and the oscillating circuit that consumes less current operates to suppress the consuming current of the oscillating circuit.

In FIG. 1, one input terminal of a 2-input NAND gate ND2 forming an S / R latch is
Although the output of the oscillation stage (amplifier) is input, the same function can be achieved by inputting a signal obtained by inverting the output of the amplitude detection circuit 1 to the input terminal by an inverter gate. Further, the amplitude detection circuit 1 realizes a function of inverting the output from a low level to a high level when the amplitude width of the oscillation stage exceeds a certain value. For example, a well-known peak hold circuit, level comparator, etc. It is composed of a circuit.

[0025]

Second Embodiment FIG. 2 shows the circuit configuration of the second embodiment of the present invention. In FIG. 2, CP6 and CP7 are external capacitors,
The amplitude detection circuit 2 is a detection circuit that changes the output signal from a low level to a high level when the amplitude width of the oscillation stage becomes a certain value or more. ND2 and ND3 are 2-input NAND gates.
IV5, IV6, IV7 are inverter gates, Rf3 is a feedback resistor, X3 is a mechanical oscillator, Tr10, T
r11, Tr14, Tr15 are P-channel MOS transistors, and Tr12, Tr13, Tr16, Tr17 are N-channel MO transistors.
It is an S transistor.

The MOS transistors Tr11 and Tr12, and the MOS transistors Tr15 and Tr16 are CMOS
It constitutes an inverter. Further, the MOS transistors Tr10, Tr13 and Tr14, Tr17 form a switch for switching the amplifier. The two-input NAND gates ND2 and ND3 form an S / R latch as in the first embodiment.

In this oscillator circuit, a P-channel MOS transistor Tr15 and an N-channel MOS transistor Tr16 are provided.
Threshold voltage of other P-channel and N-channel MO
It is set lower than the threshold voltage of the S transistor. Therefore, the oscillation circuit composed of the MOS transistors Tr15 and Tr16 is
It consumes more current and lowers the oscillation start voltage than the oscillator circuit composed of r12.

Next, the operating principle of this embodiment will be described. Immediately after the power is turned on, the amplitude detection circuit 2 outputs a low level. As a result, the output of the 2-input NAND gate ND3 becomes high level, the MOS transistors Tr10 and Tr13 are turned off, the MOS transistors Tr14 and Tr17 are turned on, and an oscillation circuit having a low oscillation start voltage composed of the MOS transistors Tr15 and Tr16 is provided. It operates and the oscillation is started.

After the lapse of a certain time, the amplitude detection circuit 2 detects that the amplitude has reached a certain value or more, and the output of the amplitude detection circuit 2 changes from low level to high level, and the two inputs N
The output of the AND gate ND3 becomes low level, and the MOS
The transistors Tr10 and Tr13 are turned on, the MOS transistors Tr14 and Tr17 are turned off, and the oscillation circuit having a small current consumption, which is constituted by the MOS transistors Tr11 and Tr12, operates and the current consumption of the oscillation circuit is suppressed.

The present invention has been described above with reference to the first and second embodiments, but the present invention is not limited to the embodiments of these embodiments, and various embodiments according to the principle of the present invention are possible. Including. For example, a configuration in which two amplifiers (inverters) are provided in the first and second embodiments has been proposed, but the present invention is not limited to two amplifiers (inverters), and the present invention is more numerous. It also includes the configuration of an oscillator circuit including an inverter.

[0031]

As described above, according to the present invention,
Oscillation immediately after the power is turned on, provided with a first amplifier composed of a low-current-consumption CMOS inverter, a second amplifier which consumes more current than the first amplifier but has a lower oscillation start voltage, and a means for controlling switching between them. At the start, the second amplifier, which consumes a large amount of current but has a low oscillation starting voltage, is activated, the amplitude of the oscillation stage is monitored, and the switch is switched after the amplitude exceeds a certain value. By activating the amplifier to configure the oscillation circuit, the oscillation start voltage is lowered and the consumption current is reduced.

Further, in the present invention, a plurality of amplifiers are constituted by CMOS inverters, and among them, threshold values of P-channel MOS transistors and N-channel MOS transistors which constitute a CMOS inverter which is activated at the start of oscillation immediately after power-on. By setting the voltage low, the current consumption is significantly reduced while keeping the oscillation start voltage low. Further, the oscillator circuit according to the present invention particularly contributes to lowering the voltage and current consumption of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an oscillator circuit according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of an oscillator circuit according to the present invention.

FIG. 3 is a circuit diagram of a conventional oscillator circuit using a damping resistor.

FIG. 4 is a circuit diagram of a conventional oscillation circuit in which an amplifier is composed of a load resistor and an N-channel MOS transistor.

[Explanation of symbols]

 ND0 to ND3 2-input NAND gate X0 to X3 mechanical oscillator IV0 to IV2, IV4 to IV7 inverter gate IV3 CMOS inverter CP0 to CP7 external capacitance Rd0 to Rd1 damping resistance R0, R1 load resistance Tr0 to Tr8, Tr10 to Tr17 MOS Transistor

Claims (6)

[Claims] 1. An oscillator circuit comprising a mechanical oscillator and a drive circuit for applying a voltage to the mechanical oscillator, wherein the drive circuit has a plurality of inverters connected in parallel with each other, and one end thereof. Is connected to the common connection point of the input terminals of the plurality of inverters and the other end is connected to the common connection point of the output terminals of the plurality of inverters, and is dependent on the value of the voltage amplitude of the oscillation circuit. And an oscillation circuit comprising switching means for switching the plurality of inverters. 2. A switching circuit, wherein the switching means detects an amplitude of an output voltage of an oscillation circuit, a latch circuit which takes in an output of the amplitude detection circuit and holds it, and a power supply wiring based on an output of the latch circuit. 2. The oscillation circuit according to claim 1, further comprising a switch circuit that cuts off or connects the current paths of the plurality of inverters with a ground wiring. 3. The oscillator circuit according to claim 1, wherein the plurality of inverters include an inverter having a low oscillation start voltage and an inverter having low power consumption. 4. The oscillator circuit according to claim 3, wherein the plurality of inverters are all CMOS inverters. 5. The oscillator circuit according to claim 3, wherein at least one of the plurality of inverters is a resistance load type inverter. 6. The oscillator circuit according to claim 3, wherein the switching means switches to an inverter having a low oscillation start voltage after power is turned on, and controls switching to an inverter having low power consumption after oscillation stabilization.