JP2000286637A - Oscillation circuit - Google Patents

Oscillation circuit

Info

Publication number
JP2000286637A
JP2000286637A JP8948599A JP8948599A JP2000286637A JP 2000286637 A JP2000286637 A JP 2000286637A JP 8948599 A JP8948599 A JP 8948599A JP 8948599 A JP8948599 A JP 8948599A JP 2000286637 A JP2000286637 A JP 2000286637A
Authority
JP
Japan
Prior art keywords
oscillation
inverter
oscillation circuit
circuit
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8948599A
Other languages
Japanese (ja)
Inventor
Makiyo Tokawa
牧世 東川
Yoji Fujiwara
洋治 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8948599A priority Critical patent/JP2000286637A/en
Priority to CN 00104770 priority patent/CN1268807A/en
Publication of JP2000286637A publication Critical patent/JP2000286637A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H03B5/364Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006Functional aspects of oscillators
    • H03B2200/0082Lowering the supply voltage and saving power
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006Functional aspects of oscillators
    • H03B2200/0094Measures to ensure starting of oscillations

Landscapes

  • Oscillators With Electromechanical Resonators (AREA)

Abstract

PROBLEM TO BE SOLVED: To shorten the oscillation start time of a crystal oscillation circuit while the center potential of the output of the circuit is fixed and, at the same time, to reduce the power consumption of the circuit. SOLUTION: A crystal oscillation circuit is provided with a three-state inverter buffer 12 and an ON/OFF control circuit 11. At the time of starting the oscillation circuit to oscillate, the buffer 12 is turned on and the circuit is started with the total gain of the buffer 12 and a logic inverter 13. Since the power supply to a logic element is fixed, the center potential of the output to the succeeding stage does not vary, but is fixed. The oscillation of the oscillation circuit is continued by only using the gain of the logic inverter 13 by turning off the three-state inverter buffer 12 by means of the ON/OFF control circuit 11 after the time required for stabilizing the oscillation circuit has elapsed. Since the oscillation circuit is made to make oscillating operations by only using the gain of the logic inverter 13 of a CMOS, the power consumption of the oscillation circuit can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、発振回路に関し、
特に、低消費電力で発振起動時間が短い水晶発振回路に
関する。
The present invention relates to an oscillation circuit,
In particular, it relates to a crystal oscillation circuit with low power consumption and a short oscillation start-up time.

【0002】[0002]

【従来の技術】従来の水晶発振回路は、図3に示すCM
OS発振回路のように構成されていた。図3において、
18はCMOSインバータ、19は帰還抵抗、20は水晶発振
子、21はゲート側コンデンサ、22はソース側コンデンサ
である。この発振回路において、CMOSインバータ18
は増幅素子として動作し、CMOSインバータ18の出力
を帰還抵抗19、水晶発振子20、ゲート側コンデンサ21、
ソース側コンデンサ22を介して帰還させて発振する。水
晶発振回路は、水晶発振子のQが大きいので、起動から
発振が安定するまで、CR発振回路に比較して長い時間
がかかる。
2. Description of the Related Art A conventional crystal oscillation circuit has a CM shown in FIG.
It was configured like an OS oscillation circuit. In FIG.
18 is a CMOS inverter, 19 is a feedback resistor, 20 is a crystal oscillator, 21 is a gate-side capacitor, and 22 is a source-side capacitor. In this oscillation circuit, the CMOS inverter 18
Operates as an amplifying element, and outputs the output of the CMOS inverter 18 to the feedback resistor 19, the crystal oscillator 20, the gate-side capacitor 21,
Oscillation is caused by feedback through the source-side capacitor 22. In the crystal oscillation circuit, since the Q of the crystal oscillator is large, it takes a longer time from startup until the oscillation is stabilized as compared with the CR oscillation circuit.

【0003】水晶発振回路の発振起動時間を短縮する従
来の例として、実開平6-77318号公報に開示されている
水晶発振回路がある。この水晶発振回路は、図4に示す
ように、電流制御形水晶発振回路と電源との間に、スイ
ッチ素子と抵抗の並列回路を設けたものである。電源オ
ン時には、スイッチ素子をオン状態にして、発振回路に
印加する電圧を高くする。発振が安定する一定時間後に
は、スイッチ素子をオフ状態にして、印加電圧を下げ
る。
As a conventional example of shortening the oscillation start time of the crystal oscillation circuit, there is a crystal oscillation circuit disclosed in Japanese Utility Model Laid-Open No. 6-77318. In this crystal oscillation circuit, as shown in FIG. 4, a parallel circuit of a switch element and a resistor is provided between a current control type crystal oscillation circuit and a power supply. When the power is turned on, the switch element is turned on to increase the voltage applied to the oscillation circuit. After a certain period of time when the oscillation stabilizes, the switching element is turned off to lower the applied voltage.

【0004】[0004]

【発明が解決しようとする課題】しかし、図3に示した
従来例の構成では、低消費電力化するためにCMOSイ
ンバータの能力を小さくすると、CMOSインバータの
増幅作用が低下し、発振起動時間が長くなる。また、発
振起動時間を短くするために、CMOSインバータの能
力を大きくすると、CMOSインバータの増幅作用は向
上するが、消費電力が大きくなるという問題があった。
However, in the configuration of the conventional example shown in FIG. 3, if the capacity of the CMOS inverter is reduced in order to reduce power consumption, the amplifying action of the CMOS inverter is reduced and the oscillation start time is reduced. become longer. Further, when the capacity of the CMOS inverter is increased to shorten the oscillation start time, the amplifying action of the CMOS inverter is improved, but there is a problem that the power consumption is increased.

【0005】また、図4に示した従来例の構成では、低
消費電力化し、かつ発振動作時間短縮を実現したが、論
理インバータへの印加電圧を変化させるために、次段へ
の出力信号のセンター電位が変化する。次段ゲートの闘
値は一定であるから、センター電位の変化のため、発振
信号の位相が変化するという問題があった。
In the conventional configuration shown in FIG. 4, the power consumption is reduced and the oscillation operation time is shortened. However, in order to change the voltage applied to the logic inverter, the output signal to the next stage is changed. The center potential changes. Since the threshold value of the next gate is constant, there is a problem that the phase of the oscillation signal changes due to a change in the center potential.

【0006】本発明は、上記従来の問題を解決し、発振
回路において、増幅素子として用いる論理インバータヘ
の印加電圧を変化させず、かつ低消費電力化し、かつ発
振動作時間短縮することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and to reduce the power consumption and shorten the oscillation operation time of an oscillation circuit without changing the voltage applied to a logic inverter used as an amplification element. I do.

【0007】[0007]

【課題を解決するための手段】上記の課題を解決するた
めに、本発明では、発振回路を、増幅素子としての論理
インバータと、水晶発振子と、帰還抵抗と、ゲート側コ
ンデンサと、ソース側コンデンサと、論理インバータに
並列かつ順方向に接続され、発振起動時の一定時間のみ
オンとなるスリーステートインバータバッファとを具備
する構成とした。
In order to solve the above-mentioned problems, according to the present invention, an oscillation circuit includes a logic inverter as an amplifying element, a crystal oscillator, a feedback resistor, a gate-side capacitor, and a source-side. A configuration is provided that includes a capacitor and a three-state inverter buffer that is connected in parallel and forward direction to the logic inverter, and that is turned on only for a certain period of time when the oscillation is started.

【0008】このように構成したことにより、スリース
テートインバータバッファがオン状態のとき、論理イン
バータヘの印加電圧を変化させずに、論理インバータの
ゲインとあわせて通常より大きなゲインを得て、発振動
作安定までの時間を短縮することができ、かつ低消費電
力化できる。
[0008] With this configuration, when the three-state inverter buffer is in the on state, the gain applied to the logic inverter can be increased to a larger value than the normal one without changing the voltage applied to the logic inverter, and the oscillation operation can be performed. Time until stabilization can be shortened, and power consumption can be reduced.

【0009】[0009]

【発明の実施の形態】本発明の請求項1に記載の発明
は、増幅素子としての論理インバータと、水晶発振子
と、帰還抵抗と、ゲート側コンデンサと、ソース側コン
デンサと、論理インバータに並列かつ順方向に配置さ
れ、発振起動時の一定時間のみオンとなるスリーステー
トインバータバッファを備えた発振回路であり、論理イ
ンバータヘの印加電圧を変化させずに通常より大きなゲ
インを得て、発振動作安定までの時間を短縮するという
作用を有する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to a first aspect of the present invention is directed to a logic inverter as an amplifying element, a crystal oscillator, a feedback resistor, a gate-side capacitor, a source-side capacitor, and a logic inverter. In addition, the oscillation circuit is equipped with a three-state inverter buffer that is arranged in the forward direction and is turned on only for a certain period of time at the time of oscillation startup. It has the effect of shortening the time until stabilization.

【0010】本発明の請求項2に記載の発明は、水晶発
振子と、前記水晶発振子に並列に接続された帰還抵抗
と、前記帰還抵抗と並列に接続された論理インバータ
と、前記論理インバータのゲート側及びソース側に設け
たコンデンサと、前記論理インバータと並列かつ順方向
に接続されたスリーステートインバータバッファと、発
振起動から一定時間経過すると前記スリーステートイン
バータバッファをオフにする制御回路とを具備する発振
回路であり、スリーステートインバータバッファをオフ
にして低消費電力で発振動作を継続させるという作用を
有する。
According to a second aspect of the present invention, there is provided a crystal oscillator, a feedback resistor connected in parallel with the crystal oscillator, a logic inverter connected in parallel with the feedback resistor, and the logic inverter. A capacitor provided on the gate side and the source side of the logic inverter, a three-state inverter buffer connected in parallel and forward with the logic inverter, and a control circuit for turning off the three-state inverter buffer after a lapse of a predetermined time from the start of oscillation. The oscillation circuit has a function of turning off the three-state inverter buffer and continuing the oscillation operation with low power consumption.

【0011】以下、本発明の実施の形態について、図1
と図2を参照しながら詳細に説明する。
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described in detail with reference to FIG.

【0012】(実施の形態)本発明の実施の形態は、ス
リーステートインバータバッファを、論理インバータに
並列かつ順方向に接続し、発振起動時の一定時間のみオ
ンとする水晶発振回路である。
(Embodiment) An embodiment of the present invention is a crystal oscillation circuit in which a three-state inverter buffer is connected to a logic inverter in parallel and in a forward direction, and is turned on only for a certain period of time when oscillation is started.

【0013】図1は、本発明の実施の形態の水晶発振回
路の回路図である。図1において、オン・オフ制御回路
11は、スリーステートインバータバッファをオン・オフ
制御する回路である。12は、スリーステートインバータ
バッファである。13は、CMOSの論理インバータ、14
は帰還抵抗、15は水晶振動子、16はゲート側コンデン
サ、17はソース側コンデンサである。図2は、本発明の
実施の形態の発振回路の動作フローチャートである。
FIG. 1 is a circuit diagram of a crystal oscillation circuit according to an embodiment of the present invention. In FIG. 1, an on / off control circuit
Reference numeral 11 denotes a circuit for controlling on / off of the three-state inverter buffer. 12 is a three-state inverter buffer. 13 is a CMOS logic inverter, 14
Is a feedback resistor, 15 is a crystal oscillator, 16 is a gate-side capacitor, and 17 is a source-side capacitor. FIG. 2 is an operation flowchart of the oscillation circuit according to the embodiment of the present invention.

【0014】上記のように構成された本発明の実施の形
態の水晶発振回路の動作を、図2を参照して説明する。
電源をオンにすると、水晶発振回路は発振を開始する。
発振起動時に、抵抗、コンデンサ、オペアンプ等で構成
したオン・オフ制御回路11の信号により、スリーステー
トインバータバッファ12が、抵抗とコンデンサで決まる
ある時間オン状態となる。スリーステートインバータバ
ッファ12のゲインと論理インバータ13のゲインとあわせ
て、通常より大きなゲインで水晶発振回路は起動する。
そのため、発振の立ち上がり時間が短くなる。論理イン
バータ13への印加電圧を変化させないので、次段への出
力信号のセンター電位は変化しない。したがって、発振
信号の位相が変化するということはない。
The operation of the thus-configured crystal oscillation circuit according to the embodiment of the present invention will be described with reference to FIG.
When the power is turned on, the crystal oscillation circuit starts oscillating.
At the time of starting the oscillation, the three-state inverter buffer 12 is turned on for a certain period of time determined by the resistor and the capacitor by the signal of the on / off control circuit 11 composed of a resistor, a capacitor, an operational amplifier and the like. The crystal oscillation circuit is started with a gain larger than usual, in accordance with the gain of the three-state inverter buffer 12 and the gain of the logic inverter 13.
Therefore, the rise time of the oscillation is shortened. Since the voltage applied to the logic inverter 13 is not changed, the center potential of the output signal to the next stage does not change. Therefore, the phase of the oscillation signal does not change.

【0015】また、発振が安定する一定時間後に、オン
・オフ制御回路11の信号により、スリーステートインバ
ータバッファ12がオフ状態になる。水晶発振回路が安定
して、発振できる最低のゲインを有する論理インバータ
13のみのゲインで発振を継続する。なお、ON/OFF
制御回路11は、タイマーや遅延素子等でもよい。
After a certain period of time when the oscillation is stabilized, the three-state inverter buffer 12 is turned off by a signal from the on / off control circuit 11. A logic inverter with the lowest gain at which the crystal oscillation circuit is stable and can oscillate
Oscillation continues with a gain of only 13. In addition, ON / OFF
The control circuit 11 may be a timer, a delay element, or the like.

【0016】インバータヘの印加電圧を変化させるので
はなく、発振起動時にスリーステートインバータバッフ
ァ12をオンとし、CMOSの論理インバータ13の利得と
合わせて大きな利得を得ることで、発振起動時間を短縮
できる。また、発振が定常状態になる一定時間後に、ス
リーステートインバータバッファ12をオフにすること
で、CMOSの論理インバータ13のみの利得で発振させ
るので、低消費電力で発振動作を継続させることができ
る。さらに、論理素子の電源が一定であるため、次段へ
の出力のセンター電位は変化せず一定である。
Rather than changing the voltage applied to the inverter, the three-state inverter buffer 12 is turned on at the time of oscillation startup, and a large gain is obtained in accordance with the gain of the CMOS logic inverter 13, so that the oscillation startup time can be reduced. . In addition, by turning off the three-state inverter buffer 12 after a certain period of time when the oscillation is in a steady state, the oscillation is performed with the gain of only the CMOS logic inverter 13, so that the oscillation operation can be continued with low power consumption. Furthermore, since the power supply of the logic element is constant, the center potential of the output to the next stage does not change and remains constant.

【0017】上記のように、本発明の実施の形態では、
発振回路を、増幅素子としての論理インバータと、水晶
発振子と、帰還抵抗と、ゲート側コンデンサと、ソース
側コンデンサと、論理インバータに並列かつ順方向に配
置され、発振起動時の一定時間のみオンとなるスリース
テートインバータバッファを備えた構成としたので、ス
リーステートインバータバッファがオン状態のとき、論
理インバータのゲインとあわせて、論理インバータヘの
印加電圧を変化させずに通常より大きなゲインを得て、
発振動作安定までの時間を短縮することができ、かつ低
消費電力化できる。
As described above, in the embodiment of the present invention,
The oscillation circuit is arranged in parallel and forward direction with the logic inverter as the amplifying element, the crystal oscillator, the feedback resistor, the gate-side capacitor, the source-side capacitor, and the logic inverter. When the three-state inverter buffer is in the ON state, it is possible to obtain a larger gain than usual without changing the applied voltage to the logical inverter, together with the gain of the logical inverter. ,
The time until the oscillation operation stabilizes can be reduced, and the power consumption can be reduced.

【0018】[0018]

【発明の効果】以上の説明から明らかなように、本発明
では、発振回路を、増幅素子としての論理インバータ
と、水晶発振子と、帰還抵抗と、ゲート側コンデンサ
と、ソース側コンデンサと、、論理インバータに並列か
つ順方向に配置され、発振起動時の一定時問のみオンと
なるスリーステートインバータバッファを備えた構成と
したので、出力のセンター電位を変化させずに、発振起
動時間を短縮し、低消費電力で発振動作させることがで
きるという効果が得られる。
As is apparent from the above description, according to the present invention, the oscillation circuit comprises a logic inverter as an amplifying element, a crystal oscillator, a feedback resistor, a gate-side capacitor, a source-side capacitor, A three-state inverter buffer that is arranged in parallel with the logic inverter in the forward direction and that is turned on only at certain times when the oscillation starts is provided, so that the oscillation start time is reduced without changing the output center potential. Thus, an effect that the oscillation operation can be performed with low power consumption can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態の水晶発振回路の構成図、FIG. 1 is a configuration diagram of a crystal oscillation circuit according to an embodiment of the present invention;

【図2】本発明の実施の形態の水晶発振回路の動作フロ
ーチャート、
FIG. 2 is an operation flowchart of the crystal oscillation circuit according to the embodiment of the present invention;

【図3】従来の水晶発振回路の構成図、FIG. 3 is a configuration diagram of a conventional crystal oscillation circuit,

【図4】従来の別の水晶発振回路の構成図である。FIG. 4 is a configuration diagram of another conventional crystal oscillation circuit.

【符号の説明】[Explanation of symbols]

11 ON/OFF制御回路 12 スリーステートインバータバッファ 13 論理インバータ 14、19 帰還抵抗 15、20 水晶発振子 16、21 ゲート側コンデンサ 17、22 ソース側コンデンサ 18 論理インバータ 11 ON / OFF control circuit 12 Three-state inverter buffer 13 Logical inverter 14, 19 Feedback resistor 15, 20 Crystal oscillator 16, 21 Gate side capacitor 17, 22 Source side capacitor 18 Logical inverter

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 増幅素子としての論理インバータと、水
晶発振子と、帰還抵抗と、ゲート側コンデンサと、ソー
ス側コンデンサと、前記論理インバータに並列かつ順方
向に接続され、発振起動時の一定時間のみオンとなるス
リーステートインバータバッファとを具備することを特
徴とする発振回路。
1. A logic inverter as an amplifying element, a crystal oscillator, a feedback resistor, a gate-side capacitor, a source-side capacitor, are connected in parallel and forward to the logic inverter, and are provided for a certain period of time when oscillation is started. An oscillation circuit comprising: a three-state inverter buffer that is turned on only.
【請求項2】 水晶発振子と、前記水晶発振子に並列に
接続された帰還抵抗と、前記帰還抵抗と並列に接続され
た論理インバータと、前記論理インバータのゲート側及
びソース側に設けたコンデンサと、前記論理インバータ
と並列かつ順方向に接続されたスリーステートインバー
タバッファと、発振起動から一定時間経過すると前記ス
リーステートインバータバッファをオフにする制御回路
とを具備することを特徴とする発振回路。
2. A crystal oscillator, a feedback resistor connected in parallel with the crystal oscillator, a logic inverter connected in parallel with the feedback resistor, and capacitors provided on a gate side and a source side of the logic inverter. An oscillation circuit comprising: a three-state inverter buffer connected in parallel with the logic inverter in a forward direction; and a control circuit for turning off the three-state inverter buffer after a lapse of a predetermined time from the start of oscillation.
JP8948599A 1999-03-30 1999-03-30 Oscillation circuit Pending JP2000286637A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8948599A JP2000286637A (en) 1999-03-30 1999-03-30 Oscillation circuit
CN 00104770 CN1268807A (en) 1999-03-30 2000-03-28 Oscillator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8948599A JP2000286637A (en) 1999-03-30 1999-03-30 Oscillation circuit

Publications (1)

Publication Number Publication Date
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Cited By (3)

* Cited by examiner, † Cited by third party
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JP2008147815A (en) * 2006-12-07 2008-06-26 Sanyo Electric Co Ltd Oscillation circuit
US7583565B2 (en) 2006-02-16 2009-09-01 Seiko Instruments, Inc. Electronic timepiece
EP3232564A1 (en) * 2016-04-11 2017-10-18 MediaTek Inc. Oscillator circuit with reconfigurable oscillator amplifier and/or hybrid amplitude calibration circuit and associated method

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CN101212221B (en) * 2006-12-29 2010-08-18 上海贝岭股份有限公司 Buffer in ultra-low power consumption integrated circuit
EP2634914B1 (en) * 2012-03-02 2015-01-28 Nxp B.V. An oscillator circuit
CN107294513B (en) * 2016-03-30 2021-02-02 中芯国际集成电路制造(上海)有限公司 Crystal oscillator circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7583565B2 (en) 2006-02-16 2009-09-01 Seiko Instruments, Inc. Electronic timepiece
JP2008147815A (en) * 2006-12-07 2008-06-26 Sanyo Electric Co Ltd Oscillation circuit
US8890632B2 (en) 2006-12-07 2014-11-18 Semiconductor Components Industries, Llc Oscillator circuit
EP3232564A1 (en) * 2016-04-11 2017-10-18 MediaTek Inc. Oscillator circuit with reconfigurable oscillator amplifier and/or hybrid amplitude calibration circuit and associated method
CN107294525A (en) * 2016-04-11 2017-10-24 联发科技股份有限公司 Pierce circuit and its correlation technique
US10291237B2 (en) 2016-04-11 2019-05-14 Mediatek Inc. Oscillator circuit with reconfigurable oscillator amplifier and/or hybrid amplitude calibration circuit and associated method
CN107294525B (en) * 2016-04-11 2021-05-07 联发科技股份有限公司 Oscillator circuit and related method thereof

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