JP2002014741A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit having a self-biasing type clock signal amplifier which can speedily supply a stable clock signal and minimize an increase of a current. SOLUTION: The semiconductor integrated circuit having the self-biasing type clock signal amplifier which generates the clock signal with the input voltage from an AC signal source 2 is provided with a voltage supply means comprising a reference voltage source 6 composed of an operational amplifier OP-Amp which abruptly varying a rise of a voltage by applying a bias voltage in addition to the voltage from the AC signal source 2 when the signal source 2 starts up.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for supplying a clock with a self-biased clock signal amplifier.

[0002]

2. Description of the Related Art In a conventional self-biased clock signal amplifier, a period from the start of a signal source to the output of a clock signal is determined by a coupling capacitance and a feedback resistor. FIG. 8 shows an example of a conventional self-biased clock signal amplifier. In FIG. 8, 1 is a coupling capacity,
Reference numeral 2 denotes an AC signal source, 3 denotes a feedback resistor, 4 denotes a first-stage inverter, and 5 denotes a second-stage inverter.

As shown in FIG. 8, a coupling capacitor 1 and an AC signal source 2 are usually provided outside an IC and are not included inside an IC as a semiconductor integrated circuit according to the present invention. The conventional self-biased clock signal amplifier includes a first-stage inverter 4 including a feedback resistor and a second-stage inverter 5. Here, instead of the inverter, NAND
Even if a gate and a NOR gate are used, they can be regarded as an inverter with a control input, so that they are logically equivalent.

Next, the operation of the conventional self-biased clock signal amplifier will be described with reference to FIG. A in FIG.
Focusing on the voltage applied to the point, the voltage applied to the point A is the coupling capacitance 1 and the feedback resistance 3
Approach the bias point based on the time constant determined by A
As the voltage applied to the point approaches the bias point, the clock signal is gradually input from the self-biased clock signal amplifier to the internal logic circuit, but this clock signal is also unstable at first, and a stable clock is input. Takes more time.

[0005]

Here, in order to supply a stable clock signal to the internal logic circuit more quickly, the coupling capacitance 1 or the feedback resistor 3 may be made smaller, but if the feedback resistor 3 is made smaller, The current increases,
As a result, power consumption has increased. When the coupling capacitance is reduced, the cutoff frequency of the high-pass filter formed together with the feedback resistor 3 increases, and a desired clock may not be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and is a self-biased clock signal amplifier capable of quickly supplying a stable clock signal and minimizing an increase in current. It is intended to obtain a semiconductor integrated circuit having the following.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal based on an input voltage from an AC signal source. At the time of start-up, a voltage supply means for applying a bias voltage to the voltage from the AC signal source and changing the rise of the voltage sharply is provided.

In a semiconductor integrated circuit according to a second aspect of the present invention, in the semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal based on an input voltage from an AC signal source, when the signal source starts up, A voltage supply means comprising an operational amplifier for applying a bias voltage to the voltage from the signal source and changing the rise of the voltage sharply is provided.

In the semiconductor integrated circuit according to the third aspect of the present invention, after the generation of the clock signal is stabilized, the application of the bias voltage by the voltage supply means is stopped.

In a semiconductor integrated circuit according to a fourth aspect of the present invention, there is provided a counter circuit for counting a clock signal generated by a self-biased clock signal amplifier.
By controlling the voltage supply means according to the count value of the counter circuit, the application of the bias voltage by the voltage supply means is stopped.

In a semiconductor integrated circuit according to a fifth aspect of the present invention, a reference voltage source for supplying a reference voltage to a positive input terminal of the operational amplifier is provided.

In a semiconductor integrated circuit according to a sixth aspect of the present invention, there is provided a counter circuit for counting a clock signal generated by a self-biased clock signal amplifier,
The circuit configuration is made variable according to the count value of the counter circuit.

[0013] In a semiconductor integrated circuit according to a seventh aspect of the present invention, there is provided a counter circuit for counting a clock signal generated by a self-biased clock signal amplifier.
The resistance value of the feedback resistor in the self-biased clock signal amplifier is made relatively small when the signal source rises according to the count value of the counter circuit.

According to an eighth aspect of the present invention, in a semiconductor integrated circuit, a first inverter having a feedback resistor connected in parallel and a self-biased clock signal amplifier connected in series with the first inverter together with the first inverter. And a counter circuit that counts a clock signal generated by a self-biased clock signal amplifier formed by the first and second inverters. When the signal source rises, the resistance value of the feedback resistor in the self-biased clock signal amplifier is made relatively small when the signal source rises, and the resistance of the feedback resistor in the self-biased clock signal amplifier is increased in accordance with the increase in the count value of the counter circuit. The value is increased.

In a semiconductor integrated circuit according to a ninth aspect of the present invention, a counter circuit for counting a clock signal generated by a self-biased clock signal amplifier is provided.
A relatively high-performance inverter is used when the signal source starts up according to the count value of the counter circuit.

In the semiconductor integrated circuit according to the tenth aspect,
A first inverter connected in parallel with a feedback resistor, a second inverter connected in series to the first inverter and forming a self-biased clock signal amplifier together with the first inverter; A counter circuit for counting a clock signal generated by a self-biased clock signal amplifier constituted by a second inverter, wherein a plurality of inverters having different performances are selectively used as the first inverter. And using a high-performance inverter at the time of starting the signal source according to the count value of the counter circuit, and sequentially using lower-performance inverters as the count value of the counter circuit increases. It is.

In the semiconductor integrated circuit according to the eleventh aspect,
The voltage supply means supplies a bias voltage by resistance division.

In the semiconductor integrated circuit according to the twelfth aspect,
A device comprising: a first inverter connected in parallel with a feedback resistor; and a second inverter connected in series to the first inverter and forming a self-biased clock signal amplifier together with the first inverter. A first resistor connected between a bias voltage supply power supply and an input side of the first inverter; a second resistor connected between an input side of the first inverter and a ground portion; At the time of startup by the AC signal source, the voltage by the bias voltage supply power supply is divided by the first and second resistors, and a bias voltage for steepening the voltage rise is supplied. Things.

In the semiconductor integrated circuit according to the thirteenth aspect,
A counter circuit for performing a count operation of a clock signal generated by a self-biased clock signal amplifier constituted by first and second inverters is provided, and a clock count number for causing the counter circuit to perform a predetermined operation is provided. It can be set.

In a semiconductor integrated circuit according to a fourteenth aspect,
A counter circuit for performing a count operation of a clock signal generated by a self-biased clock signal amplifier constituted by first and second inverters is provided, and a clock count number for causing the counter circuit to perform a predetermined operation is provided. It is provided with a count number register to be set.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 First Embodiment A first embodiment of the present invention will be described with reference to FIGS. Figure 1
3 is a connection diagram illustrating a configuration according to Embodiment 1. FIG. FIG. 2 is an image diagram showing an operation in the first embodiment in comparison with a conventional technique. FIG. 2A shows the operation of the related art, and FIG. 2B shows the operation in the first embodiment.

In FIG. 1, reference numeral 1 denotes a coupling capacity;
Is an AC signal source, 3 is a feedback resistor, 4 is a first inverter composed of a first-stage inverter, 5 is a second inverter composed of a second-stage inverter, and 6 is an operational amplifier OP-Amp.
, A counter circuit 7, and an OP-Amp control circuit 8 for controlling an operational amplifier OP-Amp constituting the reference voltage source 6.

In the configuration of the first embodiment shown in FIG. 1, in addition to a conventional self-biased clock signal amplifier, a reference voltage source 6, a counter circuit 7, and an OP-Amp control circuit 8 comprising an operational amplifier OP-Amp are provided. It has a equipped configuration.
Here, the feedback resistor 3, the inverter 4, the reference voltage source 6, the counter circuit 7, and the OP-Amp control circuit 8
As shown in FIG. 1, the IC is integrated as a semiconductor integrated circuit inside the IC, and the coupling capacitor 1 and the AC signal source 2 are provided outside the IC. The clock signal generated by the inverters 4 and 5 is supplied to an internal logic circuit integrated and formed inside the IC.

The reference voltage source 6 supplies a bias point voltage to the point A on the input side of the first-stage inverter 4, and the rise of the potential at the point A starting from the rise of the signal source is shown in FIG.
As shown in FIG. As a result, the clock input to the internal logic can be hastened. FIG.
2A shows the rise of the potential at the point A and the clock signal output according to the prior art for comparison with FIG. 2B, and FIG. 2B according to the present invention illustrates the conventional technique. 2A shows that the rise of the potential at the point A and the output of the clock signal change faster and sharper than those in FIG.

The counter circuit 7 counts the number of clock inputs to the internal logic, and sends a signal to the operational amplifier OP-Amp control circuit 8 when the count reaches a specified number. The OP-Amp control circuit 8 that controls the operational amplifier OP-Amp recognizes that the self-biased clock signal has entered a steady state and has started to supply a stable clock based on the signal from the counter circuit 7, and configures the reference voltage source 6. By turning off the operational amplifier OP-Amp and stopping the supply of the bias point voltage, the increase in current is minimized. Here, instead of the inverters 4 and 5, a NAND gate, NO
Even if an R gate is used, it can be regarded as an inverter with a control input, so that it is logically equivalent.

According to the first embodiment of the present invention, in a semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal based on an input voltage from an AC signal source 2, when the signal source 2 starts up, A voltage supply means comprising a reference voltage source 6 comprising an operational amplifier OP-Amp for applying a bias voltage to the bias point voltage from the AC signal source 2 and changing the rising of the voltage sharply is provided. A counter circuit for counting the clock signal generated by the signal amplifier is provided, and after the generation of the clock signal is stabilized, the voltage supply means comprising the reference voltage is controlled according to the count value of the counter circuit; The application of the bias voltage by the voltage supply means is stopped. , Stable clock signal is promptly supplied, and the increase in current can be obtained a semiconductor integrated circuit having a self-bias type clock signal amplifier that can be minimized.

Embodiment 2 FIG. Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 is a connection diagram showing a configuration according to the second embodiment. In FIG. 3, reference numeral 1 denotes a coupling capacitor, 2 denotes an AC signal source, 3 denotes a feedback resistor, 4 denotes a first inverter including a first-stage inverter, 5 denotes a second inverter including a second-stage inverter, and 6 denotes a second inverter. A reference voltage source constituted by an operational amplifier OP-Amp, 7 is a counter circuit, 8 is an operational amplifier O constituting a reference voltage source
An OP-Amp control circuit for controlling P-Amp, and 9 is a reference voltage source.

The configuration of the second embodiment shown in FIG. 3 has a configuration further including a reference voltage source 9 in addition to the configuration of the first embodiment. Here, feedback resistor 3, inverter 4, 5, reference voltage source 6, counter circuit 7, OP-Amp
As shown in FIG. 3, the control circuit 8 and the reference power supply 9 are integrated as a semiconductor integrated circuit inside the IC, and the coupling capacitance 1 and the AC signal source 2 are provided outside the IC. The clock signal generated by the inverters 4 and 5 is supplied to an internal logic circuit integrated and formed inside the IC.

In the second embodiment, the reference voltage source 9
Has the same configuration as the input section of the self-biased clock signal amplifier including the feedback resistor 3 and the first-stage inverter 4, and the reference voltage from the reference voltage source 9 is used as the positive input terminal of the operational amplifier OP-Amp that forms the reference voltage source 6 To improve the accuracy of the bias voltage supplied to the point A by the reference voltage source 6. As a result, the time required for the clock to stabilize can be further reduced. Here, instead of inverters 4 and 5, NA
Even if an ND gate and a NOR gate are used, they can be regarded as an inverter with a control input, so that they are logically equivalent.

According to the second embodiment of the present invention, in a semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal based on an input voltage from an AC signal source, when starting up the signal source, A voltage supply means comprising an operational amplifier OP-Amp for applying a bias voltage to the voltage from the signal source to sharply change the rise of the voltage is provided, and the reference voltage source 9 is provided by a self-consistent circuit comprising the feedback resistor 3 and the first-stage inverter 4. It has the same configuration as the input part of the bias type clock signal amplifier, and a reference voltage source for supplying a reference voltage to the positive input terminal of the operational amplifier OP-Amp is provided. The increase can be minimized and the correct bias voltage Clock signal by setting it is possible to obtain a semiconductor integrated circuit having a self-bias type clock signal amplifier can be further shorten the time required to stabilize.

Embodiment 3 Third Embodiment A third embodiment according to the present invention will be described with reference to FIG. FIG. 4 is a connection diagram showing a configuration according to the third embodiment.

In FIG. 4, reference numeral 1 denotes a coupling capacity;
.., 13 are switch elements S
W is a feedback resistor selected by W, 4 is a first inverter composed of a first-stage inverter, 5 is a second inverter composed of a second-stage inverter, 7 is a counter circuit, and 10 is an on / off switch element SW. This is a SW control circuit for controlling.

In FIG. 4, in addition to the self-biased clock signal amplifier, the SW control circuit 10 and the switch element SW
, 13 are selected. Here, feedback resistor 3, inverter 4,
5, the counter circuit 7, the SW control circuit 10, the switch element SW and the feedback resistors 11, 12,..., 13 are integrated as a semiconductor integrated circuit inside the IC, as shown in FIG. Signal source 2 is an IC
It is provided outside. The clock signal generated by the inverters 4 and 5 is supplied to an internal logic circuit integrated and formed inside the IC.

In the third embodiment, the clock input to the internal logic is counted by the counter circuit 7, and when the clock reaches an arbitrary number (N1, N2,..., NM), the SW control circuit 1
Signals are sequentially sent to 0. The feedback resistors 11, 12,..., 13 selected by the switch element SW have a total feedback resistance sufficiently higher than the resistance of the feedback resistor in the conventional self-biased clock signal amplifier when the signal source starts up. It is assumed that the configuration is such that the value gradually becomes larger by a signal sequentially sent from the SW control circuit 10 so that the value becomes smaller.

In the third embodiment, the time constant determined by the coupling capacitance 1 and the overall feedback resistance is reduced by setting the overall feedback resistance to a sufficiently small value at the time of starting the signal source. The rise of the potential at the point A on the input side of the inverter 4 is sharply changed as shown in FIG. As a result, the clock input to the internal logic can be hastened. Further, as the stable supply of the clock is started and the count is advanced, the overall feedback resistance is gradually changed to a large value, thereby minimizing an increase in current. Here, NAN is used instead of inverters 4 and 5.
Even if a D gate and a NOR gate are used, they can be regarded as an inverter with a control input, so that they are logically equivalent.

According to the third embodiment of the present invention, the counter circuit 7 for counting the clock signal generated by the self-biased clock signal amplifier constituted by the first and second inverters 4 and 5 is provided. ,
Self-biased clock signal amplifier capable of quickly supplying a stable clock signal and minimizing an increase in current because the circuit configuration is made variable in accordance with the count value of the counter circuit 7. A semiconductor integrated circuit having a clock signal can be obtained, and the count value of the counter circuit that performs the count operation of the generated clock signal can be used to form an appropriate circuit configuration according to the generation state of the clock signal. A signal can be generated.

According to the third embodiment of the present invention, the first inverter 4 having feedback resistors 11, 12,..., 13 connected in parallel, and the first inverter 4 connected in series to the first inverter 4, Second inverter 5 constituting a self-biased clock signal amplifier together with first inverter 4
And a counter circuit 7 that counts a clock signal generated by a self-biased clock signal amplifier constituted by the first and second inverters 4 and 5 according to a count value of the counter circuit 7. When the signal source 2 rises, the resistance value of the feedback resistors 11, 12,..., 13 in the self-biased clock signal amplifier is made relatively small, and the self-biased clock signal amplifier is increased in accordance with the increase in the count value of the counter circuit 7. , 13 are increased, the resistance value of the feedback resistors 11, 12,..., 13 is controlled in accordance with the count value of the counter circuit 7, thereby stabilizing the resistance value. Self-biased clock that can supply a clock signal quickly and minimize the increase in current It is possible to obtain a semiconductor integrated circuit having a signal amplifier.

Embodiment 4 FIG. Embodiment 4 of the present invention will be described with reference to FIG. FIG. 5 is a connection diagram showing a configuration according to the fourth embodiment.

In FIG. 5, reference numeral 1 denotes a coupling capacity;
, 16 are inverters selected by the switch element SW as first inverters of the first-stage inverter, and 5 is a second inverter of the second-stage inverter. Inverter, 7 is a counter circuit, and 10 is a SW control circuit for controlling ON / OFF of the switch element SW.

In FIG. 5, in addition to the conventional self-biased clock signal amplifier, a configuration including a SW control circuit 10 and inverters 14, 15,..., 16 selected by SW instead of the first-stage inverter 4 is shown. Have. Here, the feedback resistor 3, inverter 4, 5, reference voltage source 6, counter circuit 7, SW control circuit 10, switch element SW and inverters 14, 15,...
The IC is integrated as a semiconductor integrated circuit inside the IC, and the coupling capacitor 1 and the AC signal source 2 are provided outside the IC. The clock signal generated by the inverters 4 and 5 is supplied to an internal logic circuit integrated and formed inside the IC.

In the fourth embodiment, the clock input to the internal logic is counted by the counter circuit 7, and when a predetermined number (N1, N2,..., NM) is reached, the SW control circuit 1
Signals are sequentially sent to 0. The inverters 14, 15,..., 16 selected by the switch element SW are selected when the signal source is started up.
In addition, a configuration is adopted in which a signal having a gradually lower capacity is selected based on a signal sequentially transmitted from the SW control circuit 10.

In the fourth embodiment, when a signal source is started, a high-performance inverter is used to operate even if the potential at the point A is low, thereby making it possible to hasten the clock input to the internal logic. In addition, as the clock is supplied stably and the count advances, the use of a low-performance inverter gradually minimizes the increase in current. Here, instead of the inverters 14, 15,.
Even if an ND gate and a NOR gate are used, they can be regarded as an inverter with a control input, so that they are logically equivalent.

According to the fourth embodiment of the present invention, the first inverters 14, 1 having feedback resistors connected in parallel are provided.
, 16, a second inverter 5 connected in series to the first inverter 4 and constituting a self-biased clock signal amplifier together with the first inverter 4, and the first and second inverters 14 , 15, ..., 16,
And a counter circuit 7 for counting the clock signal generated by the self-biased clock signal amplifier composed of the first inverter 14,
, 16, a plurality of inverters having different performances are selectively used, and a high-performance inverter is used when the signal source starts up according to the count value of the counter circuit 7. 7 are sequentially used in accordance with the increase of the count value of the counter circuit 7, so that the performance of the first-stage inverters 14, 15,... A semiconductor integrated circuit having a self-biased clock signal amplifier capable of quickly supplying a stable clock signal and minimizing an increase in current can be obtained.

Embodiment 5 FIG. Embodiment 5 of the present invention will be described with reference to FIG. FIG. 6 is a connection diagram showing a configuration according to the fifth embodiment.

In FIG. 6, reference numeral 1 denotes a coupling capacity;
Is an AC signal source, 3 is a feedback resistor, 4 is a first inverter composed of a first-stage inverter, 5 is a second inverter composed of a second-stage inverter, 7 is a counter circuit, and 10 is an on / off switch element SW. SW control circuit for controlling off,
BV is a bias voltage supply power supply, and 17 and 18 are bias voltage supply resistors.

FIG. 6 shows a configuration in which the reference voltage in the first embodiment is replaced with a bias voltage source configured by resistance division using bias voltage supply resistors 17 and 18 selected by the switch element SW. Here, feedback resistor 3, inverter 4, 5, counter circuit 7, SW control circuit 10, switch element SW and bias voltage supply resistor 1
As shown in FIG. 6, the reference numerals 7 and 18 are integrated as a semiconductor integrated circuit inside the IC, and the coupling capacitance 1 and the AC signal source 2 are provided outside the IC. The clock signal generated by the inverters 4 and 5 is supplied to an internal logic circuit integrated and formed inside the IC.

A bias voltage source constructed by resistance division using the bias voltage supply resistors 17 and 18 supplies a bias point voltage to point A, and the rising of the potential at point A starting from the rise of the signal source changes sharply. Let it. As a result, the clock input to the internal logic can be hastened.
The counter circuit 7 counts the number of clock inputs to the internal logic, and when a predetermined number is reached, the SW control circuit 10
Send a signal to The SW control circuit 10 opens the switch elements SW of the bias voltage supply resistors 17 and 18 based on a signal from the counter circuit 7 to minimize an increase in current. Here, even if a NAND gate or a NOR gate is used instead of the inverters 4 and 5, it can be regarded as an inverter with a control input, so that it is logically equivalent.

According to the fifth embodiment of the present invention, the first inverter 4 having a feedback resistor connected in parallel and the self-biased type connected together with the first inverter 4 in series with the first inverter 4 are provided. A first resistor 17 connected between a bias voltage supply power supply BV and an input side of the first inverter 4; and a first resistor 17 connected to a second inverter constituting a clock signal amplifier. A second terminal connected between the input side of the inverter 4 and the ground part
And the voltage from the bias voltage supply power supply BV is divided by the first and second resistors 17 and 18 at the time of startup by the AC signal source 2 so that the voltage rises steeply. Is supplied, the voltage from the bias voltage supply power supply BV is divided by the first and second resistors 17 and 18 so that a stable clock signal is quickly supplied and the current is reduced. A semiconductor integrated circuit having a self-biased clock signal amplifier whose increase can be minimized can be obtained.

Embodiment 6 FIG. Embodiment 6 of the present invention will be described with reference to FIG. FIG. 7 is a connection diagram showing a configuration of the sixth embodiment. In FIG. 1, reference numeral 1 denotes a coupling capacitor, 2 denotes an AC signal source, 3 denotes a feedback resistor, 4 denotes a first inverter including a first-stage inverter, 5 denotes a second inverter including a second-stage inverter, and 6 denotes a second inverter. A reference voltage source composed of an operational amplifier OP-Amp, 7 is a counter circuit, and 8 is an operational amplifier OP-
An OP-Amp control circuit for controlling Amp, and 19 is a count number register for setting the count number of the counter circuit 7. Here, even if a NAND gate or a NOR gate is used instead of the inverters 4 and 5, it can be regarded as an inverter with a control input, so that it is logically equivalent.

In FIG. 7, a count number register 19 is added to the configuration of the first embodiment. Here, the feedback resistor 3, inverter 4, 5, reference voltage source 6, counter circuit 7, OP-Amp control circuit 8 and count number register 19 are integrated as a semiconductor integrated circuit inside the IC as shown in FIG. The coupling capacitor 1 and the AC signal source 2 are provided outside the IC. The clock signal generated by the inverters 4 and 5 is supplied to an internal logic circuit integrated and formed inside the IC.

In the first embodiment, the clock count used to determine whether or not the stable clock supply has started is predetermined. In the sixth embodiment, however, the count number register 19 is controlled by software S / W or the like. Write the count number. As a result, it is possible to set an optimal clock count for an actual operating condition.

Similarly, it is also possible to add a count number register 19 to the configuration of the second to fifth embodiments to perform the same operation.

In the second embodiment shown in FIG. 3, a count number register for setting the operation count number of the counter circuit 7 is provided, and the reference voltage source 9 is connected to the positive input terminal according to the count number set in the count number register. Reference voltage source 6 composed of operational amplifier OP-amp connected to
To control the bias voltage supply operation.

In the third embodiment shown in FIG. 4, a count register for setting the operation count of the counter circuit 7 is provided, and the feedback resistors 11, 12,... It is possible to control the control signal supply operation of the SW control circuit 10 that supplies a control signal to the switch element SW that controls ON / OFF of the connection of the connection 13.

In the fourth embodiment shown in FIG. 5, a count register for setting the operation count of the counter circuit 7 is provided, and the inverters 14, 15,... The control signal supply operation of the SW control circuit 10 that supplies a control signal to the switch element SW that selectively controls the connection of the switches can be controlled.

In the fifth embodiment shown in FIG. 6, a count number register for setting the operation count number of the counter circuit 7 is provided, and the connection of the resistors 17 and 18 is turned on by the count number set in the count number register. The control signal supply operation of the SW control circuit 10 that supplies a control signal to the switch element SW to be turned off can be controlled.

According to the sixth embodiment of the present invention, the counter circuit 7 for counting the clock signal generated by the self-biased clock signal amplifier is provided, and the counter circuit 7 performs a predetermined operation. A semiconductor integrated circuit with a self-biased clock signal amplifier that can supply a stable clock signal quickly and minimize the current increase because of the provision of a count number register that sets the clock count number In addition to this, there is an effect that a predetermined operation can be accurately performed by the clock count number of the counter circuit 7 set by the count number register.

[0058]

According to the first aspect of the present invention, in a semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal by an input voltage from an AC signal source, when the signal source starts up, the AC signal A voltage supply means for applying a bias voltage to the voltage from the source and steeply changing the rise of the voltage is provided, so that a stable clock signal can be quickly supplied and an increase in current can be minimized. A semiconductor integrated circuit having a self-biased clock signal amplifier can be obtained.

According to the second aspect of the present invention, in a semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal based on an input voltage from an AC signal source, when the signal source starts up, the AC signal source Since a voltage supply means comprising an operational amplifier for applying a bias voltage to the voltage and changing the rise of the voltage sharply is provided, a stable clock signal can be promptly supplied by applying the bias voltage by the voltage supply means comprising the operational amplifier. It is possible to obtain a semiconductor integrated circuit having a self-biased clock signal amplifier capable of minimizing an increase in current.

According to the third aspect of the present invention, after the generation of the clock signal is stabilized, the application of the bias voltage by the voltage supply means is stopped. The semiconductor integrated circuit having a self-biased clock signal amplifier that can minimize the increase by the stop of the bias voltage after stabilization can be obtained.

According to the fourth aspect, there is provided a counter circuit for counting the clock signal generated by the self-biased clock signal amplifier, and controlling the voltage supply means according to the count value of the counter circuit. As a result, the application of the bias voltage by the voltage supply means is stopped, so that a stable clock signal is quickly supplied, and the increase in current is minimized by stopping the bias voltage after the stabilization according to the count value of the counter circuit. Thus, a semiconductor integrated circuit having a self-biased clock signal amplifier that can be suppressed to a minimum can be obtained.

According to the fifth aspect of the present invention, since the reference voltage source for supplying the reference voltage to the positive input terminal of the operational amplifier is provided, a stable clock signal is quickly supplied, and the increase of the current is caused by the stabilized bias voltage. It is possible to obtain a semiconductor integrated circuit having a self-biased clock signal amplifier in which the time required until the clock signal is stabilized can be shortened by setting a proper bias voltage, while minimizing the time by stopping the operation.

According to the sixth aspect of the present invention, the counter circuit for counting the clock signal generated by the self-biased clock signal amplifier is provided, and the circuit configuration is made variable according to the count value of the counter circuit. Therefore, a self-biased clock signal amplifier capable of quickly supplying a stable clock signal and minimizing an increase in current can be provided by adopting an appropriate circuit configuration according to the generation state of the clock signal. And a semiconductor integrated circuit having the same.

According to the seventh aspect of the invention, the counter circuit for counting the clock signal generated by the self-biased clock signal amplifier is provided, and when the signal source starts up according to the count value of the counter circuit. Since the resistance value of the feedback resistor in the bias type clock signal amplifier is made relatively small, a stable clock signal is quickly supplied by controlling the resistance value of the feedback resistor by the count value of the counter circuit, and the current is reduced. It is possible to obtain a semiconductor integrated circuit having a self-biased clock signal amplifier capable of minimizing the increase.

According to the eighth aspect, a self-biased clock signal amplifier comprising a first inverter having a feedback resistor connected in parallel and a second inverter connected in series to the first inverter, A counter circuit for performing a count operation of a clock signal generated by the self-biased clock signal amplifier; and a resistance of a feedback resistor in the self-biased clock signal amplifier when the signal source starts up according to the count value of the counter circuit. Since the value of the feedback resistor in the self-biased clock signal amplifier is increased in accordance with the increase in the count value of the counter circuit, the feedback resistance is increased in accordance with the increase in the count value of the counter circuit. By increasing the resistance value, a stable clock signal can be supplied quickly and the current Increase it is possible to obtain a semiconductor integrated circuit having a self-bias type clock signal amplifier that can be minimized.

According to the ninth aspect, there is provided a counter circuit for counting the clock signal generated by the self-biased clock signal amplifier, and a comparison is made when the signal source starts up according to the count value of the counter circuit. High-performance inverters are used, so by selecting the performance of the inverter according to the increase in the count value of the counter circuit, a stable clock signal can be supplied promptly and the increase in current is minimized. A semiconductor integrated circuit having a self-biased clock signal amplifier capable of performing the above operation can be obtained.

According to the tenth aspect, a self-biased clock signal amplifier comprising a first inverter connected in parallel with a feedback resistor and a second inverter connected in series to the first inverter, A counter circuit that counts a clock signal generated by the self-biased clock signal amplifier; a plurality of inverters having different performances are selectively used as the first inverter; The high-performance inverter is used when the signal source is started in accordance with the count value of the counter circuit, and the lower-performance inverter is sequentially used in accordance with the increase in the count value of the counter circuit. Speed of stable clock signal by sequentially selecting inverter performance according to Supplied, and the increase in current can be obtained a semiconductor integrated circuit having a self-bias type clock signal amplifier that can be minimized.

According to the eleventh aspect, in the first to fourth aspects, the bias voltage is supplied by resistance division as the voltage supply means. Therefore, the supply of the bias voltage by resistance division provides a stable clock. A semiconductor integrated circuit having a self-biased clock signal amplifier that can supply a signal quickly and minimize an increase in current can be obtained.

According to the twelfth aspect, there is provided a self-biased clock signal amplifier comprising a first inverter having a feedback resistor connected in parallel and a second inverter connected in series to the first inverter. A first resistor connected between a bias voltage supply power supply and an input side of the first inverter; and a first resistor connected between an input side of the first inverter and a ground portion. A second resistor is provided, and at the time of startup by the AC signal source, a voltage by the bias voltage supply power supply is divided by the first and second resistors, and a bias voltage for steepening the rise of the voltage is set. Since the bias voltage is supplied, a stable clock signal is promptly supplied and a current is increased by supplying a bias voltage by resistance division of the first resistor and the second resistor. It is possible to obtain a semiconductor integrated circuit having a self-bias type clock signal amplifier that can be minimized.

According to the thirteenth aspect, a counter circuit for counting the clock signal generated by the self-biased clock signal amplifier is provided, and the clock count for causing the counter circuit to perform a predetermined operation is determined. Since the setting is possible, a semiconductor integrated circuit having a self-biased clock signal amplifier capable of quickly supplying a stable clock signal and minimizing an increase in current can be obtained, and can be used as a counter circuit. A predetermined operation can be accurately performed by the set count number.

According to the fourteenth aspect, a counter circuit for counting the clock signal generated by the self-biased clock signal amplifier is provided, and a clock count for causing the counter circuit to perform a predetermined operation is determined. Since the count number register to be set is provided, it is possible to obtain a semiconductor integrated circuit having a self-biased clock signal amplifier capable of quickly supplying a stable clock signal and suppressing an increase in current to a minimum. The predetermined operation can be accurately performed by the count number of the counter circuit set by the count number register.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an image diagram showing an operation of the self-biased clock amplifier according to the first embodiment of the present invention in comparison with a conventional technique.

FIG. 3 is a connection diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a connection diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a connection diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 6 is a connection diagram showing a configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 8 is a connection diagram illustrating a configuration of a semiconductor integrated circuit according to the related art.

FIG. 9 is an image diagram illustrating an operation of a self-biased clock amplifier according to the related art.

[Explanation of symbols]

1 coupling capacity, 2 AC signal source, 3 feedback resistor, 4th stage inverter, 5th stage inverter, 6
Reference voltage source, 7 counter circuit, OP-Amp operational amplifier, 8 OP-Amp control circuit, 9 reference voltage source, SW switch element, 10 SW control circuit, 1
1, 12, 13 a feedback resistor selected by the switch element SW, 14, 15, 16 an inverter selected by the switch element SW, a BV bias voltage supply power supply,
17, 18 Bias voltage supply resistor selected by switch element SW, 19 count register.

Continued on the front page (72) Inventor Tsutsumi Matsuishi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5B079 BA15 BC10 DD02 5F038 BB05 BG06 BG09 CD06 DF06 EZ20 5J098 AA11 AB02 AB08 AB23 AC04 AC19 AC30 AD03 CB09

Claims (14)

[Claims] 1. A semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal based on an input voltage from an AC signal source, wherein a bias voltage is applied to a voltage of the AC signal source when the signal source starts up. And a voltage supply means for rapidly changing the rise of the voltage by applying the voltage. 2. A semiconductor integrated circuit having a self-biased clock signal amplifier for generating a clock signal based on an input voltage from an AC signal source, wherein when starting up the signal source, a bias voltage is applied to a voltage from the AC signal source. And a voltage supply means comprising an operational amplifier for changing the rise of the voltage sharply by applying a voltage. 3. The semiconductor integrated circuit according to claim 1, wherein, after the generation of the clock signal is stabilized, the application of the bias voltage by the voltage supply unit is stopped. 4. A counter circuit that counts a clock signal generated by a self-biased clock signal amplifier, and controls the voltage supply means according to the count value of the counter circuit to control the voltage supply means. 4. The semiconductor integrated circuit according to claim 3, wherein the application of the bias voltage is stopped. 5. The semiconductor integrated circuit according to claim 2, wherein a reference voltage source for supplying a reference voltage to a positive input terminal of the operational amplifier is provided. 6. A counter circuit for counting a clock signal generated by a self-biased clock signal amplifier, wherein a circuit configuration is variable according to a count value of the counter circuit. A semiconductor integrated circuit according to claim 5. 7. A counter circuit for performing a count operation of a clock signal generated by a self-biased clock signal amplifier, wherein the self-biased clock signal amplifier is activated when the signal source is started according to the count value of the counter circuit. 7. The semiconductor integrated circuit according to claim 6, wherein the resistance value of the feedback resistor is relatively small. 8. A first inverter connected in parallel with a feedback resistor, a second inverter connected in series to the first inverter and forming a self-biased clock signal amplifier together with the first inverter, A counter circuit that counts a clock signal generated by a self-biased clock signal amplifier constituted by the first and second inverters, and starts up the signal source according to the count value of the counter circuit. Sometimes, the resistance value of the feedback resistor in the self-biased clock signal amplifier is made relatively small, and the resistance value of the feedback resistor in the self-biased clock signal amplifier is increased in accordance with an increase in the count value of the counter circuit. 7. The semiconductor integrated circuit according to claim 6, wherein: 9. A counter circuit for counting a clock signal generated by a self-biased clock signal amplifier is provided, and a relatively high-performance inverter is used when the signal source starts up according to the count value of the counter circuit. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is used. 10. A first inverter having a feedback resistor connected in parallel thereto, a second inverter connected in series to the first inverter and forming a self-biased clock signal amplifier together with the first inverter, A counter circuit for counting a clock signal generated by a self-biased clock signal amplifier constituted by the first and second inverters, wherein a plurality of inverters having different performances are selectively used as the first inverter. And a high-performance inverter is used when the signal source is started in accordance with the count value of the counter circuit, and a lower-performance inverter is sequentially used in accordance with an increase in the count value of the counter circuit. 7. The semiconductor integrated circuit according to claim 6, wherein: 11. The semiconductor integrated circuit according to claim 1, wherein said voltage supply means supplies a bias voltage by resistance division. 12. A first inverter having a feedback resistor connected in parallel thereto, and a second inverter connected in series to the first inverter and constituting a self-biased clock signal amplifier together with the first inverter. A first resistor connected between a bias voltage supply power supply and an input side of the first inverter; and a first resistor connected between an input side of the first inverter and a ground portion. 2
And at the time of startup by the AC signal source,
5. The power supply according to claim 1, wherein a voltage from said power supply for bias voltage supply is divided by said first and second resistors, and a bias voltage for steepening the rise of the voltage is supplied. A semiconductor integrated circuit according to any one of the above. 13. A counter circuit for performing a count operation of a clock signal generated by a self-biased clock signal amplifier constituted by first and second inverters, and a predetermined operation performed by the counter circuit. 11. The semiconductor integrated circuit according to claim 4, wherein said clock count number can be set. 14. A counter circuit for counting a clock signal generated by a self-biased clock signal amplifier comprising first and second inverters, and a counter circuit for performing a predetermined operation. 11. The semiconductor integrated circuit according to claim 4, further comprising a count number register for setting the clock count number.