JP2004221632A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of decreasing an oscillation start time not only at application of power but also even just after release of oscillation stop, and suppressing an unnecessarily consumed current. <P>SOLUTION: The oscillation circuit includes: an oscillation circuit body having an oscillation stop function; and a voltage application circuit for applying an intermediate voltage between a power level and a ground level to at least one part of internal nodes of the oscillation circuit body for a period of the oscillation stop of the oscillation circuit body by the oscillation stop function and applying no intermediate voltage thereto for a period when the oscillation stop is released. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillation circuit having an oscillation stop function.
[0002]
[Prior art]
For example, an oscillation circuit using a piezoelectric element such as a quartz oscillator is widely used as a reference clock generation circuit in the fields of communication equipment and video equipment. With the recent trend toward higher communication speeds and higher video quality, high-speed processing of large amounts of data has been demanded even in systems such as communication and video, and the oscillation frequency of the oscillator circuit has been gradually increasing. Tend to be.
[0003]
In an oscillation circuit using a crystal oscillator having very good frequency accuracy, a fundamental wave oscillation mode is usually used. However, in the fundamental wave vibration mode, at present, the oscillation frequency is limited to about 50 MHz due to the problem of the processing technology of the crystal resonator. Also, an oscillation frequency of 50 MHz is feasible but very expensive. For this reason, as a method for configuring a higher-frequency crystal oscillation circuit, there is a harmonic vibration mode in which the n-th harmonic (n = 3, 5, 7,...) Is oscillated.
[0004]
This overtone vibration mode utilizes the characteristic of the crystal resonator that converts physical vibration into an electric signal, and utilizes the characteristic that, in addition to the fundamental wave, the frequency component of the nth harmonic passes through the resonator. It is. The passing gain of each vibration mode is the highest for the fundamental wave, and gradually decreases as the harmonic becomes the third, fifth, seventh,... Further, in order to oscillate in the overtone vibration mode, it is necessary to select a frequency in the oscillation circuit.
[0005]
FIG. 3 is a schematic configuration diagram of an example of a conventional oscillation circuit. An oscillation circuit 50 shown in FIG. 1 is a third harmonic oscillation circuit, and includes an oscillation amplifier (NAND circuit) 16, a waveform shaping buffer 18, a feedback resistor (1MΩ) 20, a limiting resistor (100Ω) 22, , A crystal oscillator 24, a frequency adjustment capacitor (10 pF) 26, a DC cut capacitor (0.1 μF) 28, a filter capacitor (10 pF) 30, and a filter inductor (2 μH) 32.
[0006]
Here, an oscillation stop control signal EN is input to one input of the oscillation amplifier 16, and an output XO of the oscillation amplifier 16 is output as a signal OUT via a waveform shaping buffer 18. The feedback resistor 20 is connected between the other input XI of the oscillation amplifier 16 and the output XO. One terminal of the limiting resistor 22 is connected to the output XO of the oscillation amplifier 16, and the crystal oscillator 24 is connected between the other input XI of the oscillation amplifier 16 and the other terminal of the limiting resistor 22. The frequency adjustment capacitor 26 is connected between the other terminal of the limiting resistor 22 and the ground, and one terminal of the DC cut capacitor 28 is connected to the other input XI of the oscillation amplifier 16.
[0007]
The filter capacitor 30 and the filter inductor 32 are connected in parallel between the other terminal of the DC cut capacitor 28 and the ground. The filter capacitor 30 and the filter inductor 32 play a role of a high-pass filter 48 that blocks a fundamental wave of the crystal resonator 24. The values of the feedback resistor 20, the limiting resistor 22, the frequency adjustment capacitor 26, the DC cut capacitor 28, the filter capacitor 30, and the filter inductor 32 are merely examples, and the oscillation of the fundamental wave and the third harmonic of the crystal resonator 24 is performed. It is necessary to set appropriately according to the frequency.
[0008]
In the oscillation circuit 50, the crystal oscillator 24 outputs a sine wave of a predetermined frequency. When the power is on and the oscillation stop control signal EN is at a high level, the fundamental wave is cut off by the action of the filter capacitor 30 and the filter inductor 32, and the third harmonic is reduced by the feedback resistor 20, the limiting resistor 22, and the frequency adjusting capacitor 26. , The DC cut capacitance 28 and the oscillation amplifier 16 are amplified to a predetermined amplitude. Then, the waveform is shaped into a square wave by the waveform shaping buffer 18 and output as a signal OUT.
[0009]
When the power is on and the oscillation stop control signal EN is at a low level, the output of the NAND circuit serving as the oscillation amplifier 16 is at a high level, and the output OUT of the waveform shaping buffer 18 is also at a high level. At this time, the frequency adjustment capacitor 26 is charged up to the power supply voltage VDD via the limiting resistor 22, and the DC cut capacitor 28 is charged up to the power supply voltage VDD via the feedback resistor 20. When the power is off, the frequency adjustment capacitor 26 and the DC cut capacitor 28 are discharged.
[0010]
In the oscillation circuit 50, as shown in the timing chart of FIG. 4A, when transitioning from the power-off state to the power-on state, or as shown in the timing chart of FIG. At the time of transition from the oscillation stop state to the oscillation start state by the control of EN, it takes time to charge up or discharge the DC cut capacitor 28, so that the oscillation start time becomes longer. That is, when the power supply is turned on and immediately after the oscillation stop is released, the oscillation amplifier 16 is in the non-oscillation state until the voltage level of the other input XI becomes VDD / 2.
[0011]
There has been a problem that the non-oscillation state during this period may cause a serious error in a system using the output of the oscillation circuit as a reference clock, for example, a transfer error in a communication device or the like.
[0012]
In order to solve such a problem, FIG. 1 of Patent Document 1 discloses a crystal oscillation circuit to which a quick charging circuit is added in order to improve a starting characteristic. However, since the crystal oscillation circuit disclosed in FIG. 1 of Patent Document 1 does not have an oscillation stop function, consideration is given to power-on. However, this technique is applied to an oscillation circuit having an oscillation stop function. Even if it is applied, there is a problem that the oscillation start time immediately after the cancellation of the oscillation stop cannot be improved.
[0013]
FIG. 2 of Patent Document 1 also shows a crystal oscillator that uses an operational amplifier having a high gain and a low output impedance as an oscillation amplifier, provides a bias circuit at its non-inverting input terminal, and can arbitrarily set its operating point. A circuit is disclosed. However, the circuit shown in FIG. 2 has a problem that unnecessary current consumption always flows because the bias circuit is always connected. Further, like the circuit shown in FIG. There was a problem that the oscillation starting time immediately after the stop was canceled could not be improved.
[0014]
[Patent Document 1]
JP-A-57-24106
[Problems to be solved by the invention]
An object of the present invention is to solve the problems based on the above-described conventional technology, to shorten the oscillation start-up time not only at the time of power-on but also immediately after the oscillation stop is released, and to suppress unnecessary current consumption. It is an object of the present invention to provide an oscillation circuit that can be used.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the present invention includes an oscillation circuit body having an oscillation stop function, and a voltage supply circuit that generates an intermediate voltage between a power supply and a ground and supplies the intermediate voltage to the oscillation circuit body,
The voltage supply circuit supplies the intermediate voltage to at least one of the internal nodes of the oscillation circuit main body during a period in which the oscillation stop function stops the oscillation of the oscillation circuit main body, and a period in which the oscillation stop is released. The present invention provides an oscillation circuit characterized by not supplying the intermediate voltage.
[0017]
Here, the voltage supply circuit includes a power supply voltage detection circuit, and supplies the intermediate voltage until the power supply voltage reaches a predetermined voltage when the power supply transitions from power off to power on. After reaching a predetermined voltage, it is preferable not to supply the intermediate voltage.
[0018]
Alternatively, the voltage supply circuit includes a time detection circuit, and supplies the intermediate voltage for a predetermined fixed period when transitioning from power-off to power-on, and does not supply the intermediate voltage after the predetermined fixed period has elapsed. Is preferred.
[0019]
Further, it is preferable that the intermediate voltage supplied by the voltage supply circuit is a substantially central voltage between the power supply and the ground.
[0020]
Further, the oscillation circuit body includes an oscillation amplifier, a feedback resistor and a limiting resistor, a vibrator, a frequency adjustment capacitor and a DC cut capacitor,
An oscillation stop control signal is input to one input of the oscillation amplifier, the feedback resistor is connected between the other input and the output of the oscillation amplifier, and one terminal of the limiting resistor is an output of the oscillation amplifier. The oscillator is connected between the other terminal of the limiting resistor and the other input of the oscillation amplifier, and the frequency adjustment capacitor is connected between the other terminal of the limiting resistor and ground. Preferably, the DC cut capacitor is connected between the other input of the oscillation amplifier and ground.
[0021]
Further, it is preferable that the oscillation circuit body further includes a high-pass filter, and the high-pass filter is connected between the DC cut capacitor and a ground.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an oscillation circuit of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0023]
FIG. 1 is a schematic configuration diagram of an embodiment of the oscillation circuit of the present invention.
The oscillation circuit 10 shown in FIG. 1 includes an oscillation circuit body 12 having an oscillation stop function and a voltage supply circuit 14. That is, the oscillation circuit 10 of the present embodiment further includes the voltage supply circuit 14 as compared with the conventional oscillation circuit 50 shown in FIG. Therefore, the same reference numerals as those of the components of the conventional oscillation circuit 50 shown in FIG.
[0024]
That is, the oscillation circuit body 12 is a third harmonic oscillation circuit, and includes an oscillation amplifier (NAND circuit) 16, a waveform shaping buffer 18, a feedback resistor 20, a limiting resistor 22, a crystal oscillator 24, A frequency adjustment capacitor 26, a DC cut capacitor 28, a filter capacitor 30, and a filter inductor 32 are provided. The filter capacitance 30 and the filter inductor 32 play a role of a high-pass filter 48 that blocks a fundamental wave of the crystal resonator 24.
[0025]
The voltage supply circuit 14 applies the intermediate voltage between the power supply and the ground to the other input XI of the oscillation amplifier 16 during the transition from power-off to power-on and during the period when the oscillation circuit body 12 stops oscillating by the oscillation stop function. To supply. The voltage supply circuit 14 includes a P-type MOS transistor (hereinafter, referred to as PMOS) 34, an N-type MOS transistor (hereinafter, referred to as NMOS) 36, resistance elements 38 and 40, an inverter 42, an AND circuit 44, O. And a C (power-on-clear) circuit 46.
[0026]
Here, the AND circuit 44 has an oscillation stop control signal EN for instructing start and stop of oscillation, and a P.O. O. The output of the C circuit 46 is input, and the output of the AND circuit 44 is input to one input of the oscillation amplifier 16, the gate of the PMOS 34, and the inverter 42. The PMOS 34, the resistance elements 38 and 40, and the NMOS 36 are connected in series between the power supply and the ground, and the output of the inverter 42 is input to the gate of the NMOS 36. The node at the connection point between the resistance elements 38 and 40 is connected to the other input XI of the oscillation amplifier 16.
[0027]
Hereinafter, the operation when the power supply is turned on will be described. It is assumed that the oscillation stop control signal EN goes high as the power supply rises.
[0028]
P. O. The C circuit 46 constantly monitors the power supply voltage VDD. As shown in the timing chart of FIG. 2A, when the power is off, that is, when the power supply voltage VDD = 0V, the P.C. O. The output of the C circuit 46 is at a low level (ground level). When the power supply voltage VDD reaches a predetermined voltage, for example, a voltage level of VDD (maximum value) × 0.8 when the power supply is started, the P.V. O. The output of the C circuit 46 changes to a high level (VDD (maximum value) × 0.8 voltage level).
[0029]
Accordingly, the output of the AND circuit 44 is at a low level until the power supply voltage reaches a voltage level of VDD (maximum value) × 0.8 at the time of power-on, and the PMOS 34 and the NMOS 36 are simultaneously turned on.
[0030]
When both the PMOS 34 and the NMOS 36 are turned on, the voltage level at the connection point between the resistance elements 38 and 40 becomes a voltage level determined by the resistance division ratio of the resistance elements 38 and 40. For example, when the resistance values of the resistance elements 38 and 40 are equal, the voltage level at the connection point between the resistance elements 38 and 40 becomes a voltage level VDD / 2 substantially at the center between the power supply and the ground. Is applied to the other input XI of the oscillation amplifier 16.
[0031]
After that, O. When the output of the C circuit 46 goes high, the output of the AND circuit 44 also goes high, and both the PMOS 34 and the NMOS 36 are turned off. As a result, one input of the oscillation amplifier 16 becomes high level, and the supply of the voltage level of VDD / 2 from the voltage supply circuit 14 to the other input XI of the oscillation amplifier 16 is stopped. The oscillation operation is started with the voltage level of VDD / 2 supplied by the circuit 14 being maintained.
[0032]
Therefore, as shown in the timing chart of FIG. 2A, the oscillating operation of the other input XI of the oscillation amplifier 16 is started from the voltage level near VDD / 2, so that the DC cut capacitor 28 is charged up. The time can be shortened, and the oscillation starting time can be shortened. On the other hand, in the conventional oscillation circuit 50 shown in FIG. 3, as shown in the timing chart of FIG. 4A, the time for charging up the DC cut capacitor 28 is long, and the oscillation start time is also long.
[0033]
Next, the operation when the oscillation stop is released will be described. Note that the power is on, and O. It is assumed that the output of the C circuit 46 is always at the high level.
[0034]
As shown in the timing chart of FIG. 2B, the oscillation stop control signal EN is at a low level when the oscillation of the oscillation circuit body 12 is stopped, and is at a high level when the oscillation is started. Accordingly, the output of the AND circuit 44 is at a low level during the period when the oscillation of the oscillation circuit main body 12 is stopped by the oscillation stop function, and the PMOS 34 and the NMOS 36 are simultaneously turned on. Thus, in the present embodiment, for example, a voltage level of VDD / 2 is applied to the other input XI of the oscillation amplifier 16.
[0035]
Thereafter, when the oscillation stop control signal EN goes high, the output of the AND circuit 44 also goes high, and both the PMOS 34 and the NMOS 36 are turned off. As a result, one input of the oscillation amplifier 16 becomes high level, and the supply of the voltage level of VDD / 2 to the other input XI is stopped, but the input XI is supplied as shown in the timing chart of FIG. Then, the oscillating operation is started with the supplied voltage level of VDD / 2 maintained.
[0036]
For this reason, as shown in the timing chart of FIG. 2B, the time for discharging the DC cut capacitor 28 can be eliminated, and the oscillation starting time can be shortened. On the other hand, in the conventional oscillation circuit 50 shown in FIG. 3, as shown in the timing chart of FIG. 4B, the time for discharging the DC cut capacitor 28 is long, and the oscillation start time is also long.
[0037]
Here, the reason why the oscillation start-up time is increased is that, as described above, it takes time to charge up or discharge the DC cut capacitor 28 when the power is turned on and immediately after the oscillation stop is released. When the power supply is turned on, the DC cut capacitor 28 is charged up from the power supply via the oscillation amplifier 16 and the feedback resistor 20. Immediately after the oscillation stop is released, the current is discharged from the DC cut capacitor 28 to the ground via the feedback resistor 20 and the oscillation amplifier 16.
[0038]
For this reason, the oscillation start time is influenced by the RC time constant based on the resistance value R of the feedback resistor 20 having a relatively large value and the capacitance value C of the DC cut capacitor 28. Therefore, if the value of the resistance value R of the feedback resistor 20 or the value of the capacitance value C of the DC cut capacitor 28 is reduced, the charge-up time or the discharge time is reduced, and the oscillation start-up time is also reduced.
[0039]
However, simply reducing the circuit constant deteriorates other oscillation characteristics. For example, when the resistance value R of the feedback resistor 20 is reduced, adverse effects such as poor oscillation start-up, poor stability, and increased current consumption may occur. Further, when the capacitance value C of the DC cut capacitor 28 is reduced, the effect of the high-pass filter 48 for cutting off the fundamental wave is reduced, and abnormal oscillation (in this embodiment, fundamental wave oscillation) may occur. The margin will be reduced.
[0040]
On the other hand, in the oscillation circuit 10 of the present invention, when the power supply voltage reaches a predetermined voltage at the time of transition from power-off to power-on, and during the oscillation stop of the oscillation circuit body 12 by the oscillation stop function, By supplying a voltage level of VDD / 2 to the other input XI of the oscillation amplifier 16, the time required to charge up and discharge the DC cut capacitor 28 immediately after power-on and immediately after oscillation stop is released is reduced. .
[0041]
This makes it possible to speed up the voltage follow-up of the XI without deteriorating the characteristics of the high-pass filter 48 that blocks the fundamental wave, and without deteriorating the oscillation startup stability and the margin. As a result, the oscillation start time can be significantly reduced.
[0042]
In the above embodiment, the voltage supply circuit 14 outputs a low level until the power supply voltage reaches the predetermined voltage when the power supply transitions from power-off to power-on, and the power supply voltage has reached the predetermined voltage. P. output high level at the time O. Although an example in which the C circuit (power supply voltage detection circuit) 46 is provided has been described, the present invention is not limited to this. For example, a predetermined period is measured by a counter or the like when transitioning from power off to power on. The voltage supply circuit 14 may include a time detection circuit for supplying the intermediate voltage during the predetermined period.
[0043]
The oscillation amplifier 16 is not limited to the NAND circuit, and uses another multi-input CMOS logic gate according to the oscillation stop control signal EN, the output voltage of the power supply voltage detection circuit, and the polarity of the output of the time detection circuit. You can also. Further, the present invention is not limited to the third harmonic oscillation circuit, but is applicable to all fundamental and nth harmonic (n = 3, 5, 7,...) Oscillation circuits. Further, the vibrator is not limited to a quartz vibrator, and any conventionally known piezoelectric element such as a piezoelectric ceramic vibrator can be used.
[0044]
Further, the specific circuit configuration of the voltage supply circuit 14 is not limited at all, and an intermediate voltage between the power supply and the ground can be generated and supplied to at least one of the internal nodes of the oscillation circuit body 12. If possible. Also, when the power is turned on, P.P. O. The timing at which the output of the C circuit 46 changes from the low level to the high level is not limited to the voltage level of VDD (maximum value) × 0.8, and may be appropriately set as needed.
[0045]
The oscillation circuit of the present invention is basically as described above.
As described above, the oscillation circuit of the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the gist of the present invention. .
[0046]
【The invention's effect】
As described above in detail, the oscillation circuit of the present invention oscillates the intermediate voltage between the power supply and the ground during the oscillation stop of the oscillation circuit body having the oscillation stop function and the oscillation circuit body by the oscillation stop function. A voltage supply circuit that supplies the voltage to at least one of the internal nodes of the circuit body and does not supply the intermediate voltage while the oscillation stop is released.
Thus, according to the oscillation circuit of the present invention, the oscillation start time after the oscillation stop is released can be shortened without lowering the oscillation start stability and the margin.
In addition, the provision of the power supply voltage detection circuit and the time detection circuit can shorten the oscillation start-up time when the power supply is turned on. In addition, since there is no need to change the circuit of the oscillation circuit body, it is possible to realize a higher-quality, higher-frequency oscillation circuit with a higher degree of freedom in design, for example, by adding an overtone filter having a very large time constant. There are benefits.
Furthermore, since no current flows through the voltage supply circuit after the oscillation is started, there is a merit that unnecessary power consumption can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an embodiment of an oscillation circuit of the present invention.
FIGS. 2 (a) and 2 (b) are timing charts of an embodiment illustrating operations of the oscillation circuit shown in FIG. 1 when power is turned on and when oscillation stop is released, respectively.
FIG. 3 is a schematic diagram of an example of a conventional oscillation circuit.
4 (a) and 4 (b) are timing charts showing an example of operations of the oscillation circuit shown in FIG. 3 when power is turned on and when oscillation stop is released, respectively.
[Explanation of symbols]
10, 50 Oscillation circuit 12 Oscillation circuit body 14 Voltage supply circuit 16 Oscillation amplifier 18 Waveform shaping buffer 20 Feedback resistor 22 Limiting resistor 24 Crystal oscillator 26 Frequency adjustment capacitor 28 DC cut capacitor 30 Filter capacitor 32 Filter inductor 34 P-type MOS transistor 36 N-type MOS transistors 38, 40 Resistive element 42 Inverter 44 AND circuit 46 O. C circuit 48 High pass filter

Claims (6)

An oscillation circuit body having an oscillation stop function, and a voltage supply circuit that generates an intermediate voltage between a power supply and ground and supplies the intermediate voltage to the oscillation circuit body,
The voltage supply circuit supplies the intermediate voltage to at least one of the internal nodes of the oscillation circuit body during a period when the oscillation stop function stops the oscillation of the oscillation circuit body, and a period during which the oscillation stop is released. Is an oscillation circuit not supplying the intermediate voltage. The voltage supply circuit includes a power supply voltage detection circuit, and supplies the intermediate voltage until the power supply voltage reaches a predetermined voltage when the power supply transitions from power-off to power-on. 2. The oscillation circuit according to claim 1, wherein the intermediate voltage is not supplied after reaching the voltage. The voltage supply circuit includes a time detection circuit, and supplies the intermediate voltage for a predetermined fixed period when transitioning from power-off to power-on, and does not supply the intermediate voltage after the predetermined fixed period has elapsed. 2. The oscillation circuit according to 1. The oscillation circuit according to any one of claims 1 to 3, wherein the intermediate voltage supplied by the voltage supply circuit is a substantially central voltage between the power supply and the ground. The oscillation circuit body includes an oscillation amplifier, a feedback resistor and a limiting resistor, a vibrator, a frequency adjustment capacitor and a DC cut capacitor,
An oscillation stop control signal is input to one input of the oscillation amplifier, the feedback resistor is connected between the other input and the output of the oscillation amplifier, and one terminal of the limiting resistor is an output of the oscillation amplifier. The oscillator is connected between the other terminal of the limiting resistor and the other input of the oscillation amplifier, and the frequency adjustment capacitor is connected between the other terminal of the limiting resistor and ground. 5. The oscillation circuit according to claim 1, wherein the DC cut capacitor is connected between the other input of the oscillation amplifier and a ground. The oscillation circuit according to claim 5, wherein the oscillation circuit body further includes a high-pass filter, and the high-pass filter is connected between the DC cut capacitor and a ground.

Images