JPH11186848A - Oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit where a rise time of oscillation upon application of power is short, and an oscillation is maintained with reduced power consumption during steady-state operation is settled. SOLUTION: A counting means 60 is reset at the time of application of a power supply and a control signal CONT is set to 'L'. Thus, a PMOS 32 and an NMOS 42 are conductive, a voltage nearly equal to the difference between a power supply voltage VDD and the grounding level GND is applied to an inverter 10 and the oscillation is started. When an output signal OSC of the inverter 10 reaches a specified level, a pulse signal PLS from a Schmitt circuit 50 is given to a counting means 60. When the counted number of the pulse signals PLS reaches a specified volume, the control signal CONT of the counting means 60 is set to 'H' and the PMOS 32 and the NMOS 42 are nonconductive. Thus, a power supply voltage is applied to the inverter 10 via resistors 31, 41 and then the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit using a piezoelectric oscillator such as a quartz oscillator, and more particularly to an oscillation circuit having a short oscillation start time after power-on and low power consumption.

[0002]

2. Description of the Related Art Oscillation circuits used in portable devices such as portable telephones and portable personal computers use batteries as power sources, so that low power consumption is required.
FIG. 2 is a configuration diagram showing an example of a conventional low power consumption type oscillation circuit. This oscillation circuit uses a complementary MO as an amplifier.
An S (hereinafter referred to as “CMOS”) inverter 1 is used, and a feedback circuit including a crystal resonator 2 and a feedback resistor 3 connected in parallel is connected between the output side and the input side of the inverter 1. . Further, the input side and the output side of the inverter 1 are provided with capacitors 4 for stabilizing the oscillation operation, respectively.
5 is connected to one end of each of these capacitors 4, 5
Is connected to the ground potential GND. Inverter 1 is connected to power supply potential VD via current limiting resistors 6 and 7.
D and ground potential GND, these resistors 6, 7
The power supply current is supplied via the power supply.

[0005] A buffer amplifier 8 for outputting a stable oscillation signal OUT is connected to the output side of the inverter 1, and a circuit on the load side is connected via the buffer amplifier 8. When power is supplied to the oscillation circuit and the power supply potential VDD is applied, a relatively small power supply current is supplied to the inverter 1 via the resistors 6 and 7.
When the power supply current is supplied, the inverter 1 amplifies and outputs a minute voltage or the like given to the input side due to, for example, ambient thermal noise. Of the amplified various frequency components, only a specific natural frequency component of the feedback circuit composed of the crystal oscillator 2 and the feedback resistor 3 is positively fed back to the input side of the inverter 1 again. Output signal has an increased amplitude. The output signal of the inverter 1 is amplified by the buffer amplifier 8 and supplied to the load-side circuit as an oscillation signal OUT. By using the resistors 6 and 7 for limiting the power supply current of the inverter 1, power consumption of the oscillation circuit is reduced.

[0004]

However, the conventional oscillation circuit has the following problems (1) and (2). (1) The output signal of the inverter 1 is applied to the crystal unit 2 and is mechanically excited to oscillate a specific frequency. Therefore, in order to shorten the start-up time of the oscillation circuit, the inverter 1 having a large driving capability is required. In order to increase the drive capability of the inverter 1, it is necessary to increase the power supply current. However, in the conventional oscillation circuit, the power supply current is suppressed by the resistors 6 and 7 in order to reduce power consumption. Therefore, the stable oscillation signal OU
It took a long time before T was obtained. (2) The output signal of the inverter 1 is
Is supplied to the circuit on the load side, but until the stable oscillation signal OUT is obtained, a noise-like oscillation signal OUT having an unstable cycle may be output, and the circuit on the load side malfunctions. May be caused.

The present invention solves the above-mentioned problems (1) and (2) of the prior art, provides a short stabilization time of the oscillation operation at power-on, and generates a noise-like oscillation signal at the start of oscillation. An object of the present invention is to provide an oscillation circuit that does not output and can maintain stable oscillation operation by reducing power consumption after the oscillation operation is established.

[0006]

According to a first aspect of the present invention, there is provided an oscillator circuit comprising:
A logic gate driven by a drive voltage applied between a first power supply terminal connected to a first power supply potential and a second power supply terminal, inverting and amplifying a signal on an input side, and outputting the amplified signal to an output side;
Feedback means including a piezoelectric oscillator which is excited by an output signal of the logic gate and positively feedbacks a specific natural frequency component in the output signal to the input side of the logic gate; variable resistance means as described below; Trigger means, count means,
Output control means. The variable resistance means is connected between a second power supply potential and a second power supply terminal of the logic gate, and has a resistance controlled to a low resistance or a high resistance by a control signal. The Schmitt trigger means outputs a pulse signal at a first level when the output signal of the logic gate exceeds a first threshold voltage, and outputs the pulse signal at a second level lower than the first threshold voltage. When the voltage falls below the threshold voltage, the pulse signal is output to a second level different from the first level and output. The counting means counts the number of pulses of the pulse signal, and when the counted result is equal to or less than a predetermined number, controls the resistance value of the variable resistance means to have a low resistance, and the counted result indicates the predetermined number. When it exceeds, the control signal for controlling the resistance value of the variable resistance means to become high resistance is output. The output control means outputs an output signal of the Schmitt trigger means as an oscillation signal when the number of pulses of the pulse signal exceeds the predetermined number.

According to a second aspect of the present invention, in the oscillation circuit, the oscillation circuit is driven by a driving voltage applied between the first and second power supply terminals,
A logic gate for inverting and amplifying a signal on the input side and outputting the inverted signal to the output side, feedback means similar to the first invention, Schmitt trigger means, counting means, output control means, And second variable resistance means. The first variable resistance means is connected between a first power supply potential and a first power supply terminal of the logic gate, and has a resistance controlled to a low resistance or a high resistance by a control signal. The second variable resistance means is connected between a second power supply potential and a second power supply terminal of the logic gate, and has a resistance controlled to a low resistance or a high resistance by the control signal. is there. According to a third invention, a logic gate in the oscillation circuit according to the first and second inventions is controlled by an oscillation control signal, and when the oscillation control signal is activated, the logic gate is supplied between the first and second power supply terminals. When the oscillation control signal is inactivated, the inversion amplification operation is stopped when the signal on the input side is inverted and amplified by the driving voltage applied thereto and output to the output side.

According to the first aspect of the present invention, since the oscillation circuit is configured as described above, the following operation is performed. When the power is turned on, the first power supply potential is supplied to the first power supply terminal of the logic gate, and the second power supply potential is supplied to the second power supply terminal via the variable resistance means controlled to have a low resistance. You.
An output signal is output to the output side of the logic gate by the positive feedback operation of the feedback means connected to the input / output side of the logic gate, and when the amplitude of the output signal exceeds the first and second threshold voltages, Schmitt A pulse signal is output from the trigger means. The pulse signal is counted by the counting means, and when the count value exceeds a predetermined number, a control signal for controlling the resistance value to a high resistance is output from the counting means to the variable resistance means. As a result, the drive voltage applied to the logic gate decreases, and the power consumption of the logic gate decreases. Further, the output control means is controlled by the control signal, and the output signal of the Schmitt trigger means is output as an oscillation signal.

According to the second aspect, the following operation is performed. When the power is turned on, the first power supply potential is supplied to the first power supply terminal of the logic gate via the first variable resistance means controlled to have low resistance, and the second power supply terminal is controlled to have low resistance. The second power supply potential is supplied via the second variable resistance means. An output signal is output to the output side of the logic gate by the positive feedback operation of the feedback means connected to the input / output side of the logic gate, and when the amplitude of the output signal exceeds the first and second threshold voltages, Schmitt A pulse signal is output from the trigger means. The pulse signal is counted by the counting means, and when the count value exceeds a predetermined number, a control signal for controlling the resistance value to a high resistance from the counting means to the first and second variable resistance means. Is output. As a result, the drive voltage applied to the logic gate decreases, and the power consumption of the logic gate decreases.
Further, the output control means is controlled by the control signal, and the output signal of the Schmitt trigger means is output as an oscillation signal.

According to the third aspect, the following operation is performed. When the oscillation control signal is activated and the power is turned on, the same operation as in the oscillation circuits of the first and second inventions is performed, and the oscillation signal is output. When the oscillation control signal is deactivated in this state, the inverting amplification operation of the logic gate stops, and the output of the oscillation signal stops.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a configuration diagram of an oscillation circuit showing a first embodiment of the present invention. This oscillation circuit includes a logic gate (for example, CM
OS inverter) 10. Inverter 10
Are input terminal 11, output terminal 12, power supply terminal 13,
It is driven by a drive voltage applied to the power supply terminals 13 and 14, inverts and amplifies a signal supplied to the input terminal 11, and outputs the inverted signal to the output terminal 12. The output terminal 12 and the input terminal 11 of the inverter 10 are connected to feedback means (for example, a feedback circuit) composed of a piezoelectric oscillator (for example, a crystal oscillator) 21, a feedback resistor 22, and capacitors 23 and 24 for stabilizing the oscillation operation. ) 20 are connected. The feedback circuit 20 inverts the phase of a certain natural frequency component in the output signal OSC of the inverter 10 and
This is a circuit for forming a positive feedback loop by giving it to the input side of 0 and performing an oscillation operation at a constant frequency. The crystal oscillator 21 and the feedback resistor 22 are connected in parallel to the input terminal 11 and the output terminal 12 of the inverter 10. One end of each of the capacitors 23 and 24 is connected to the input terminal 11 and the output terminal 12 of the inverter 10, and the other end of each of the capacitors 23 and 24 is connected to the ground potential GND.

The power supply terminal 13 of the inverter 10 is connected to the power supply potential VDD via a first variable resistance means (for example, a variable resistance circuit) 30. The variable resistance circuit 30
It comprises a resistor 31 and a P-channel MOS transistor (hereinafter referred to as “PMOS”) 32 connected in parallel with the resistor 31. The PMOS 32 is turned on / off by a control signal CONT applied to the gate. The power supply terminal 14 of the inverter 10 is connected to the ground potential GND via a second variable resistance means (for example, a variable resistance circuit) 40. The variable resistance circuit 40 includes a resistor 41 and an N-channel MOS transistor (hereinafter, referred to as an N-channel MOS transistor) connected in parallel to the resistor 41.
“NMOS”) 42. NMOS 42
Is supplied with a control signal CONT via an inverter 43, and this control signal CONT causes N
The MOS 42 is controlled to be on / off.

An output terminal 12 of the inverter 10 is connected to an input side of a Schmitt trigger means (for example, a Schmitt circuit) 50. The Schmitt circuit 50 has a waveform shaping function. When the output signal OSC of the inverter 10 exceeds the threshold voltage Vt1, the Schmitt circuit 50 goes to, for example, a level “H”, and the output signal OSC becomes the threshold voltage Vt2 (Vt
2 <Vt1), and outputs a pulse signal PLS which becomes level "L" when the voltage falls to 2 <Vt1) or less.

On the output side of the Schmitt circuit 50, a counting means 6 composed of a counter 61 and a set / reset type flip-flop (hereinafter referred to as "FF") 62.
0 is connected. The counter 61 receives the pulse signal PL
It has a clock terminal C to which S is applied, a reset terminal R to which a reset signal RST is applied, and an output terminal O. The counter 61 has a function of counting the number of pulses of the pulse signal PLS supplied to the clock terminal C, and outputting an overflow signal OVF from the output terminal O when the count value reaches a predetermined number. Counter 6
1 is connected to the set terminal S of the FF 62. Further, a reset signal RST is supplied to a reset terminal R of the FF 62. FF62
When the overflow signal OVF is supplied to the set terminal S, the control signal CONT outputted to the output terminal Q becomes “H”, and when the reset signal RST is supplied to the reset terminal R, the control signal CONT becomes “L”. It can be switched. Control signal CO output from FF62
NT is provided to the variable resistance circuits 30 and 40. Further, the control signal CONT is output from an output control means (for example, a two-input AND gate, hereinafter, “AND”).
) 70 is connected to the first input terminal. AN
A pulse signal S50 from the Schmitt circuit 50 is supplied to a second input terminal of D70. AND70 is
This is a gate circuit for outputting the pulse signal PLS as an oscillation signal OUT to a circuit on the load side when the control signal CONT is "H".

FIG. 3 is a signal waveform diagram showing the operation of FIG. The operation of the oscillation circuit of FIG. 1 will be described with reference to FIG. At time t0 in FIG. 3, when the power is turned on and the power supply potential VDD is applied, the counter 61 and the F
F62 is in a reset state, the count value of the counter 61 is 0, and the control signal CON output from the FF62 is
T is "L". Therefore, the variable resistance circuit 30
And the PMOS in the variable resistance circuit 40
42 is in an ON state, and the resistors 31 and 41 are in a short-circuited state. As a result, the power supply terminals 13 and 14 of the inverter 10 substantially have the power supply potential VDD,
A power supply voltage of the ground potential GND is applied. These power supply potential VCC and ground potential GND are connected to inverter 1
When supplied to 0, the inverter 10 starts an amplifying operation, amplifies and outputs a minute voltage or the like given to the input side due to noise at power-on or ambient thermal noise. Among the amplified various frequency components, the crystal oscillator 21 and the feedback resistor 2
2 and a feedback circuit 2 composed of capacitors 23 and 24
Only the specific natural frequency component of 0 is fed back to the input side of the inverter 10 again, so that the amplitude of the output signal OSC gradually increases.

At time t1, when the peak voltage of the output signal OSC exceeds the threshold voltage Vt1 and reaches an amplitude such that the bottom voltage becomes equal to or lower than the threshold voltage Vt2, the output of the pulse signal PLS from the Schmitt circuit 50 starts. Is done. Pulse signal PL output from Schmitt circuit 50
S is counted by the counter 61. At time t2, when the count value of the counter 61 reaches a predetermined value,
The overflow signal O output from the counter 61
VF becomes “H”. When the overflow signal OVF becomes “H”, the FF 62 is set, and the control signal CONT output from the FF 62 is
It becomes "H". When the control signal CONT becomes “H”, the PMOS 32 in the variable resistance circuit 30 and the variable resistance circuit 4
Each of the PMOSs 42 within 0 changes to the off state.
Thereby, the power supply terminals 13 and 14 of the inverter 10
They are connected to the power supply potential VDD and the ground potential GND via the resistors 31 and 41, respectively.

Thus, the power supply terminal 1 of the inverter 10
Although the drive voltage applied between the terminals 3 and 14 decreases, the resistance value of the resistors 31 and 41 is set to an appropriate value so that the oscillation operation of the inverter 10 does not stop, so that the necessary minimum value can be obtained. The oscillation operation can be continued at the amplitude of. On the other hand, the output signal OSC of the inverter 10 is applied to the second input terminal of the AND 70 after the waveform is shaped by the Schmitt circuit 50. Therefore, at time t2, when the control signal CONT becomes “H”, the AND70
Pulse signal PLS supplied to the second input terminal of
Is output from the output side of the AND 70 as an oscillation signal OUT.

As described above, in the first embodiment,
There are the following advantages (i) and (ii). (I) When the amplitude of the output signal OSC of the inverter 10 exceeds a predetermined value, the pulse signal PLS whose waveform has been shaped
Circuit 50 for outputting the pulse signal PL
When a predetermined number of S have been output, a variable resistance circuit 3 for lowering the drive voltage applied to the inverter 10
It has 0,40. As a result, at the start of oscillation,
By driving the inverter 10 with a high drive voltage, a stable oscillation output can be obtained in a short time, and after stable oscillation is obtained, the stable oscillation can be maintained with low power consumption. (Ii) An AND 70 that supplies a pulse signal PLS from the Schmitt circuit 50 as an oscillation signal OUT to a circuit on the load side by a control signal CONT output when stable oscillation is obtained. As a result, the unstable output signal OSC immediately after the start of the oscillation is not output as the oscillation signal OUT, and malfunction in the circuit on the load side can be prevented.

Second Embodiment FIG. 4 is a block diagram of an oscillator circuit according to a second embodiment of the present invention, in which components common to those in FIG. 1 are denoted by common reference numerals. In the oscillation circuit of the second embodiment, the inverter 10 in the oscillation circuit of the first embodiment shown in FIG.
Instead of a two-input NAND gate (hereinafter referred to as “NA
ND ”). NAND10A
Has an output terminal 12 and power supply terminals 13 and 14 similar to those of the inverter 10 in addition to having first and second input terminals 11a and 11b. The feedback circuit 20 is connected to the output terminal 12 and the input terminal 11a.

On the other hand, the input terminal 11b is connected to the NAND 10
Oscillation control signal ACT for controlling the inverting amplification operation of A
Is given. That is, the oscillation control signal A
When CT is “H”, NAND 10A is connected to inverter 1
The same operation as 0 is performed. When the oscillation control signal ACT is "L", the output signal of the output terminal 12 of the NAND 10A is fixed at "H", and the inversion amplification operation by the NAND 10A is stopped. Further, this oscillation circuit includes an inverter 81 for inverting the oscillation control signal ACT, and a two-input OR gate (hereinafter, referred to as “OR”) for outputting a logical sum of an output signal of the inverter 81 and a reset signal RST. 82. The output side of the OR 82 is connected to the counter 61 and the reset terminal R of the FF 62.

Other configurations are the same as those in FIG. In such an oscillation circuit, the operation when the oscillation control signal ACT changes from “H” or “L” to “H” is the same as the operation of the first embodiment. In contrast,
When the oscillation control signal ACT changes from “H” to “L”,
When the operation of the NAND 10A stops and the counter 6
1 and the FF 62 are reset and the control signal CONT becomes “L”, so that the oscillation signal OUT output from the AND 70 is immediately stopped.

As described above, in the second embodiment,
A two-input NAND 10A is used as a logic gate, and an oscillation control signal ACT is connected to a second input terminal of the NAND 10A.
To give. Thus, in addition to the advantages (i) and (ii) of the first embodiment, the oscillation control signal ACT
The oscillation operation can be freely controlled by
For example, by stopping the oscillation operation in a standby state of a mobile phone or the like, there is an advantage that power consumption can be further reduced.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (e). (A) Although the quartz oscillator 21 is used, a piezoelectric oscillator such as a ceramic oscillator may be used. (B) The feedback circuit 20 is not limited to the circuits shown in FIGS. 1 and 4. For example, it is also possible to use a feedback circuit that can control the load capacitance by voltage control and change the oscillation frequency. .

(C) Although two variable resistance circuits 30 and 40 are provided, one of the variable resistance circuits 30 and 40 may be omitted. In this case, the omitted power supply terminals 13 and 14 are connected to the power supply potential VDD or the ground potential GND.
Just connect directly to. By doing so, the control signal C
Since the average voltage of the output signal OSC fluctuates due to the ONT, the amplitude of the output signal OSC cannot be extremely reduced in order to maintain stable oscillation, but there is an advantage that the circuit configuration can be simplified. (D) Although the control logic of the variable resistance circuits 30, 40, the counting means 60, and the like has been described as positive logic, the PMOS 32, NM
By changing the polarity of the OS 42 or the like, a negative logic may be used. (E) The counting means 60 includes the counter 61 and the FF 62
The control signal CON is not limited to the combination of the control signals CON when the pulse signal PLS is counted and reaches a predetermined number of pulses.
Anything that outputs T can be used.

[0025]

As described above in detail, according to the first aspect, the resistance between the power supply terminal of the logic gate and the power supply potential is controlled so as to be small at the time of startup and to be large after stable oscillation is established. Variable resistance means. This allows
After the stable oscillation operation has been established, the oscillation operation can be continued with reduced power consumption. In addition, after the predetermined pulse signal is output, the output control means for outputting the pulse signal as an oscillation signal is provided, so that an unstable oscillation signal at the time of starting is not output, and the load-side circuit Malfunction can be prevented.

According to the second aspect, the resistance value between the first and second power supply terminals of the logic gate and the first and second power supply potentials is small at the time of startup, and is large after stable oscillation is established. And first and second variable resistance means for controlling the resistance. As a result, the average potential of the output signal output from the logic gate can be kept constant, and in addition to the effect of the first invention, there is an effect that a stable operation with lower power consumption can be maintained. . According to the third aspect, since the logic gate whose inversion amplification operation is controlled by the oscillation control signal is used, oscillation can be freely controlled in addition to the effects of the first and second aspects. Therefore, for example, there is an effect that power consumption in a standby state of a mobile phone or the like can be further reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an oscillation circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an example of a conventional oscillation circuit.

FIG. 3 is a signal waveform diagram showing the operation of FIG.

FIG. 4 is a configuration diagram of an oscillation circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 inverter 10A NAND 20 feedback circuit 21 crystal oscillator 22 feedback resistor 30, 40 variable resistor circuit 50 Schmitt circuit 60 counting means 61 counter 62 FF 70 AND

Claims (3)

[Claims] 1. A drive circuit is driven by a drive voltage applied between a first power supply terminal connected to a first power supply potential and a second power supply terminal, inverts and amplifies a signal on an input side, and outputs the signal on an output side. A logic gate that is excited by an output signal of the logic gate, and a feedback unit that includes a piezoelectric oscillator that positively feeds back a specific natural frequency component in the output signal to an input side of the logic gate; A variable resistance means connected between the logic gate and a second power supply terminal of the logic gate, the resistance value of which is controlled to a low resistance or a high resistance by a control signal; When the pulse signal exceeds the first threshold voltage, the pulse signal is output to a first level, and when the output signal falls below a second threshold voltage lower than the first threshold voltage, the pulse signal is output to the first level. Schmitt output to a different second level Triggering means, counts the number of pulses of the pulse signal, and controls the resistance value of the variable resistance means to have a low resistance when the counting result is equal to or less than a predetermined number, and the counting result indicates the predetermined number. Counting means for outputting the control signal for controlling the resistance value of the variable resistance means to have a high resistance when the pulse number exceeds the predetermined value; and the Schmitt when the number of pulses of the pulse signal exceeds the predetermined number. An oscillation circuit, comprising: output control means for outputting an output signal of the trigger means as an oscillation signal. 2. A logic gate driven by a drive voltage applied between first and second power supply terminals, inverting and amplifying a signal on an input side and outputting the signal to an output side; and a logic gate excited by an output signal of the logic gate. Feedback means including a piezoelectric oscillator for positively feeding back a specific natural frequency component in the output signal to the input side of the logic gate; and between a first power supply potential and a first power supply terminal of the logic gate. A first variable resistance means having a resistance value controlled to a low resistance or a high resistance by a control signal; a first variable resistance means connected between a second power supply potential and a second power supply terminal of the logic gate; A second variable resistance means whose resistance value is controlled to a low resistance or a high resistance by a signal; and outputting a pulse signal to a first level when an output signal of the logic gate exceeds a first threshold voltage. , The output signal being the first threshold voltage A Schmitt trigger for outputting the pulse signal at a second level different from the first level when the voltage drops below a second threshold voltage, which is lower than the first threshold voltage, and counting the number of pulses of the pulse signal, When the result is equal to or less than a predetermined number, control is performed so that the resistance values of the first and second variable resistance means become low resistance, and when the count result exceeds the predetermined number, the first and second variable resistance means are controlled. Counting means for outputting the control signal for controlling the resistance value of the variable resistance means to have a high resistance; and output of the Schmitt trigger means when the number of pulses of the pulse signal exceeds the predetermined number. An output control means for outputting a signal as an oscillation signal. 3. The logic gate is controlled by an oscillation control signal, and when the oscillation control signal is activated, the logic gate is driven by a drive voltage applied between the first and second power supply terminals to generate an input-side signal. Is inverted and amplified and output to the output side,
3. The oscillation circuit according to claim 1, wherein the inversion amplification operation is stopped when the oscillation control signal is deactivated.