JPH02274103A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPH02274103A JPH02274103A JP9792689A JP9792689A JPH02274103A JP H02274103 A JPH02274103 A JP H02274103A JP 9792689 A JP9792689 A JP 9792689A JP 9792689 A JP9792689 A JP 9792689A JP H02274103 A JPH02274103 A JP H02274103A
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- circuit
- section
- output
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 107
- 238000001514 detection method Methods 0.000 claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 230000010356 wave oscillation Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
- H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
- H03B2200/006—Functional aspects of oscillators
- H03B2200/0082—Lowering the supply voltage and saving power
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
- H03B2200/006—Functional aspects of oscillators
- H03B2200/0094—Measures to ensure starting of oscillations
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は発振回路（・二関電−１特にガ作および停止を
頻繁に繰りヌす発振回路に関する
〔従来の技術〕
従来、この種の発振回路は、第２図に示すように、水晶
振動子ＸＬと第１の容量Ｃ７と第２の容量Ｃ２とを備え
る入力部］と、ＮＡＮＤ回路２１よりなるインバータと
抵［Ｒ＋ とを備える第１の発振部２とを僅えて構成さ
れ、外部からの発振制御信号の入力端子６に高レベルの
発振制御信号ＯＣ４が入力されろと発振し、入力端子６
に低レベルの発振制御信号ＱＣ，が入力されると発振が
停止するようになっていた
〔発明が解決しようヒする課題〕
上述した従来の発振回路は、発振部が１個で構成されて
いるので、電源電子が低い時から高い時まで高調波発振
を防止し５、消費電流を小さくすることが非常に困鞄で
あるという欠点がある〔課題を解決するための手段〕
本発明の発振回路（士、水晶振動子と第１の容量と第２
の容量とをｆ萌える入力部と、増幅回路の出力を前記入
力部に正帰還し第１の発振制御信号に応じて発振の起動
及び停止を行う第１の発振部と、増幅回路の出力を前記
入力部に正帰還し第２の発振制御信号に応じて発振の起
動及び停止を行う第２の発振部と、前記第１の発振部と
第２の発振部の出力を入力とし該出力を検出して発振検
出信号を出力する発振検出回路と、前記発振検出信号と
外部から供給される前記第１の発振制御信号を入力とし
前記第２の発振制御信号を出力するＡＮＤ回路とを含ん
で構成される７
０実施例ご
次に、本発明について図面を参照して説明する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an oscillation circuit (Ni-Kanden-1), especially an oscillation circuit that frequently repeats operation and stop [Prior Art] Conventionally, this type of oscillation As shown in FIG. 2, the circuit includes an input section including a crystal resonator XL, a first capacitor C7, and a second capacitor C2, and a first section including an inverter including a NAND circuit 21 and a resistor R+. It oscillates when a high-level oscillation control signal OC4 is input to the input terminal 6 of the oscillation control signal from the outside, and the input terminal 6
The oscillation is stopped when a low-level oscillation control signal QC is input to the oscillation circuit. [Problem to be solved by the invention] The conventional oscillation circuit described above is composed of one oscillation section. Therefore, the oscillation circuit of the present invention has the disadvantage that it is extremely difficult to prevent harmonic oscillation from low to high power supply voltage and to reduce current consumption.[Means for Solving the Problems] The oscillation circuit of the present invention (The crystal oscillator, the first capacitor, and the second
an input section that positively feeds the output of the amplifier circuit to the input section and starts and stops oscillation in accordance with a first oscillation control signal; a second oscillation section that provides positive feedback to the input section and starts and stops oscillation in accordance with a second oscillation control signal; an oscillation detection circuit that detects and outputs an oscillation detection signal; and an AND circuit that receives the oscillation detection signal and the first oscillation control signal supplied from the outside and outputs the second oscillation control signal. 70 Embodiments Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.
第１図に示すように、本実施例は水晶振動子ＸＬと？Ａ
ｌの容量Ｃ１と第２の容量Ｃ２とを備える入力部１と、
２人力ＮＡＮＤ回路２１と抵抗Ｒ７とを備える第１の発
振部２と、クロックドインバータ３１と抵抗Ｒ２とを備
える第２の発振部３と、インバータ４１とバイナリフリ
ップフロップとう・ソチ回路とを備える発振検出回路４
と、ＡＮＤ回路５とを含んで構成される。As shown in FIG. 1, this embodiment uses a crystal resonator XL? A
an input section 1 comprising a capacitor C1 of l and a second capacitor C2;
A first oscillation section 2 including a two-power NAND circuit 21 and a resistor R7, a second oscillation section 3 including a clocked inverter 31 and a resistor R2, and an inverter 41 and a binary flip-flop circuit. Oscillation detection circuit 4
and an AND circuit 5.
第１図において１発振部２は２人力ＮＡＮＤ回路２１と
正帰還用の抵抗Ｒ１にて構成され、抵抗Ｒ２は２人力Ｎ
ＡＮＤ回１ｉＩ８２１の一方の入力端と出力端の間に接
続されることにより発振部２は増幅回路として動作する
。又、２人力ＮＡＮＤ回路２１の他の入力端には入力端
子６から入力される外部からの第１の発振制御信号Ｃ○
１が入力され発振制御が行われ、発振制御信号ＣＯ＋が
高レベル入力で発振開始し、低レベル入力で発振停止と
なる。In FIG. 1, one oscillation section 2 is composed of a two-man powered NAND circuit 21 and a resistor R1 for positive feedback, and the resistor R2 is composed of a two-man powered NAND circuit 21 and a positive feedback resistor R1.
The oscillation section 2 operates as an amplifier circuit by being connected between one input terminal and the output terminal of the AND circuit 1iI821. Moreover, the first oscillation control signal C○ from the outside input from the input terminal 6 is input to the other input terminal of the two-manpower NAND circuit 21.
When 1 is input, oscillation control is performed, and when the oscillation control signal CO+ is input at a high level, oscillation starts, and when input at a low level, oscillation is stopped.
同様に、発振部３はクロックドインバータ３１と正帰還
用の抵抗Ｒ２にて構成され、抵抗Ｒ２はクロックドイン
バータ３１の入力端と出力端の間に接続されることによ
り発振部３は増幅回路として動作する。又、クロックド
インバータ３１のイネーブル端子にはＡＮＤ回路５から
の出力の第２のＱ振制御信号ＯＣ２が入力されて発振制
御が行われ、発振制御信号ＯＣ２が高レベル入力で発振
開始し、低レベル入力で発振停止となる。ここで発振部
３にＮＡＮＤ河路を用いないのは、発振停止時にフロー
ティング出力とするためである、発振検出回路４は発振
部２及び発振部３の出力をインバータ４１に入力し、そ
の出力をバイナリフリップフロップのクロック入力端へ
入力する。Similarly, the oscillation section 3 is composed of a clocked inverter 31 and a positive feedback resistor R2, and the resistor R2 is connected between the input end and the output end of the clocked inverter 31, so that the oscillation section 3 is configured as an amplifier circuit. operates as Further, the second Q oscillation control signal OC2 output from the AND circuit 5 is input to the enable terminal of the clocked inverter 31 to perform oscillation control, and when the oscillation control signal OC2 is input at a high level, it starts oscillating and when it is at a low level. Oscillation stops with level input. The reason why the NAND channel is not used in the oscillation section 3 is to provide a floating output when the oscillation is stopped.The oscillation detection circuit 4 inputs the outputs of the oscillation sections 2 and 3 to the inverter 41, and outputs the output from the oscillation section 3. Input to the clock input terminal of the binary flip-flop.
発振検出図′Ｉ＠４のインバータ４１のしきい電圧は、
発振検出の精度を向上させるため発振部２及び発振部３
のしきい電圧とは２００ ｍＶ以上離して設定する 又
、バイナリフリップフロップにて３回カウントしその出
力をラッチ回路にてラッチし発振検出信号としている。The threshold voltage of the inverter 41 in the oscillation detection diagram 'I@4 is
In order to improve the accuracy of oscillation detection, the oscillation unit 2 and the oscillation unit 3 are
The threshold voltage is set at least 200 mV.Also, a binary flip-flop is used to count three times, and the output is latched by a latch circuit to be used as an oscillation detection signal.
ＡＮＤ回路５は発振検出回路４の出力と外部からの発振
制御信号○Ｃ２を入力とｉ−５その出力の発振制御信号
ＯＣ２を発振部３のクロックドインバータ３１のイネー
ブル端子へ入力する又、発振部２の２人力Ｎ Ａ Ｎ
Ｄ回路２１の他方の入力端には入力端子６からの発振制
御信号○Ｃ７が入力される。The AND circuit 5 inputs the output of the oscillation detection circuit 4 and the oscillation control signal ○C2 from the outside, and inputs the output oscillation control signal OC2 to the enable terminal of the clocked inverter 31 of the oscillation section 3. Part 2 2-man power N A N
The oscillation control signal ○C7 from the input terminal 6 is input to the other input terminal of the D circuit 21.
いま、発振制御信号ＯＣ７が低レベルの時は、発振部２
及び発振部３は１！振せず、かつ、発振検出回路４の内
部のバイナリフリ・ツブフロ・ツブの出力は低レベルと
なっている。Now, when the oscillation control signal OC7 is at a low level, the oscillation section 2
And the oscillation part 3 is 1! There is no oscillation, and the output of the binary free-tube flow-tube inside the oscillation detection circuit 4 is at a low level.
次に、発振制御信号ＯＣ１が高レベルとなり発振開始を
指示すると、発振部２及び発振部３がアクティブとなり
、外部取付は部品の水晶振動子Ｘｔ、と容量Ｃ１，Ｃ２
により構成される入力部１の発振定数にしたがった発振
動作が開始される。Next, when the oscillation control signal OC1 becomes high level and instructs to start oscillation, the oscillation units 2 and 3 become active, and the externally mounted parts include the crystal resonator Xt and the capacitors C1 and C2.
An oscillation operation is started according to the oscillation constant of the input section 1 configured by the following.
発振部２及び発振部３の出力は徐々にレベルを上昇し、
所定時間経過後その振幅は電源電圧レベルにまで達する
。その振幅を発振検出図Ｆｌ＠ ４のインバータ４１が
検出し、バイナリフリップフロップの出力が最初低レベ
ルであったのが高レベルとなりその出力をラッチ回路に
てラッチする、即ち、発振検出回路４は発振回路が動作
し発振が安定したと判断する。従って、ＡＮＤ回路５か
らの発振制御信号ＯＣ２により発振部３が切離される。The outputs of the oscillation units 2 and 3 gradually increase in level,
After a predetermined period of time, the amplitude reaches the power supply voltage level. The inverter 41 of the oscillation detection circuit Fl@4 detects the amplitude, and the output of the binary flip-flop, which was initially low level, becomes high level and the output is latched by the latch circuit, that is, the oscillation detection circuit 4 It is determined that the oscillation circuit is operating and oscillation is stable. Therefore, the oscillation section 3 is disconnected by the oscillation control signal OC2 from the AND circuit 5.
グ発明の効果で
以上説明したように本発明は、発振検出して発振部の規
模を小さくすることにより、消費電流を小さくし、発振
部の利得も下がることから２高周波発振を防止できる効
果がある。As explained above in the Effects of the Invention, the present invention detects oscillation and reduces the size of the oscillation unit, thereby reducing current consumption and reducing the gain of the oscillation unit, which has the effect of preventing two high frequency oscillations. be.
第１図は本発明の一実施例の回路図、第２図は従来の発
振回路の一例のｌ’ｊＦｌ路図である。
１・・・入力部、２．３・・・発振部、４・・・発振検
出回路、５・・・ＡＮＤ回路、６・・・入力端子、２１
・・・２人力ＮＡＮＤ回路、３１・・・クロックドイン
バータ、４１ ・・・インバータ、Ｃ＋、Ｃ２−容量、
ＯＣ。
ＯＣ２・・・発振制御信号、Ｒ，、Ｒ２・・・抵抗、Ｘ
Ｌ・・水晶振動子６
代理入 弁理士 内 原 晋FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an l'jFl path diagram of an example of a conventional oscillation circuit. DESCRIPTION OF SYMBOLS 1... Input part, 2.3... Oscillation part, 4... Oscillation detection circuit, 5... AND circuit, 6... Input terminal, 21
... 2-person NAND circuit, 31 ... Clocked inverter, 41 ... Inverter, C+, C2- capacity,
O.C. OC2...Oscillation control signal, R,, R2...Resistance, X
L...Crystal unit 6 Patent attorney Susumu Uchihara
Claims (1)
と、増幅回路の出力を前記入力部に正帰還し第１の発振
制御信号に応じて発振の起動及び停止を行う第１の発振
部と、増幅回路の出力を前記入力部に正帰還し第２の発
振制御信号に応じて発振の起動及び停止を行う第２の発
振部と、前記第１の発振部と第２の発振部の出力を入力
とし該出力を検出して発振検出信号を出力する発振検出
回路と、前記発振検出信号と外部から供給される前記第
１の発振制御信号を入力とし前記第２の発振制御信号を
出力するＡＮＤ回路とを含むことを特徴とする発振回路
。an input section including a crystal resonator, a first capacitor, and a second capacitor; a first section that positively feeds back the output of the amplifier circuit to the input section and starts and stops oscillation in accordance with a first oscillation control signal; an oscillation section, a second oscillation section that positively feeds back the output of the amplifier circuit to the input section and starts and stops oscillation according to a second oscillation control signal; an oscillation detection circuit that receives the output of the oscillation section and detects the output and outputs an oscillation detection signal; and a second oscillation control circuit that receives the oscillation detection signal and the first oscillation control signal supplied from the outside as input. An oscillation circuit comprising: an AND circuit that outputs a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9792689A JPH02274103A (en) | 1989-04-17 | 1989-04-17 | Oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9792689A JPH02274103A (en) | 1989-04-17 | 1989-04-17 | Oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02274103A true JPH02274103A (en) | 1990-11-08 |
Family
ID=14205287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9792689A Pending JPH02274103A (en) | 1989-04-17 | 1989-04-17 | Oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02274103A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04200009A (en) * | 1990-11-29 | 1992-07-21 | Toshiba Corp | Oscillator circuit |
| JPH07154143A (en) * | 1993-11-26 | 1995-06-16 | Nec Corp | Oscillating circuit |
| US6133801A (en) * | 1996-04-23 | 2000-10-17 | Nec Corporation | Crystal oscillation circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51123044A (en) * | 1975-04-21 | 1976-10-27 | Hitachi Ltd | Starting circuit in the oscillation circuit |
| JPS5364454A (en) * | 1976-11-22 | 1978-06-08 | Seiko Epson Corp | Oscillator circuit |
| JPS5441058A (en) * | 1977-09-08 | 1979-03-31 | Citizen Watch Co Ltd | Crystal oscillator circuit |
| JPS63172505A (en) * | 1987-01-09 | 1988-07-16 | Mitsubishi Electric Corp | Cmos gate array osclllation circuit device with oscillation stop function |
-
1989
- 1989-04-17 JP JP9792689A patent/JPH02274103A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51123044A (en) * | 1975-04-21 | 1976-10-27 | Hitachi Ltd | Starting circuit in the oscillation circuit |
| JPS5364454A (en) * | 1976-11-22 | 1978-06-08 | Seiko Epson Corp | Oscillator circuit |
| JPS5441058A (en) * | 1977-09-08 | 1979-03-31 | Citizen Watch Co Ltd | Crystal oscillator circuit |
| JPS63172505A (en) * | 1987-01-09 | 1988-07-16 | Mitsubishi Electric Corp | Cmos gate array osclllation circuit device with oscillation stop function |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04200009A (en) * | 1990-11-29 | 1992-07-21 | Toshiba Corp | Oscillator circuit |
| JPH07154143A (en) * | 1993-11-26 | 1995-06-16 | Nec Corp | Oscillating circuit |
| US6133801A (en) * | 1996-04-23 | 2000-10-17 | Nec Corporation | Crystal oscillation circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5113156A (en) | Low power crystal oscillator with automatic gain control | |
| KR100313725B1 (en) | Oscillator circuit containing a noise prevention circuit | |
| US4387350A (en) | Watch circuit with oscillator gain control | |
| US11082006B2 (en) | Low power crystal oscillator | |
| US4864255A (en) | Oscillator capable of quickly supplying a stable oscillation signal | |
| JPH0416963B2 (en) | ||
| US4196404A (en) | Crystal oscillator having low power consumption | |
| JP4598992B2 (en) | Crystal oscillation circuit | |
| US4459565A (en) | Low current electronic oscillator system | |
| JPH02274103A (en) | Oscillation circuit | |
| GB2102991A (en) | Reference pulse generator | |
| JP2000013143A (en) | Oscillation circuit | |
| US5220291A (en) | Complementary transistor oscillator | |
| JP3255581B2 (en) | Oscillator circuit | |
| US11876486B1 (en) | Low power crystal oscillator | |
| JPH05303656A (en) | Oscillation circuit | |
| JPS6359106A (en) | Pulse generating circuit | |
| JPH0722245B2 (en) | Oscillator circuit | |
| KR940006602Y1 (en) | Circuit for controlling power of electronic circuit | |
| JPH0697732A (en) | Oscillation circuit | |
| KR910000192B1 (en) | Voltage controled oscillator using mos | |
| JPH0553402B2 (en) | ||
| CN117200704A (en) | Low power crystal oscillator with automatic amplitude control | |
| JPH04208701A (en) | Operation stabilizing method for oscillator | |
| JPH02228107A (en) | Bias source circuit and oscillating circuit of gate type linear amplifier |