JPH07193428A - Integrated circuit for oscillation and oscillator circuit - Google Patents

Abstract

PURPOSE:To improve oscillation start, to suppress the deterioration of the duty of the oscillation output at the time of steady state oscillation and to reduce current consumption. CONSTITUTION:The change circuit 7 receiving the output of the detector circuit 6 detecting an oscillation initial state lowers the inversion potential of an inverter 1, increases mutual conductance and makes oscillation easy. Because the inversion potential is lowered than the inversion potential of an inverter 5 at this time, the output of the inverter 5 is held at an 'H'. When an oscillation detector circuit 6 detects a steady state oscillation, the change circuit 7 is interrupted from an oscillation part OSC and the oscillation of the oscillation part itself is performed. At this time, the inversion potential of the CMOS inverter 1 of the oscillation part OSC and the inversion potential of the CMOS inverter 5 for output buffer are equal, the duty of oscillation output is not deteriorated and current consumption is also suppressed. Because sufficient negative resistance can be obtained at the oscillation initial state, the feedback resistance 3 of a low value can be used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation integrated circuit and an oscillation circuit.

[0002]

2. Description of the Related Art Conventionally, in an oscillation integrated circuit and an oscillation circuit in which a piezoelectric oscillator such as a crystal oscillator is connected between the input and output of a CMOS inverter, when the oscillation output is sent to the subsequent stage, the piezoelectric oscillator is connected. The second CMOS inverter is connected to the output of the CMOS inverter
The latter stage circuit is connected to the output of the CMOS inverter. In such a case, the oscillation output having a small amplitude in the initial stage of oscillation is inverted by the second CMOS inverter,
This output puts the latter-stage circuit in an operating state, but generally, the inversion potentials of these two CMOS inverters are set equal to each other, and noise generated in the latter-stage circuit makes the small-amplitude oscillation operation unstable. For this reason, attempts have been made to stabilize the oscillation output in the initial stage of oscillation, and such an example is disclosed in Japanese Patent Laid-Open No. 4-273602. As shown in A of FIG. 7, this is because the crystal unit QZ1 and the feedback resistor R1 are connected between the input / output terminals of the first CMOS inverter IV1 having the load capacitors C1 and C2 connected to the input / output terminals. The second CMOS inverter IV2 is connected to the output terminal of the CMOS inverter IV1. Here, the inversion potential of the first CMOS inverter IV1 is, as shown in B of FIG.
5v, and the inversion potential of the second CMOS inverter IV2 is 2.0v as shown in C of FIG. Oscillation starts, and the first CMOS inverter IV1
Oscillation output changes as shown in A of FIG. here,
The amplitude of this oscillation output gradually increases, but the second CMO
Until the inversion potential of the S inverter IV2 is exceeded, the second C
The output of the MOS inverter IV2 is held at a low level as shown in B of FIG. Therefore, the small-amplitude oscillation output in the initial stage of oscillation is not output to the subsequent circuit, and the first CMO
The oscillation output of the S inverter IV1 can be stably increased without being affected by noise generated in the subsequent circuit.

[0003]

However, the inversion potential of the first CMOS inverter IV1 and the second CMOS inverter IV1
If it is different from that of the inverter IV2, the duty of the output during steady oscillation cannot be set to 1/2 as shown in B of FIG.

Further, in the prior art, in order to shorten the oscillation start time, it is common to increase the negative resistance by increasing the transconductance of the first CMOS inverter IV1. Increasing the mutual conductance of the CMOS inverter IV1 of No. 1 causes an increase in current consumption.

An object of the present invention is to provide an oscillation integrated circuit and an oscillation circuit capable of improving the oscillation startability, suppressing the deterioration of the duty of the oscillation output during steady oscillation, and reducing the current consumption. Especially.

[0006]

A CMOS inverter,
An oscillating unit including a feedback resistor connected in parallel to the CMOS inverter and a load capacitance connected to each of the input terminal and the output terminal of the CMOS inverter is provided, and a piezoelectric vibrator is externally attached to the oscillating unit. In an integrated circuit for oscillation used as an oscillation detection circuit, an oscillation detection circuit that detects an initial state of oscillation of the oscillation unit and a change circuit that changes the inversion potential and the transconductance of the CMOS inverter according to the output of the oscillation detection circuit are provided. To have.

Also, a CMOS inverter and this CMO
A piezoelectric vibrator connected between the input and output of the S inverter, a feedback resistor connected in parallel to the CMOS inverter,
In an oscillation circuit including an oscillation section including load capacitors connected to the input terminal and the output terminal of the CMOS inverter, an oscillation detection circuit for detecting an initial state of oscillation of the oscillation section, and an oscillation detection circuit of the oscillation detection circuit. And a change circuit for changing the inversion potential and the transconductance of the CMOS inverter according to the output.

The above object is achieved by the above.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an oscillation integrated circuit according to an embodiment of the present invention will be described. FIG. 1 is an electric circuit diagram showing the configuration of this example. In the figure, 1 is a CMOS inverter, and the inversion potential is VTM (for example, the power source V of the CMOS inverter 1).
When the voltage of DD is 5v, it is 2.5v. ). Also, the input terminal IN of this CMOS inverter 1
A capacitor 2 as a load capacitance is connected to each of 1 and the output terminal OUT1. 3 is a feedback resistor, CM
Input terminal IN1 and output terminal OUT1 of the OS inverter 1
Connected between and. These CMOS inverter 1,
The load capacitance 2 and the feedback resistor 3 constitute the oscillator OSC. 4 is a crystal oscillator as a piezoelectric oscillator,
It is externally attached between the input terminal IN1 and the output terminal OUT1 of the S inverter 1.

Reference numeral 5 denotes a CMOS inverter for an oscillation buffer, which sends the oscillation output of the oscillation section OSC to a subsequent circuit (not shown).

An oscillation detection circuit 6 detects the initial state of oscillation of the oscillator OSC. This oscillation detection circuit 5 has a C
MOS inverters iv0 to iv3 and N-channel type M
It is composed of an OS transistor tr0, a resistor r0, and a capacitor c0. The CMOS inverter iv0 is set to an inversion potential VTH higher than the inversion potential VTM (2.5v) of the CMOS inverter 1. In addition, the CMOS inverter i
v1 is for waveform shaping and output stabilization for receiving the output of the CMOS inverter iv0. The MOS transistor tr0 has a drain connected to the power source VDD (5
v) and the gate receives the output of the CMOS inverter iv1 to be turned on and off to change the potential of the connection point VB with the resistor r0. The capacitance element c0 has one terminal connected to the connection point VB between the MOS transistor tr0 and the resistor r0 and the other terminal connected to the power supply VDD, and delays the rise of the potential change at the connection point VB. The CMOS inverter iv2 has an input terminal connected to the connection point VB, and outputs an output to a change circuit described later according to the potential of the connection point VB. CMOS inverter iv3 is C
The output of the MOS inverter iv2 is received, and the output obtained by inverting this output is output to the changing circuit. Where CMOS
The output from the inverter iv2 and the CMOS inverter i
The inverted output from v3 is output to the changing circuit described later and used as a detection signal of the initial state of oscillation. As will be described later, in the initial state of oscillation, the CMOS inverter iv2 outputs "L" and the CMOS inverter iv3 outputs "H".

Reference numeral 7 is a change circuit, which changes the inversion potential and the transconductance of the CMOS inverter 1 according to the output of the oscillation detection circuit 6. The changing circuit 6 is composed of N-channel type MOS transistors tr1 to tr3. The drain and source of the MOS transistor tr1 are connected to the output terminal OUT1 of the CMOS inverter 1 and the power supply VSS (0v), respectively. The source and drain of the MOS transistor tr2 are the gate of the MOS transistor tr1 and the input terminal I of the CMOS inverter 1, respectively.
It is connected to N1 and the gate has a CMO of the oscillation detection circuit 6.
The output of the S inverter iv3 is received and turned on and off. M
The drain and source of the OS transistor tr3 are connected to the gate of the MOS transistor tr1 and the power supply VSS, respectively, and the gate receives the output of the CMOS inverter iv2 of the oscillation detection circuit 6 and is turned on and off. As will be described later, in the oscillation initial state, the MOS transistor tr2 and tr3 are turned on and off, respectively, by receiving the output from the change circuit 5, so that the MOS transistor tr is turned on.
1 operates to change the inversion potential and transconductance of the CMOS inverter 1. Conversely, in the steady oscillation state, M
Since the OS transistors tr2 and tr3 are turned off and on, respectively, the MOS transistor tr1 is turned off and cut off from the oscillation unit OSC.

The above configuration is integrated on a common substrate except for the crystal oscillator 4, but the present invention is not limited to this, and the load capacitance 2 and the feedback resistor 3 may be externally attached and various changes are made. It is possible.

Next, the operation of this example will be described with reference to the waveform chart of FIG. First, in the initial state of oscillation immediately after the power is turned on, the CMOS inverter 1 produces an oscillation output with a minute amplitude. This oscillation output is output to the CMOS inverter 5 for the output buffer and the CM of the oscillation detection circuit 6
It is output to the OS inverter iv0. The inversion potential VTH of the CMOS inverter iv0 is set higher than the inversion potential VTM of the CMOS inverter 1. At this time, the amplitude potential of the oscillation output is lower than the inversion potential VTH, and as shown in iv0 of FIG. Output "H". As a result, the CMOS inverter iv1 outputs "L" and the MOS transistor tr0 is turned off. Therefore, as shown by VB in FIG. 2, the connection point VB is held at "H", and "L" and "H" are output to the changing circuit 7 from the CMOS inverters iv2 and iv3, respectively. In the modification circuit 7 which receives the output of the oscillation detection circuit 6, the MOS transistor tr2 has a gate having the CMOS inverter iv.
The MOS transistor tr3 receives the output "H" from 3 and turns on, and the MOS transistor tr3 receives the output from the CMOS inverter iv2 on its gate and turns off. Here, the ON resistance of the MOS transistor tr2 is set to a value sufficiently smaller than that of the feedback resistor 3, and the signal input to the input terminal IN1 of the CMOS inverter 1 is the MOS transistor tr1.
Input to the gate. This makes CMOS equivalent
The inversion potential VTM of the inverter 1 is changed to a value VTL lower than this, and the transconductance increases. This increases the negative resistance of the CMOS inverter 1 and facilitates oscillation. Also, in this oscillation initial state, the CMO
The S inverter 1 oscillates around the inverted potential VTL as shown by OUT1 in FIG. Here, the inversion potential of the CMOS inverter 5 for the output buffer is set to VTM.
Then, as shown by OUT5 in FIG. 2, the output terminal OUT5 of the CMOS inverter 5 is held at “H”, and the CMO
The oscillation output from the S inverter 1 is not output to the subsequent circuit, and the CMOS inverter 1 can perform stable oscillation operation without being affected by the subsequent circuit.

As described above, when the oscillation output of the CMOS inverter 1 gradually increases from the oscillation initial state and exceeds the inversion potential VTM of the CMOS inverter 5, the CMOS inverter 5 generates an oscillation output as shown by OUT5 in FIG. Begin to. Then, the oscillation output of the CMOS inverter 1 is the inversion potential V of the CMOS inverter iv0 of the oscillation detection circuit 6.
When it exceeds TH, the output of the CMOS inverter iv0 becomes “L”, the output of the CMOS inverter iv1 becomes “H”, the MOS transistor tr0 is turned on, and the connection point V
The potential of B drops. When the oscillation output of the CMOS inverter 1 becomes equal to or lower than the inversion potential VTH of the CMOS inverter iv0 again, the MOS transistor tr0 is turned off and the potential of the connection point VB rises, but its rise is delayed by the capacitance element c0 and the resistor r0. Next, when the oscillation output of the CMOS inverter 1 exceeds the inversion potential VTH, the potential at the connection point VB is set so as not to become the original potential. Therefore, the oscillation output of the CMOS inverter 1 increases, and the potential at the connection point VB gradually decreases every time the inversion potential VTH is exceeded. As the amplitude of the oscillation output of the CMOS inverter 1 increases in this way, the potential of the connection point VB becomes lower than the inversion potential VTM of the CMOS inverter iv2 of the oscillation detection circuit 6 as shown at the timing th of VB in FIG. When it becomes “L”, the CMOS inverter i
v2 and iv3 will output "H" and "L", respectively. That is, this output causes the operation of the oscillator OSC to shift from the initial oscillation state to the steady oscillation state. In the change circuit 7 which receives the output of the oscillation detection circuit 6 as described above, the MOS transistors tr2 and tr3 are turned off and on, respectively, and the MOS transistor tr3 is turned on, whereby the MOS transistor tr1 is turned off and the CMOS inverter 1 is turned on. The inversion potential of VTM becomes
The mutual conductance is reduced, and the steady oscillation is performed only by the oscillator OSC. In this steady oscillation state, the inversion potentials of the CMOS inverter 1 of the oscillator OSC and the CMOS inverter 5 for the output buffer both match at VTM, so that the deterioration of the duty of the oscillation output sent to the subsequent circuit can be avoided. . Further, since the transconductance of the CMOS inverter 1 is reduced, the consumption current is suppressed as compared with the initial oscillation state.

As described above, in the present example, in the initial oscillation state, the inversion potential of the CMOS inverter 1 of the oscillator OSC is lowered and the mutual conductance is increased to increase the negative resistance and oscillate. Make it easier to do. At this time, the inversion potential is made lower than the inversion potential VTM of the CMOS inverter 5 for the output buffer.
Since the output of the inverter 5 is held at “H” and the oscillation output is not output to the post-stage circuit, the CMOS inverter 1 can perform stable oscillation operation without being affected by the post-stage circuit. In the steady oscillation state, the oscillator OSC
Since the inversion potentials of the CMOS inverter 1 and the CMOS inverter 5 for the output buffer both match in VTM, the deterioration of the duty of the oscillation output sent to the subsequent circuit can be avoided. Further, since the mutual conductance of the CMOS inverter 1 is reduced as compared with the initial state of oscillation, current consumption can be suppressed. Since a sufficient negative resistance is obtained in the initial state of oscillation, the feedback resistance 3 having a lower value than that of the conventional one can be used, and the current consumption can be suppressed.

The present invention is not limited to the above-mentioned one embodiment but can be variously modified. For example, it can be changed as shown in FIG. Also in FIG.
The same numbers as in the above indicate the same components. this is,
The MOS transistor tr2 of the modification circuit 7 of the above embodiment
Instead of the above, a transmission gate g is used. Reference numeral 8 denotes a modification circuit. Here, the output of the CMOS inverter iv3 of the oscillation detection circuit 6 is connected to the gate of the N-channel type MOS transistor g0 which constitutes the transmission gate g, and the transmission gate g
The output of the CMOS inverter iv2 of the oscillation detection circuit 6 is connected to the gate of the P-channel type MOS transistor g1 constituting the above. Even in this case, the same operation and effect are exhibited by the same operation as that of the above-mentioned one embodiment.

It is also possible to change it as shown in FIG. Also in this figure, the same numbers as in FIG. 1 indicate the same components. In this case, instead of the changing circuit 7 of the above-described embodiment, a changing circuit 9 composed of N-channel type MOS transistors tr4, 5 is used. This change circuit 9 is configured as follows. First, the drain of the MOS transistor tr4 is connected to the output terminal OUT1 of the CMOS inverter 1, and the oscillation detection circuit 6 is connected to its gate.
The output of the CMOS inverter iv3 is connected. M
The drain of the MOS transistor tr5 is connected to the source of the OS transistor tr4. The power supply VSS is connected to the source of the MOS transistor tr5, and the input terminal IN1 of the CMOS inverter 1 is connected to the gate thereof. The oscillation detection circuit 10 used here has the same components as the oscillation detection circuit 6 shown in the example of FIG.
Unlike the oscillation detection circuit 6, the output from the CMOS inverter iv2 is not directly sent to the change circuit. In this example, in the initial state of oscillation, the output of the CMOS inverter iv3 causes M
The OS transistor tr4 is turned on, and the same signal as the signal input to the input terminal IN1 of the CMOS inverter 1 at the gate of the MOS transistor tr5 is input to the gate of the MOS transistor tr5, which is the same as the case of FIG. , The inversion potential and the transconductance of the CMOS inverter 1 are changed, and the same effect as that of the example of FIG. 1 is obtained.

In each of the above-mentioned embodiments, the CMOS
Instead of directly connecting the crystal unit 4 and the load capacitor 2 to the output terminal of the inverter 1, they may be connected via a limiting resistor (for example, about 6 KΩ). By doing so, the load on the CMOS inverter 1 is reduced, and it is possible to reduce power consumption. For example, the circuit configuration shown in the example of FIG. 1 can be modified as shown in FIG. In the figure, the same numbers as those shown in FIG. 1 indicate the same components, and the limiting resistor RD is connected to the output terminal OUT1 of the CMOS inverter 1.
The crystal unit 4 and the capacitor 2 are connected via the limiting resistor RD. The drain of the MOS transistor tr1 of the changing circuit 7 is connected between the limiting resistor RD and the connection point Vqc of the load capacitance 2 and the crystal oscillator 4.

Further, in each of the above-described embodiments, a P-channel type M transistor is used instead of the N-channel type MOS transistor.
An OS transistor may be used. For example, the circuit configuration shown in the example of FIG. 1 can be modified as shown in FIG. In the figure, the same numbers as in FIG. 1 indicate the same components. N-channel type MOS transistor tr
P-channel type MOS transistors tr'0 to tr'3 are used instead of 0 to tr3. In this case, the power supply VSS
Power supply VDD (for example, 5v) instead of (0v)
Connect to the source of S-transistor and power VDD (5v)
Power source VSS (0v) instead of the resistor r of the oscillation detection circuit 6
0 and the capacitive element c0. Where 1
Reference numerals 1 and 12 are an oscillation detection circuit and a change circuit, respectively. Even in this case, the same action and effect are exhibited by the same operation as that of the example of FIG.

In each of the above embodiments, the crystal oscillator is used as the piezoelectric oscillator, but the piezoelectric oscillator is not limited to this. For example, a PZT-based or PbTiO ₃ -based ceramic oscillator may be used. Good.

[0022]

According to the present invention, there is provided an oscillation integrated circuit and an oscillation circuit capable of improving the oscillation startability, suppressing the deterioration of the duty of the oscillation output during the steady oscillation, and reducing the current consumption. It becomes possible to provide.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of FIG.

FIG. 3 is an electric circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is an electric circuit diagram showing the configuration of a third embodiment of the present invention.

FIG. 5 is an electric circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 6 is an electric circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 7 is an electric circuit diagram showing a configuration of a conventional oscillator circuit.

FIG. 8 is a waveform diagram for explaining the operation of FIG. 7.

[Explanation of symbols]

 1 CMOS Inverter 2 Load Capacitance 3 Feedback Resistor 4 Crystal Oscillator (Piezoelectric Oscillator) OSC Oscillator 6 Oscillation Detection Circuit 7 Change Circuit 8 Change Circuit 9 Change Circuit 10 Oscillation Detection Circuit 11 Oscillation Detection Circuit 12 Change Circuit

Claims (2)

[Claims] 1. A CMOS inverter, a feedback resistor connected in parallel to the CMOS inverter, and the CMOS.
An oscillation integrated circuit, comprising an oscillating unit composed of load capacitors connected to the input terminal and the output terminal of the inverter, respectively, wherein a piezoelectric vibrator is externally attached to the oscillating unit. An oscillation integrated circuit comprising: an oscillation detection circuit that detects an initial state; and a change circuit that changes the inversion potential and the transconductance of the CMOS inverter according to the output of the oscillation detection circuit. 2. A CMOS inverter, a piezoelectric vibrator connected between the input and output of the CMOS inverter, and the C
In an oscillation circuit including an oscillation unit composed of a feedback resistor connected in parallel to a MOS inverter and a load capacitance connected to each of the input terminal and the output terminal of the CMOS inverter, the initial state of oscillation of the oscillation unit is An oscillation circuit comprising: an oscillation detection circuit for detecting; and a change circuit for changing the inversion potential and the transconductance of the CMOS inverter according to the output of the oscillation detection circuit.