JP2585147B2 - Oscillation control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation control circuit.

[0002]

2. Description of the Related Art When transmitting the oscillation output of a crystal oscillation circuit using CMOS transistors to a subsequent circuit, an output CMOS inverter is used as an output of an oscillation CMOS inverter constituting the oscillation circuit.
An S inverter is connected, and a subsequent circuit is connected to the output of the output CMOS inverter. Conventionally, in this type of circuit, the inverted potentials of both CMOS inverters are the same.

[0003]

In the above conventional circuit,
The oscillation output with very small amplitude at the start of oscillation is the output CMO
The output is inverted by the S inverter, and the inverted circuit puts the subsequent circuit into an operating state. Therefore, the oscillation operation becomes unstable due to the influence of noise generated in the subsequent circuit, and there is a problem that the transition from the oscillation operation with a small amplitude to the oscillation operation with a normal amplitude is prevented.

An object of the present invention is to provide an oscillation control circuit in which a post-stage circuit does not operate at a minute amplitude at the start of oscillation, and the post-stage circuit starts operating after the amplitude becomes a certain value or more. .

[0005]

According to the present invention, there is provided an oscillation control circuit comprising: a pair of power supply lines; a first CMOS inverter; and a crystal resonator connected between an output terminal and an input terminal of the first CMOS inverter. And the first C
A second CMOS inverter for inputting an oscillation signal output from the MOS inverter; a second CMOS inverter connected between a source of at least one of N-channel and P-channel transistors constituting the second CMOS inverter and at least one of the power supply lines; The control MOS transistor and the oscillating potential of the oscillating signal are the first CM
From the first reference potential lower than the inversion potential of the OS inverter
Or the oscillation potential of the oscillation signal
A second reference higher than the inversion potential of the first CMOS inverter
And an operation control circuit for holding the control MOS transistor in the off state until the potential becomes higher than the potential . Also,
An output control circuit for short-circuiting the output of the second CMOS inverter to one of the power supply lines when the control MOS transistor is off may be provided.

[0006]

Embodiment 1 FIG. 1 shows a first embodiment of the oscillation control circuit according to the present invention.

[0007] The CMOS inverter IV0 is shown in FIG.
And its inversion potential (logic threshold voltage) is 2.5 volts.
The inversion potential referred to here is an input voltage at the midpoint between the falling start input voltage and the falling end input voltage in the input / output characteristics. Usually, the output voltage is the power supply voltage (5 volts).
Is the input voltage at half (2.5 volts). QZ
Is a crystal oscillator, R1 is a feedback resistor, and C1 and C2 are capacitors. An oscillation circuit is configured by the above circuit elements.

[0008] The CMOS inverter IV1 is shown in FIG.
And its inversion potential is 2.0 volts. In each embodiment, such C
For MOS inverters, “L” is added to the inverter symbol. The CMOS inverter IV2 has input / output characteristics as shown in FIG. 2C, and its inverted potential is 3.0 volts. In each embodiment, such a CMOS inverter is denoted by “H” as an inverter symbol. In addition,
In each of the embodiments, unless otherwise indicated, “L” or “H” is used for the inverter symbol unless otherwise specified.
Like the OS inverter IV0, it has input / output characteristics (transfer characteristics) as shown in FIG. 2A, and its inversion potential (logic threshold voltage) is 2.5 volts. In addition, other gate circuits and the like that substantially function as inverters have input / output characteristics (transfer characteristics) as shown in FIG. The threshold voltage is 2.5 volts. IV3 and IV
4 is a CMOS inverter, and ND1 is a CMOS NAND gate. The capacitor C3 is a CMOS NAND gate N
Although it is connected between the output of D1 and the power supply (5 volts), it is not always necessary (operations with and without connection will be described later). These CMOS inverters IV1, IV2, IV3, IV
4. CMOS NAND gate ND1 and capacitor C3
Thus, the operation control circuit OPC is configured.

IV5 is a CMOS inverter, T11 and T12 are N-channel MOS transistors, T13 and T14 are P-channel MOS transistors,
These circuit elements form a CMOS clocked inverter. A post-stage circuit LA is connected to the output of the CMOS clocked inverter.

N-channel MOS transistor T15
When the logic output value of the CMOS inverter IV4 is "1", the output of the CMOS inverter formed by the MOS transistors T12 and T13 is short-circuited.

The gate circuit such as the inverter, the MOS transistor, and the subsequent circuit LA shown in FIG.
It is stored in a C chip.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described with reference to the time chart shown in FIG. FIG. 3 shows a case where the capacitor C3 is not connected to the NAND gate ND1.
FIG. 4 shows a case where the capacitor C3 is connected to the NAND gate ND1. FIGS. 3A, 3C and 3D
Correspond to points "a", "c" and "d" in FIG. 1, respectively, and FIGS. 4A, 4B, 4C and 4D correspond to "a", "b" in FIG. , "C" and "d" points respectively.

First, the capacitor C is connected to the NAND gate ND1.
3 will be described.

As shown in FIG. 3A, an oscillation signal having a small amplitude is generated from the CMOS inverter IV0 when the power is turned on. Although the amplitude of the oscillation signal gradually increases, when the oscillation potential is between the inversion potential of the CMOS inverter IV1 (2.0 volts) and the inversion potential of the CMOS inverter IV2 (3.0 volts), the CMOS The logical output value of inverter IV1 is "0", and the logical output value of CMOS inverter IV2 is "1". The output logic value of the NAND gate ND1 is "0", and the logic output value of the CMOS inverter IV4 is "1". Therefore, MO
S transistors T11 and T14 are turned off,
C composed of MOS transistors T12 and T13
The MOS inverter becomes inactive. At this time MOS
Since the transistor T15 is on, the output of the CMOS inverter including the MOS transistors T12 and T13 is short-circuited through the MOS transistor T15. As described above, when the oscillation potential of the oscillation signal is CMOS
The MOS transistors T12 and T13 are configured until the potential becomes lower than the inverted potential (2.0 volts) of the inverter IV1 or the oscillation potential of the oscillation signal becomes higher than the inverted potential (3.0 volts) of the CMOS inverter IV2. CMOS inverter is held in a non-operating state, and its logical output value is held at "0".

When the oscillation potential of the oscillation signal exceeds the inversion potential of the CMOS inverter IV1 (2.0 volts) or the inversion potential of the CMOS inverter IV2 (3.0 volts), the logical output value of the CMOS inverter IV4 becomes "0". Becomes As a result, MOS transistors T12 and T1
For the first time, the CMOS inverter constituted by 3 becomes active, and at the same time, the MOS transistor T15 is turned off. Thereafter, according to the oscillation signal generated from the CMOS inverter IV0, as shown in FIG. 3C, the logical value "0" and "1" are alternately output from the CMOS inverter IV4. When the logical output value of the CMOS inverter IV4 is "0", the oscillation signal generated from the CMOS inverter IV0 becomes the MOS signal as shown in FIG.
CMOS composed of transistors T12 and T13
Inverted by inverter. The inverted circuit (clock signal) puts the subsequent circuit LA into an operating state. Noise is generated by the operation of the post-stage circuit LA. At this time, since the amplitude of the oscillation signal is sufficiently large,
The oscillation operation is not hindered.

Next, the operation when the capacitor C3 is connected to the NAND gate ND1 will be described.

When the oscillation potential of the oscillation signal generated from CMOS inverter IV0 exceeds the inversion potential (2.0 volts) of CMOS inverter IV1 or the inversion potential (3.0 volts) of CMOS inverter IV2, NAND gate N is activated.
The output of D1 starts an inversion operation. At this time, the value of the capacitor C3 and each MO constituting the NAND gate ND1 are
By appropriately selecting the value of the ON resistance of the S transistor, the output of the NAND gate ND1 becomes as shown in FIG. That is, the charging time constant and the discharging time constant for the capacitor C3 are selected to appropriate values. As a result, the logical output value of CMOS inverter IV4 is
As shown in (C), “0” is kept held. As shown in FIG. 4D, a clock signal having a duty of 50% can be output from the CMOS inverter including the MOS transistors T12 and T13.

In this embodiment, the MOS transistor T
Although 15 is configured with an N-channel type, it may be configured with a P-channel type by using a logical value opposite to the logical output value of the CMOS inverter IV4.

Embodiment 2 FIG. 5 shows a second embodiment of the oscillation control circuit according to the present invention.

In this embodiment, the clocked inverter (CMOS inverter IV) in the first embodiment (see FIG. 1) is used.
5, the functions of the MOS transistors T11, T12, T13 and T14) and the short-circuit MOS transistor T15 are represented by NAND gates (N
Channel MOS transistors T21 and T22, P
This is replaced by the function of the channel MOS transistors T23 and T24), and the first half of the circuit is the same as that of the first embodiment shown in FIG. Therefore, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Input / output characteristics (transfer characteristics) of each inverter
Is also shown in FIG. 2 as in the first embodiment. Other gate circuits and the like that substantially function as inverters have input / output characteristics (transfer characteristics) as shown in FIG. 2A unless otherwise specified, and have inverted potentials (logic thresholds). Voltage) is 2.5 volts. The meanings of the symbols “L” and “H” attached to the inverter symbols are the same as those described in the first embodiment. 3 and FIG. 4 can also be used for the time chart. FIG. 3 shows a case where the capacitor C3 is not connected to the NAND gate ND1, and FIG. 4 shows a case where the capacitor C3 is connected to the NAND gate ND1. That is, FIGS. 3 (A), (C) and (D) correspond to points “a”, “c” and “d” in FIG. 5, respectively, and FIGS. 4 (A), (B), (C) and (D)
Correspond to points “a”, “b”, “c” and “d” in FIG. 5, respectively.

The gate circuit such as the inverter, the MOS transistor, and the subsequent circuit LA shown in FIG.
It is stored in a C chip.

Next, the operation of this embodiment will be described by taking as an example a case where the capacitor C3 is not connected to the NAND gate ND1. The description of the same operation as in the first embodiment is omitted.

When the oscillation potential of the oscillation signal output from CMOS inverter IV0 is between the inverted potential of CMOS inverter IV1 (2.0 volts) and the inverted potential of CMOS inverter IV2 (3.0 volts), CMO
The logical output value of the S inverter IV4 is "1", and the logical output value of the CMOS inverter IV6 is "0". Therefore, MOS transistor T21 is turned off, and MOS transistor T24 is turned on. As a result, the output of the CMOS inverter constituted by the MOS transistors T22 and T23 is short-circuited through the MOS transistor T24. As described above, the oscillation potential of the oscillation signal is CMO
Until the inverted potential of the S inverter IV1 becomes lower than 2.0 volts, or until the oscillation potential of the oscillation signal becomes higher than the inverted potential of the CMOS inverter IV2 (3.0 volts), the MOS transistors T22 and T23 are used. CMOS inverter is kept inactive,
The logical output value is held at "1".

When the oscillation potential of the oscillation signal exceeds the inversion potential of the CMOS inverter IV1 (2.0 volts) or the inversion potential of the CMOS inverter IV2 (3.0 volts), the logic output value of the CMOS inverter IV4 becomes "0". ,
The logical output value of the CMOS inverter IV6 is "1". Therefore, MOS transistor T21 is turned on, and MOS transistor T24 is turned off. As a result, the CMOS inverter constituted by MOS transistors T22 and T23 is activated for the first time. The subsequent operation is basically the same as the operation described in the first embodiment, and the description is omitted.

The capacitor C is connected to the NAND gate ND1.
The operation when 3 is connected can be easily analogized from the above description and the like, and a description thereof will be omitted.

Embodiment 3 FIG. 6 shows a third embodiment of the oscillation control circuit according to the present invention.

This embodiment is similar to the clocked inverter (CMOS inverter IV) in the first embodiment (see FIG. 1).
5, the NOR gates (N-channel MOS transistors T31 and T32, P-channel MOS transistors T33 and T34) which have the functions of the MOS transistors T11, T12, T13 and T14 and the short-circuit MOS transistor T15 surrounded by a dashed line in FIG. The first half of the circuit is the same as that of the first embodiment shown in FIG. Therefore, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The input / output characteristics (transfer characteristics) of each inverter are also shown in FIG. 2 as in the first embodiment. Other gate circuits and the like that substantially function as inverters have input / output characteristics (transfer characteristics) as shown in FIG. 2A unless otherwise specified, and have inverted potentials (logic thresholds). Voltage) is 2.5 volts. The meanings of the symbols “L” and “H” attached to the inverter symbols are the same as those described in the first embodiment. 3 and FIG. 4 can also be used for the time chart. FIG. 3 shows a case where the capacitor C3 is not connected to the NAND gate ND1, and FIG. 4 shows a case where the capacitor C3 is connected to the NAND gate ND1. That is, FIGS. 3A, 3C, and 3D correspond to points “a”, “c”, and “d” in FIG. 6, respectively, and FIGS. 4A, 4B, 4C, and 4C. (D) corresponds to points "a", "b", "c" and "d" in FIG.

The gate circuit such as the inverter, the MOS transistor, and the subsequent circuit LA shown in FIG.
It is stored in a C chip.

Next, the operation of the present embodiment will be described by taking as an example a case where the capacitor C3 is not connected to the NAND gate ND1. The description of the same operation as in the first embodiment is omitted.

When the oscillation potential of the oscillation signal output from CMOS inverter IV0 is between the inversion potential of CMOS inverter IV1 (2.0 volts) and the inversion potential of CMOS inverter IV2 (3.0 volts), CMO
The logical output value of S inverter IV4 is "1". Therefore, the MOS transistor T31 is turned on and the MOS transistor T31 is turned on.
The transistor T34 is turned off. As a result, MO
CMO composed of S transistors T32 and T33
The output of the S inverter is short-circuited through the MOS transistor T31. Thus, the oscillation potential of the oscillation signal is C
Until the inverted potential (2.0 volts) of the MOS inverter IV1 becomes lower or the oscillation potential of the oscillation signal becomes CMO.
MOS transistors T32 and T33 until the potential becomes higher than the inversion potential (3.0 volts) of S inverter IV2.
Is held in a non-operating state, and its logical output value is held at "0".

When the oscillation potential of the oscillation signal exceeds the inversion potential of the CMOS inverter IV1 (2.0 volts) or the inversion potential of the CMOS inverter IV2 (3.0 volts), the logical output value of the CMOS inverter IV4 becomes "0". Becomes Therefore, MOS transistor T31 is turned off, and MOS transistor T34 is turned on. As a result, the CMOS inverter constituted by MOS transistors T32 and T33 is activated for the first time. The subsequent operation is basically the same as the operation described in the first embodiment, and the description is omitted.

The capacitor C is connected to the NAND gate ND1.
The operation when 3 is connected can be easily analogized from the above description and the like, and a description thereof will be omitted.

Embodiment 4 FIG. 7 shows a fourth embodiment of the oscillation control circuit according to the present invention.

The oscillation circuit composed of the CMOS inverter IV0 and the like is the same as in the first embodiment. The input / output characteristics (transfer characteristics) of each inverter are also shown in FIG. 2 as in the first embodiment. Other gate circuits and the like that substantially function as inverters have input / output characteristics (transfer characteristics) as shown in FIG. 2A unless otherwise specified, and have inverted potentials (logic thresholds). Voltage) is 2.5 volts. The meaning of the symbol “L” attached to the inverter symbol is the same as that described in the first embodiment.

The CMOS inverter IV7 is shown in FIG.
And its inversion potential is 2.0 volts. T46 is an N-channel MOS transistor, R4 is a resistor, C4 is a capacitor, IV8 is C
This is a MOS inverter. Note that the resistance value of the resistor R4 is M
This is sufficiently larger than the on-resistance value of the OS transistor T46. These CMOS inverters IV7, IV
8, the MOS transistor T46, the resistor R4 and the capacitor C4 constitute an operation control circuit OPC.

IV9 is a CMOS inverter, T41 and T42 are N-channel MOS transistors, T43 and T44 are P-channel MOS transistors,
These circuit elements form a CMOS clocked inverter. A post-stage circuit LA is connected to the output of the CMOS clocked inverter.

P-channel MOS transistor T45
When the logical output value of the CMOS inverter IV8 is "0", the output of the CMOS inverter formed by the MOS transistors T42 and T43 is short-circuited.

The gate circuit such as the inverter, the MOS transistor, and the subsequent circuit LA shown in FIG.
It is stored in a C chip.

Next, the operation of this embodiment will be described with reference to the time chart shown in FIG. FIG. 8A,
(B), (C), (D) and (E) correspond to points “a”, “b”, “c”, “d” and “e” in FIG. 7, respectively.

As shown in FIG. 8A, when the power is turned on, an oscillation signal having a small amplitude is generated from the CMOS inverter IV0. Although the amplitude of the oscillation signal gradually increases, the logic output value of the CMOS inverter IV7 is "0" until the oscillation potential becomes lower than the inverted potential (2.0 volts) of the CMOS inverter IV7. Therefore, the MOS transistor T46 is turned off, and the CM
The logical output value of the OS inverter IV8 is "0". As a result, MOS transistors T41 and T44 are turned off, and the CMOS inverter formed of MOS transistors T42 and T43 is turned off. At this time, since the MOS transistor T45 is on, the output of the CMOS inverter constituted by the MOS transistors T42 and T43 is output from the MOS transistor T45.
Shorted through 45. As described above, until the oscillation potential of the oscillation signal exceeds the inversion potential (2.0 volts) of CMOS inverter IV7, the CMOS inverter formed of MOS transistors T42 and T43 is kept in an inactive state, and its logical output value is It is held at "1".

When the oscillation potential of the oscillation signal exceeds the inversion potential (2.0 volts) of the CMOS inverter IV7, CM
The logical output value of the OS inverter IV7 is "1" and M
The OS transistor T46 is turned on. as a result,
The capacitor C4 is charged through the MOS transistor T46, and the input voltage of the CMOS inverter IV8 drops rapidly. When the MOS transistor T46 is turned off, the charge of the capacitor C4 is discharged through the resistor R4, and the input voltage of the CMOS inverter IV8 gradually rises. Then, when the input voltage of the CMOS inverter IV8 becomes lower than the inverted potential, the output logic value of the CMOS inverter IV8 is inverted from “0” to “1”. As a result, the CMOS inverter constituted by the MOS transistors T42 and T43 is turned on for the first time, and at the same time, the MOS transistor T45 is turned off. By making the resistance value of the resistor R4 sufficiently larger than the ON resistance value of the MOS transistor T46, the logic output value of the CMOS inverter IV8 becomes "1" as shown in FIG.
Will continue to be held. The oscillation signal generated from the CMOS inverter IV0 is output from the MOS transistor T0.
As shown in FIG. 8E, the duty ratio is inverted by a CMOS inverter composed of
It is possible to output a clock signal of 0%. The inverted circuit (clock signal) puts the subsequent circuit LA into an operating state.

In this embodiment, the CMOS inverter I
Although V8 has the input / output characteristics as shown in FIG. 2B, it is also possible to use V8 having the input / output characteristics as shown in FIG. 2C.

In this embodiment, the MOS transistor T
Although 45 is configured with a P-channel type, it may be configured with an N-channel type by using a logical value opposite to the logical output value of the CMOS inverter IV8.

[0044]

According to the present invention, the post-stage circuit starts operating after the amplitude of the oscillation signal becomes equal to or larger than a certain value.
Therefore, it is possible to prevent the oscillation operation from being hindered by the influence of noise generated in the subsequent circuit.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing input / output characteristics (transfer characteristics) of the CMOS inverter according to the first, second, third, and fourth embodiments.

FIG. 3 is a time chart explaining the operation of the first, second and third embodiments.

FIG. 4 is a time chart explaining the operation of the first embodiment, the second embodiment and the third embodiment.

FIG. 5 is an electric circuit diagram showing a second embodiment of the present invention.

FIG. 6 is an electric circuit diagram showing a third embodiment of the present invention.

FIG. 7 is an electric circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a time chart explaining the operation of the fourth embodiment.

[Explanation of symbols]

 IV0 first CMOS inverter QZ crystal oscillator T12, T13 second CMOS inverter T22, T23 second CMOS inverter T32, T33 second CMOS inverter T42, T43 second CMOS inverter T11, T14 control MOS transistor T21 Control MOS transistor T34 Control MOS transistor T41, T44 Control MOS transistor OPC Operation control circuit T15, T24, T31, T45 Output control circuit

Claims (2)

(57) [Claims] 1. A pair of power supply lines, a first CMOS inverter, and the first CMOS inverter
An oscillation circuit having a crystal oscillator connected between an output terminal and an input terminal of the first CMOS inverter, a second CMOS inverter for inputting an oscillation signal output from the first CMOS inverter, and N-channel and P-channels constituting the second CMOS inverter A control MOS transistor connected between the source of at least one of the channel transistors and at least one of the power supply lines; a first reference potential at which the oscillation potential of the oscillation signal is lower than the inversion potential of the first CMOS inverter Or the oscillation potential of the oscillation signal becomes lower than that of the first CMOS.
An oscillation control circuit comprising: an operation control circuit that holds the control MOS transistor in an OFF state until the control MOS transistor becomes higher than a second reference potential higher than the inverted potential of the inverter. 2. A pair of power supply lines, a first CMOS inverter, and the first CMOS inverter
An oscillation circuit having a crystal oscillator connected between an output terminal and an input terminal of the first CMOS inverter, a second CMOS inverter for inputting an oscillation signal output from the first CMOS inverter, and N-channel and P-channels constituting the second CMOS inverter A control MOS transistor connected between the source of at least one of the channel transistors and at least one of the power supply lines; a first reference potential at which the oscillation potential of the oscillation signal is lower than the inversion potential of the first CMOS inverter Or the oscillation potential of the oscillation signal becomes lower than that of the first CMOS.
An operation control circuit for holding the control MOS transistor in an off state until the control MOS transistor is turned off until the control MOS transistor is turned off until the voltage becomes higher than a second reference potential higher than the inverted potential of the inverter; And an output control circuit for short-circuiting to one of the power supply lines.