JPH06216723A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To erase a downward noise even if it is generated in an input signal for a short time, and to block its transfer to an internal circuit by using a signal of a connecting node of a MOSFET and a capacitor element as a logical input to a post-stage. CONSTITUTION:When a noise signal is inputted, since the potential of a connecting node (f) is drawn up by the previous noise signal input, it approaches a GND level by a coupling action of capacitors C2 and C3, but not does not fall entirely. Also, the potential of the connecting node (f) does not reach a threshold of an NMOSFET-N4. Accordingly, N4 is turned off, and the noise can be erased so as not to be transferred to an internal circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (I
C), especially CMOS type large scale integrated circuit (LS)
The present invention relates to a noise canceller circuit for erasing noise input from the outside to the input circuit of I) so as not to be transmitted to an LSI internal circuit.

[0002]

2. Description of the Related Art FIG. 12 shows a conventional CMOS structure LSI.
The noise canceller circuit of is shown.

In this CMOS structure LSI, for example, P
Type semiconductor substrate is used, and an N-channel insulated gate transistor (hereinafter referred to as an NMOS transistor) is used.
Are directly formed on the P-type semiconductor substrate, and P-channel type M
The OS transistor (hereinafter referred to as a PMOS transistor) is formed on the N-type well region formed on the P-type semiconductor substrate to have a predetermined depth. A ground potential (hereinafter referred to as GND) is applied to the P-type semiconductor substrate, and a positive power supply potential (hereinafter referred to as VDD) with respect to GND is applied to the N-type well region. .

In FIG. 12, A is an external input terminal of the LSI, IV1 is a CMOS inverter circuit which inverts and transfers the level of the signal from the input terminal A, and C1 delays the output signal of IV1 by charging / discharging charges. , A CMOS inverter circuit IV2 for inverting and transmitting the output signal of the CMOS inverter circuit IV1,
121 is a logic circuit, 122 is a latch circuit that holds the output signal of the logic circuit 121, 123 is an internal circuit of the LSI, and Z is an external output terminal.

In the logic circuit 121, PMOS transistors P1 and P2 and NMOS transistors N1 and N2 are connected in series between VDD and VSS,
The signal from the input terminal A is input to the gates of the PMOS transistor P1 and the NMOS transistor N2, and the PMO
The output signal of the CMOS inverter circuit IV2 is input to the S transistor P2 and the NMOS transistor N1. The latch circuit 122 is composed of CMOS inverter circuits IV3 and IV4. In the above circuit, the low logic level of the signal is set to "L" (approximately GN).
D), the high level of the logic level is "H" (almost VD
Represented by D).

In the above circuit, the input node of the CMOS inverter circuit IV1 is represented by a, the output node of the CMOS inverter circuit IV1 is represented by b, the output node of the CMOS inverter circuit IV2 is represented by c, and the output node of the logic circuit 121 is represented by d. . 13 to 16 are respectively shown in FIG.
7 shows an example of potential changes of the nodes a, b, c, d with respect to time in different operation examples of the circuit of FIG.
FIG. 13 shows an example of normal operation of the circuit of FIG. In FIG. 13, during the period of T (1) and (5), the input terminal A is externally supplied.
The case where the input signal applied to (input node a) is "H" is shown.

In this case, the output node b of the inverter circuit IV1 is "L" and the output node c of the inverter circuit IV2 is "H". Then, the logic circuit 121 receives the signals of the nodes a and c and receives the signal from the PMOS transistor P.
Both 1 and P2 are off, NMOS transistors N1 and N2
Are both turned on, and the output node d becomes "L",
This “L” output is transmitted to the internal circuit 123. FIG.
In the period T (2), the input signal changes from "H" to "L".

In this case, at the output node b of the inverter circuit IV1, there is a signal that changes from "L" to "H" with a delay due to the amount of charge of the capacitor element C1 and the time constant of the on resistance of the inverter circuit IV1. A signal that is output and changes from "H" to "L" is output to the output node c of the inverter circuit IV2. Then, the logic circuit 121
At first, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, and the output node d is in a high impedance state, but the latch circuit 122 at the next stage holds the state (“L”) up to that point.

Eventually, when the signal at the node b reaches the threshold value of the inverter circuit IV2, the output node c of the inverter circuit IV2 is inverted to "L", and the PMOS of the logic circuit 121 is formed.
The transistor P2 is turned on, the NMOS transistor N1 is turned off, and "H" is output to the output node d. That is, a signal changing from “L” to “H” is transmitted to the internal circuit 123 later than the change of the input signal. In FIG.
The period of T (3) shows the case where the input signal is "L".

In this case, the output node b of the inverter circuit IV1 becomes "H" and the output node c of the inverter circuit IV2 becomes "L". Then, the logic circuit 121
Both the OS transistors P1 and P2 are turned on, the NMOS transistors N1 and N2 are both turned off, "H" is output to the output node d, and the "H" output is output to the internal circuit 1
It is transmitted to 23. In FIG. 13, the period T (4) shows the case where the input signal changes from "L" to "H".

In this case, at the output node b of the inverter circuit IV1, there is a signal that changes from "H" to "L" with a delay due to the charge amount of the capacitor element C1 and the time constant of the on resistance of the inverter circuit IV1. A signal that is output and changes from "L" to "H" is output to the output node c of the inverter circuit IV2. Then, the logic circuit 121
At first, the PMOS transistor P1 is turned off, the NMOS transistor N1 is turned on, and the output node d is in a high impedance state, but the latch circuit 122 at the next stage holds the state (“H”) up to that point. Eventually, when the signal of the node b reaches the threshold value of the inverter circuit IV2, the output node c of the inverter circuit IV2 is inverted to “H”, the PMOS transistor P2 of the logic circuit 121 is turned off, and the NMOS transistor N1 is turned on to output. Since "L" is output from the node node d, a signal changing from "H" to "L" is transmitted to the internal circuit 123 later than the change of the input signal.

In FIG. 14, the capacitor element C1 is applied to the input signal.
7 shows an operation example in the case where a level change (noise signal) occurs in a time shorter than the delay due to the time constant of the charge amount and the ON resistance of the inverter circuit IV1.

In FIG. 14, the period T (1) shows the operation when the level change (downward noise) of "H" → "L" → "H" occurs in the input signal, and the logic circuit 121
Only "L" is output to the output node d of. A period T (2) in FIG. 14 shows an operation when a level change (upward noise) of “L” → “H” → “L” occurs in the input signal, and the output node of the logic circuit 121. Only "H" is output to d.

As described above, the circuit of FIG. 12 uses the input signal as the charge amount of the capacitor element C1 and the inverter circuit IV.
It can be seen that even if noise occurs for a time shorter than the delay due to the time constant of the ON resistance of 1, this noise acts as a noise canceller circuit that erases the noise so as not to be transmitted to the internal circuit 123.

However, in the circuit of FIG. 12, when a plurality of noise signals of a short time as described above are continuously input,
As described below, there is a problem that the noise canceller circuit cannot function. FIG. 15 shows an operation example in which a downward noise signal is continuously generated three times in the input signal.

In this case, if the second noise signal is input before the potential of the capacitor element C1 charged with the first noise signal completely falls to GND, the signal level of the node b changes. Since the voltage gradually increases until it exceeds the threshold value of the inverter circuit IV2, the inverter circuit I
The output node c of V2 is inverted to "L". This node c
Signal is inverted by the logic circuit 121 and is transmitted as upward noise to the internal circuit 123, which causes a malfunction of the internal circuit 123. FIG. 16 shows an operation example when an upward noise signal is continuously generated three times in the input signal.

In this case, if the second noise signal is input before the potential of the capacitor element C1 discharged along with the first noise signal rises completely to VDD, the signal level of the node b changes to the inverter. Since the voltage gradually decreases until it exceeds the threshold of the circuit IV2, the inverter circuit I
The output node c of V2 is inverted to "H". This node c
Signal is inverted by the logic circuit 121 and is transmitted to the internal circuit 123 as downward noise, causing a malfunction of the internal circuit 123.

[0018]

As described above, in the conventional noise canceller circuit, when a plurality of noise signals of a short time are continuously input, the next noise signal is output without completely charging and discharging the capacitor element. When input, there is a problem that the function as a noise canceller circuit is not fulfilled and a noise signal is transmitted to an internal circuit, which causes a malfunction inside the LSI.

The present invention has been made to solve the above-mentioned problems. Even when a plurality of short-time noise signals are input one-shot or continuously, a noise signal that causes a malfunction inside the LSI is transmitted. An object of the present invention is to provide a semiconductor integrated circuit having a noise canceller circuit that can be canceled out.

[0020]

A semiconductor integrated circuit of the present invention comprises an external input terminal, a first PMOS transistor having a gate input from the external input terminal and a source connected to a first potential node. A first capacitor element connected between the drain of the first PMOS transistor and the external input terminal and a gate input from the external input terminal, and a source connected to a second potential node A first NMOS transistor and the first NM
A second capacitor element connected between the drain of the OS transistor and the external input terminal; a first CMOS inverter to which an input is given from the external input terminal;
A second PMOS transistor having the gate to which the output of the first CMOS inverter is input;
The drain of the transistor is connected to the source, the source is connected to the first potential node, and the gate is connected to the first NM.
A drain is connected to a drain of the second PMOS transistor and a third PMOS transistor connected to a connection node between the OS transistor and the second capacitor element, and the output of the first CMOS inverter is input to the gate. The second NMOS transistor and the second N
The drain of the MOS transistor is connected to the source, the source is connected to the second potential node, and the gate is connected to the first potential node.
A third NMOS transistor connected to a connection node between the PMOS transistor and the first capacitor element,
A circuit for outputting a signal at a drain interconnection node between the second PMOS transistor and the second NMOS transistor.

[0021]

It has a first PMOS transistor and a first capacitor element which are connected in series between a first potential node and an external input terminal, and signals of these connection nodes are used as a logic input in a subsequent stage. As a result, even when the downward noise of the input signal for a short time occurs sporadically or continuously, the noise can be erased so as not to be transmitted to the internal circuit.

Further, the second capacitor element and the first N connected in series between the external input terminal and the second potential node.
By using a signal of these connection nodes as a logic input in a subsequent stage having a MOS transistor, noise is not transmitted to an internal circuit even when upward noise for a short time occurs singly or continuously. Can be erased as

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a CMO according to a first embodiment of the present invention.
4 shows a noise canceller circuit of an S-structure LSI.

In this CMOS structure LSI, for example, P
Type semiconductor substrate is used, the NMOS transistor is formed directly on the P type semiconductor substrate, and the PMOS transistor is formed on the N type well region formed to have a predetermined depth on the P type semiconductor substrate. Has been done. Further, it is assumed that the P-type semiconductor substrate is supplied with the ground potential GND and the N-type well region is supplied with the positive power supply potential VDD. In the circuit of FIG. 1, A is an external input terminal, 11 is a logic circuit, 12 is a latch circuit, 13 is an internal circuit, and Z is an external output terminal.

In the logic circuit 11, the node e is connected to the input terminal A, and VDD and the node e are connected.
Between and the PMOS to which the signal from the input terminal A is input.
The transistor P3 and the capacitor element C2 are connected in series. A capacitor element C3 and an NMOS transistor N3 to which a signal from the input terminal A is input are connected in series between the node e and GND. IV5 is a CMOS inverter circuit to which a signal from the input terminal A is input.

Further, between VDD and GND, a PMOS transistor P4 whose gate receives the signal at the connection node g between the capacitor element C3 and the NMOS transistor N3, and a signal at the output node h of the CMOS inverter circuit IV5. A PMOS transistor P5 and an NMOS transistor N5 which are respectively input to
The OS transistor P3 and the capacitor element C2 are connected in series with the NMOS transistor N4 whose gate receives the signal at the connection node f.

The latch circuit 12 is a CMOS inverter circuit IV6 to which the output signal of the connection node i between the PMOS transistor P5 and the NMOS transistor N5 is input.
And a CMOS inverter circuit IV7 feedback-connected between the output node j and the input node i of the CMOS inverter circuit IV6. The latch signal of the latch circuit 12 is input to the internal circuit 13, and the output signal of the internal circuit 13 is output from the output terminal Z to the outside of the LSI.
2 to 5 show examples of potential changes at the nodes e, f, g, h, and i in different operation examples of the circuit of FIG. 1, respectively. FIG. 2 shows an operation example when the input signal does not include noise. In FIG. 2, T (1),
The period of (5) shows the case where the input signal of the input terminal A (input node e) is "H".

In this case, the PMOS transistor P3
Turns off and the NMOS transistor N3 turns on. Then, the charge is stored in the capacitor element C2 so that the connection node f
The level of "H" tries to maintain the "H" level. The potential difference between both ends of the capacitor element C3 is (VDD-GND).
Therefore, the capacitor element C3 tries to maintain the "L" state of the connection node g while being charged with electric charges.

On the other hand, the NMOS transistor N4 to which the signal of the connection node f is input is turned on, the PMOS transistor P4 to which the signal of the connection node g is input is turned on, and the output node h of the inverter circuit IV5 is "L". The PMOS transistor P5 is turned on and the NMOS transistor N5 is turned off. Therefore, the output node i becomes "H", and this "H" output is transmitted to the internal circuit 13. In FIG. 2, the period T (2) shows the case where the input signal changes from "H" to "L".

In this case, the capacitor elements C2 and C3
The coupling action is exerted, and the potential of the connection node f approaches "L". Further, the connection node g has a potential lower than GND due to the coupling action of the capacitor element C3, but since a forward diode is formed between the substrate region and the drain of the NMOS transistor N3, GND-Vf.
The potential becomes (forward voltage of the diode) and maintains "L".

At this time, N input by the signal of the connection node f
The MOS transistor N4 is turned off, and the PMOS transistor P4 to which the signal of the connection node g is input is turned on. Further, the output node h of the inverter circuit IV5 becomes "H", the PMOS transistor P5 is turned off, and the NMOS transistor N5 is turned on. As a result, the output node i is in a high impedance state, but the latch circuit 12 in the next stage holds the state ("H") up to that point.

When the "L" state of the input signal continues for a while, as shown in the period T (3) in FIG.
The S transistor P3 starts to turn on, and the capacitor element C2
Charging starts, and the potential of the connection node f gradually approaches "H". When the level of the connection node f exceeds the threshold of the NMOS transistor N4, the NMOS transistor N4
Is turned on, and "L" is output to the output node i. That is, a signal that changes from “H” to “L” is transmitted to the internal circuit 13 later than the change of the input signal.

When the input signal is "L" as described above, the PMOS transistor P3 is on, the NMOS transistor N3 is off, and the potential difference across the capacitor element C2 is (VDD-GND). Therefore, the capacitor element C2 tries to hold the "H" state of the connection node f while being charged with electric charge. Further, the connection node g tries to maintain the "L" state by storing the charge of the capacitor element C3.

On the other hand, the NMOS transistor N4 to which the signal of the connection node f is input is turned on, the PMOS transistor P4 to which the signal of the connection node g is input is turned on, and the output node h of the CMOS inverter circuit IV5 becomes "H". , PMOS transistor P5 is off, NM
The OS transistor N5 is turned on. Therefore, the output node i becomes "L", and this "L" output becomes the internal circuit 1
Passed to 3. In FIG. 2, the period T (4) shows the case where the input signal changes from "L" to "H".

In this case, the capacitor elements C2 and C3
The coupling action is exerted on the connection node g, and the potential of the connection node g approaches "H". Further, the connection node f has a potential higher than VDD due to the coupling action of the capacitor element C2, but since a forward diode is formed between the substrate region and the drain of the PMOS transistor P3, VDD + Vf
The potential becomes (the forward voltage of the diode) and maintains "H".

At this time, P input by the signal of the connection node g
The MOS transistor P4 is turned off, and the NMOS transistor N4 to which the signal of the connection node f is input is turned on. Further, the output node h of the inverter circuit IV5 becomes "L", the PMOS transistor P5 is turned on, and the NMOS transistor N5 is turned off. As a result, the output node i is in a high impedance state, but the latch circuit 12 in the next stage holds the previous state (“L”).

When the "L" state of the input signal continues for a while, as shown in the period T (3) in FIG.
The S transistor N3 starts to turn on, and the capacitor element C3
Discharge starts, and the potential of the connection node g gradually approaches "L". When the level of the connection node g exceeds the threshold of the PMOS transistor P4, the PMOS transistor P4
Is turned on, and "H" is output to the output node i. That is, a signal changing from “L” to “H” is transmitted to the internal circuit 13 later than the change of the input signal.

When the input signal continues to be "H" as described above, the PMOS transistor P3 is off, the NMOS transistor N3 is on, and the potential difference across the capacitor element C3 is (VDD-GND). Therefore, the capacitor element C3 tries to maintain the "L" state of the connection node g while being charged with electric charges. Further, the connection node f tries to maintain the "H" state by the charge storage of the capacitor element C2. FIG. 3 shows an operation example when a noise signal of a short time occurs in the input signal.

In FIG. 3, during the period T (1), the operation when the level change (downward noise) of “H” → “L” → “H” occurs in the input signal is shown. Only "H" is output to d. A period T (2) in FIG. 3 shows an operation when a level change (upward noise) of “L” → “H” → “L” occurs in the input signal, and the output node d is “ Only L "outputs.

As described above, the circuit of FIG. 1 has the NMOS transistor N even if downward noise occurs in the input signal.
It can be seen that if the noise is noise for a short time that returns to "H" before turning on, this noise acts as a noise canceller circuit that erases the noise so as not to be transmitted to the internal circuit 13.

Even if upward noise occurs in the input signal, if the noise is such that it returns to "H" before the PMOS transistor P4 turns on, this noise will not be transmitted to the internal circuit 13. Can be erased.

In this case, the pulse width of the noise signal that can be canceled depends on the PMOS transistor P3 and NMOS.
It can be determined by changing the on-resistance of the transistor N3 and the capacitance values of the capacitor elements C2 and C3, and also by changing the thresholds of the PMOS transistor P4 and the NMOS transistor N4.

Further, the circuit of FIG. 1 can function as a noise canceller circuit as described below even when a plurality of noise signals as described above are continuously input. FIG. 4 shows an operation example in which a downward noise signal is continuously generated a plurality of times in the input signal. The operation in the period T (2) when the first noise signal is input is similar to the operation described above with reference to the period T (1) in FIG.

Period T during which the noise signal is input for the second time and thereafter
In the operation of (3), when the noise signal is input, the potential of the connection node f is (VDD + vf) due to the previous noise signal input.
Since it has been pulled up, C2 of the capacitor element C2
Is approached to the GND level by the coupling action of, but not completely lowered. The potential of the connection node f is NMO.
It does not reach the threshold of the S transistor N4. Therefore, the NMOS transistor N4 is turned off, and T of FIG.
Since the operation is similar to that described with reference to the period (1), noise can be erased so as not to be transmitted to the internal circuit 13. FIG. 5 shows an operation example in the case where an upward noise signal is continuously generated a plurality of times in the input signal.

When the first noise signal is input and 2
The operation when the noise signal after the first time is input is T in FIG.
Since the operation is the same as that described with reference to the period (2), noise can be erased so as not to be transmitted to the internal circuit 13.

That is, according to the noise canceller circuit of the first embodiment as described above, even if the noise of the input signal is generated for a short period of time or continuously, the noise is prevented from being transmitted to the internal circuit 13. It can be erased, and malfunction of the internal circuit 13 due to noise can be prevented.

In the normal operation, the same characteristics can be obtained by the operation equivalent to that of the conventional input buffer circuit.
Moreover, the number of elements used is smaller than that of the conventional circuit shown in FIG. FIG. 6 shows a noise canceller circuit according to the second embodiment of the present invention.

The noise canceller circuit of FIG. 6 is different in that the logic circuit 61 is different from the logic circuit 11 of FIG. 1 in that the NMOS transistor N3, the capacitor element C3, and the PMOS transistor P4 are omitted, and the others are the same. Therefore, the same reference numerals as in FIG. 1 are attached. 7 and 8
6A and 6B show examples of potential changes at the nodes e, f, h, and i in different operation examples of the circuit of FIG. FIG. 7 shows an operation example when the input signal does not include noise. The operation of the circuit of FIG. 6 in this case is similar to the operation described above with reference to FIG. 2 for the corresponding circuit portion in the noise canceller circuit of FIG. FIG. 8 shows an operation example in the case where a short downward noise signal is sporadically generated in the input signal. The operation of the circuit of FIG. 6 in this case is similar to the operation described above with reference to FIG. 3 for the corresponding circuit portion in the noise canceller circuit of FIG.

The pulse width of the noise signal that can be canceled by the noise canceller circuit of FIG.
On-resistance of OS transistor P3 and capacitor element C2
Can be determined by changing the capacitance value of
It can also be determined by changing the threshold value of the NMOS transistor N4.

Further, in the circuit of FIG. 6, even when a plurality of downward downward noise signals are continuously input,
The noise can be erased so as not to be transmitted to the internal circuit 13. FIG. 9 shows a noise canceller circuit according to the third embodiment of the present invention.

The noise canceller circuit of FIG. 9 is different from the logic circuit 11 of FIG. 1 in that the PMOS transistor P3, the capacitor element C2, and the NMOS transistor N4 are omitted, and the others are the same. Therefore, the same reference numerals as in FIG. 1 are attached. 10 and 11 show examples of potential changes at the nodes e, g, h, and i in different operation examples of the circuit of FIG. 9, respectively. FIG. 10 shows an operation example when the input signal does not include noise. The operation of the circuit of FIG. 9 in this case is similar to the operation described above with reference to FIG. 2 for the corresponding circuit portion in the noise canceller circuit of FIG. FIG. 11 shows an operation example in the case where a short upward noise signal is generated in the input signal one by one. The operation of the circuit of FIG. 9 in this case is similar to the operation described above with reference to FIG. 3 for the corresponding circuit portion in the noise canceller circuit of FIG.

The pulse width of the noise signal that can be canceled by the noise canceller circuit of FIG. 9 as described above is NM.
On-resistance of OS transistor N3 and capacitor element C3
Can be determined by changing the capacitance value of
It can also be determined by changing the threshold value of the PMOS transistor P4.

Furthermore, in the noise canceller circuit of the third embodiment, even when a plurality of downward downward noise signals as described above are continuously input, noise is generated in the internal circuit 13.
It can be erased so that it is not transmitted to.

In each of the above embodiments, GND and V
Although the case where the DD is used is shown, even when the GND and the negative power supply potential are used, the same effect as each of the above-described embodiments can be obtained by configuring the circuit accordingly.

[0055]

As described above, the noise canceller circuit in the IC of the present invention prevents noise from being transmitted to the internal circuit even when noise of a short time occurs in the input signal either singly or continuously. Can be erased,
It is possible to prevent malfunction of the LSI internal circuit due to noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a noise canceller circuit of an IC according to a first embodiment of the present invention.

FIG. 2 is a timing waveform chart showing an operation example when the input signal of the circuit of FIG. 1 does not include noise.

3 is a timing waveform chart showing an operation example in the case where a short noise signal is sporadically generated in the input signal of the circuit of FIG.

FIG. 4 is a timing waveform chart showing an operation example when a downward short noise signal is generated a plurality of times in succession in the input signal of the circuit of FIG.

5 is a timing waveform chart showing an operation example in the case where an upward short noise signal is continuously generated a plurality of times in the input signal of the circuit of FIG.

FIG. 6 is a circuit diagram showing a noise canceller circuit of an IC according to a second embodiment of the present invention.

7 is a timing waveform chart showing an operation example when the input signal of the circuit of FIG. 6 does not include noise.

8 is a timing waveform chart showing an operation example in the case where a downward short noise signal occurs in the input signal of the circuit of FIG. 6 continuously a plurality of times.

FIG. 9 is a circuit diagram showing a noise canceller circuit of an IC according to a third embodiment of the present invention.

10 is a timing waveform chart showing an operation example when the input signal of the circuit of FIG. 9 does not include noise.

11 is a timing waveform chart showing an operation example in the case where an upward short noise signal is continuously generated a plurality of times in the input signal of the circuit of FIG.

FIG. 12 is a circuit diagram showing a noise canceller circuit of a conventional IC.

13 is a timing waveform chart showing an operation example when the input signal of the circuit of FIG. 12 does not include noise.

14 is a timing waveform chart showing an operation example in the case where a short noise signal is sporadically generated in the input signal of the circuit of FIG.

FIG. 15 is a timing waveform chart showing an operation example in which a downward short noise signal is continuously generated a plurality of times in the input signal of the circuit of FIG.

16 is a timing waveform chart showing an operation example in the case where an upward short noise signal is continuously generated plural times in the input signal of the circuit of FIG.

[Explanation of symbols]

A ... Input terminal, 11, 61, 91 ... Logic circuit, 12 ... Latch circuit, 13 ... Internal circuit, P3, P4, P5 ... PMO
S transistor, N3, N4, N5 ... NMOS transistor, IV5, IV6, IV7 ... Inverter circuit, C
2, C3 ... Capacitor element, e, f, g, h, i, j ...
Node, VDD ... Power supply potential, GND ... Ground potential.

Claims (3)

[Claims] 1. An external input terminal, a first PMOS transistor having a gate input from the external input terminal and a source connected to a first potential node, a drain of the first PMOS transistor and the external terminal. A first capacitor element connected to an input terminal; a first NMOS transistor having a gate input from the external input terminal and a source connected to a second potential node; A second capacitor element connected between the drain of a transistor and the external input terminal; and a first CMOS to which an input is given from the external input terminal
An inverter, a second PMOS transistor to which the output of the first CMOS inverter is input to the gate, a drain of the second PMOS transistor is connected to the source, a source is connected to the first potential node, and a gate is connected to the gate. A third PMOS transistor connected to a connection node between the first NMOS transistor and the second capacitor element; a drain connected to the drain of the second PMOS transistor; and a gate connected to the first CMOS inverter. A second NMOS transistor to which an output is input, a drain of which is connected to a source of the second NMOS transistor, a source of which is connected to a second potential node, and a gate of which is the first PMOS transistor and a first capacitor element. A third NMOS transistor connected to the connection node with, A semiconductor integrated circuit comprising: a circuit that outputs a signal at a drain interconnection node of the second PMOS transistor and the second NMOS transistor. 2. An external input terminal, a first PMOS transistor having a gate input from the external input terminal and a source connected to a first potential node, a drain of the first PMOS transistor and the external terminal. A capacitor element connected between an input terminal and a first CMOS to which an input is given from the external input terminal.
An inverter and a second PM whose output is input to the gate and whose source is connected to the first potential node.
An OS transistor, a drain connected to the drain of the second PMOS transistor, a first NMOS transistor to which the output of the first CMOS inverter is input to the gate, and a drain connected to the source of the first NMOS transistor A second NMOS transistor having a source connected to a second potential node and a gate connected to a connection node between the first PMOS transistor and the capacitor element; and the second PMOS transistor and the first NMOS. And a circuit for outputting a signal of a drain interconnection node with a transistor. 3. An external input terminal, a first NMOS transistor having a gate input from the external input terminal and a source connected to a second potential node, a drain of the first NMOS transistor and the external A capacitor element connected between an input terminal and a first CMOS to which an input is given from the external input terminal.
An inverter and a first PM whose output is input to a gate and whose source is connected to a first potential node.
A drain is connected to the source of the OS transistor and the first PMOS transistor, the source is connected to the first potential node, and the gate is connected to the connection node between the first NMOS transistor and the capacitor element. And a second NMOS transistor having a drain connected to the drain of the second PMOS transistor, a source connected to the second potential node, and a gate to which the output of the first CMOS inverter is input. A semiconductor integrated circuit comprising: a circuit that outputs a signal at a drain interconnection node of the second PMOS transistor and the second NMOS transistor.