JP2000250666A - Central processor and method for reducing power consumption of its central processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a central processor which can be reduced in power consumption by stopping an unnecessary current from flowing in and out of a CPU while a controlled system is in a standby state and the power consumption reducing method for the central processor. SOLUTION: The central processor 104 are equipped with a power source control signal terminal 106, a 1st control signal terminal 107, and a 2nd control signal terminal 108 which are pulled up to a source voltage through resistors R1 to R3 and connected to a power source 112, a 1st controlled system 113, and a 2nd controlled system 114 respectively. This central processor 104 is equipped with a flag switching means 111 which places in the control signal terminals 106 to 108 in a high-impedance state when the power source 112, 1st controlled system 113, and 2nd controlled system 114 enter a standby state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit and a method for reducing power consumption of the central processing unit, and more particularly to a control signal terminal which is pulled up to a power supply voltage via a resistor and connected to a control target. The present invention relates to a central processing unit provided and a method for reducing power consumption of the central processing unit.

[0002]

2. Description of the Related Art Generally, a central processing unit (CPU) has a VDD terminal to which a power supply voltage is supplied, a reset terminal to which a reset signal is supplied, and a remote control input terminal to which an interrupt signal from a remote controller is inputted. And a main oscillator and a sub-oscillator for generating a clock signal required for the operation are connected to the input side. This CPU
Has a control signal terminal for outputting a control signal to various control targets. The control signal terminal is active low (LOW)
And pulled up to VDD via a pull-up resistor.

In the above-mentioned CPU, when the control target enters a power-off state (hereinafter referred to as a standby state), the main oscillator is stopped, only the sub-oscillator is oscillated, and a low-speed clock is used. CPU by stopping the unit
They are trying to reduce their own power consumption.

[0004]

By the way, in the above-mentioned conventional CPU, the current flows into or out of the CPU via the pull-up resistor even though the control target is in a standby state, and the power is reduced. It was unnecessarily consumed.

SUMMARY OF THE INVENTION In view of the above, the present invention provides a central processing unit capable of realizing low power consumption by suppressing unnecessary current flowing into or out of a CPU while a control target is on standby. It is an object to provide a method for reducing power consumption.

[0006]

In order to achieve the above object, a central processing unit according to the present invention comprises a central processing unit having a control signal terminal which is pulled up to a power supply voltage via a resistor and connected to an object to be controlled. The processing apparatus is characterized in that the processing apparatus further comprises setting means for setting the control signal terminal to a high impedance state when the control target enters a standby state.

In the central processing unit of the present invention, when the control target is in the standby state, the control signal terminal can be set to the high impedance state, so that unnecessary current flows into the central processing unit via the pull-up resistor or flows into the central processing unit. It can be prevented from flowing out. Thereby, low power consumption can be realized.

The control signal terminal is connected to a current path of both a first conductivity type MOS transistor for high level output and a second conductivity type MOS transistor for low level output, and the setting means includes: First and second conductivity type MOS
The first and second conductivity type MOSs are switched by switching a high level / low level of a signal applied to each gate of the transistor.
Preferably, the high impedance state is obtained by turning off both transistors. in this case,
The switching operation to the high impedance state by the setting means is simplified.

The setting means includes an inverter for inverting a potential state of an input / output designation flag, and an exclusive OR of the input / output designation flag and the output state designation flag for the first conductivity type MOS transistor. N to supply to gate
An AND gate and an inverted value of a logical sum of an inverted value of the input / output designation flag and the output state designation flag,
And a NOR gate for supplying the gate of the conductivity type MOS transistor. In this case, the setting means can be realized with a simple circuit configuration.

The method of reducing power consumption of a central processing unit according to the present invention is a method of reducing power consumption of a central processing unit having a control signal terminal which is pulled up to a power supply voltage via a resistor and connected to a control target. The control signal terminal is set to a high impedance state when the control target enters a standby state.

In the method for reducing power consumption of a central processing unit according to the present invention, when a control target is in a standby state, an unnecessary current flows in or out through a pull-up resistor by setting a control signal terminal to a high impedance state. Can be suppressed.

[0012]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing a CPU and its peripheral circuits according to the first embodiment of the present invention.

The CPU 104 has an input side to which a VDD terminal to which a power supply voltage is supplied, a reset terminal 110 to which a reset signal is supplied from a reset IC 102, and an interrupt signal from a remote controller (not shown). It has a remote control input terminal 103 and operates according to a built-in program when power is supplied to the VDD terminal. CP
A sub-oscillator 115 for low-speed clock and a main oscillator 105 for high-speed clock for generating a clock signal required for the operation are further connected to the input side of U104.

The reset IC 102 is supplied with VDD and supplies a generated reset signal to the CPU 104.
In the CPU 104, when power is supplied to the VDD terminal,
Reset IC 10 that rises several ms later than VDD
2 supplies the reset signal, the main oscillator 105 oscillates, and the built-in program is executed.

The CPU 104 includes, on the output side, a power supply 112 to be controlled, a first control target 113 and a second control target 1.
A power control signal terminal 10 for outputting a control signal to
6, first control signal terminal 107 and second control signal terminal 10
8 The first control output 107 is pulled up to VDD via a resistor R1, the second control signal terminal 108 is pulled up to VDD via a resistor R2, and the power control signal terminal 106 is pulled up to VDD via a resistor R3. Is pulled up. The power control signal terminal 106, the first control signal terminal 107, and the second control signal terminal 108 are all set to active low (LOW).

The power supply 112 operates according to a control signal from the power supply control signal terminal 106 of the CPU 104, and supplies power to the first control target 113 and the second control target 114, respectively. The first control target 113 operates according to a control signal from the control signal terminal 107 of the CPU 104 while receiving power supply from the power supply 112. The second control target 114 operates according to a control signal from the control signal terminal 108 of the CPU 104 while receiving power supply from the power supply 112.

The CPU 104 includes a mode switching unit 109
Having. The mode switching means 109 is provided for controlling the main oscillator 1 when dealing with a high-speed processing mode such as an internal processing such as an operation.
05 to switch to the sub-oscillator 115 when dealing with a low-speed processing mode such as input processing from a keyboard. By switching to the main oscillator 105, it is possible to cope with the high-speed processing mode, and it is possible to shorten the processing execution time. Further, by switching to the sub-oscillator 115 side, it is possible to cope with the low-speed processing mode, and it is possible to reduce power consumption.

For example, when the first controlled object 113 and the second controlled object 114 are in a standby state, the CPU 104
By switching the mode switching means 109, the main oscillator 105 is stopped and only the sub-oscillator 115 is oscillated, and the CPU 104 operating based on the main oscillator 105
Change the state of each output terminal. At the same time, an external interrupt signal from the remote control input terminal 103 is monitored. As a result, the CPU 104 reduces its own power consumption by stopping some internal circuits. When a power-on command is input to the remote control input terminal 103 and an interrupt occurs, the main oscillator 105 is oscillated, and
2 to turn on the first controlled object 113 and the second controlled object 11
4 to perform normal operation.

The CPU 104 further includes an input / output designation flag 501, an output state designation flag 502, and a flag switching means 111 for switching the selection state between "1" and "0" in the input state designation flag 503, which will be described later.

FIG. 2 is a diagram schematically showing a common circuit configuration in the vicinity of the power control signal terminal 106, the first control signal terminal 107, and the second control signal terminal 108 in the CPU 104. This circuit includes an inverter 504, a NAND gate 505, a NOR gate 506, a PchMOS-FET 507, an Nc
An hMOS-FET 508 and an input / output terminal 509 which is an input / output terminal are provided.

The inverter 504 inverts the potential state of the input / output designation flag 501. NAND gate 505
Supplies the exclusive OR of the input / output designation flag 501 and the output state designation flag 502 to the gate of the PchMOS-FET 507. The NOR gate 506 supplies the inverted value of the logical sum of the inverted value of the input / output designation flag 501 and the output state designation flag 502 to the gate of the NchMOS-FET 508.

The PchMOS-FET 507 is connected to an input / output terminal 509.
For outputting HIGH, the gate is connected to the output of the NAND gate 505, and the source and the back gate are connected to V
Commonly connected to DD. The NchMOS-FET 508 is for outputting LOW to the input / output terminal 509, and the gate is NO.
It is connected to the output of the R gate 506, and the source and the back gate are commonly connected to GND. PchMOS-FET507 and
Each drain of the NchMOS-FET 508 is commonly connected to an input / output terminal 509.

The input / output designation flag 501 determines whether the power control signal terminal 106, the first control signal terminal 107, and the second control signal terminal 108 are input terminals or output terminals. The output state designation flag 502 is set to HIGH when the power supply control signal terminal 106, the first control signal terminal 107, and the second control signal terminal 108 are designated as output terminals.
Decide which of LOW is output. When the power supply control signal terminal 106, the first control signal terminal 107, and the second control signal terminal 108 are designated as input terminals, the input state designation flag 503 indicates that the terminals 106, 107, 108
Indicates which of GH and LOW is supplied.

FIG. 3 shows each of the terminals 106 to 10 in FIG.
8 is a truth table showing the operation state of FIG. When the input / output designation flag 501 is switched to “0” and the output state designation flag 502 is switched to “0” by the flag switching unit 111, the input of the Pch MOS-FET 507 becomes “1 (LOW)” and the Nch
The input of the MOS-FET 508 becomes “0 (HIGH)” and the PchMOS-FE
Both T507 and NchMOS-FET 508 are turned off. For this reason, neither HIGH nor LOW is output to the input / output terminal 509 and the input / output terminal 509 is in a high impedance (hereinafter referred to as “Hiz”) state, and the input state designation flag 503 stores the state of the input / output terminal 509.

When the input / output designation flag 501 is switched to "0" and the output state designation flag 502 is switched to "1",
The input of the PchMOS-FET 507 becomes “1”, the input of the NchMOS-FET 508 becomes “0”, and the PchMOS-FET 507 and the NchMOS-FET
Both 508 are off. Therefore, the input / output terminal 50
Neither HIGH nor LOW is output to 9, and the input / output terminal 509 is in the Hiz state as described above.

When the input / output designation flag 501 is switched to "1" and the output state designation flag 502 is switched to "0",
The input of the PchMOS-FET 507 is “1”, the input of the NchMOS-FET 508 is “1”, the PchMOS-FET 507 is off, and the NchMOS
-FET 508 is turned on. Therefore, the input / output terminal 509
Is output, and LOW, which is the state of the input / output terminal 509, is stored in the input state designation flag 503.

When the input / output designation flag 501 is switched to "1" and the output state designation flag 502 is switched to "1",
The input of the PchMOS-FET 507 becomes “0”, the input of the NchMOS-FET 508 becomes “0”, the PchMOS-FET 507 is turned on, and the NchMOS
-FET 508 is turned off. Therefore, the input / output terminal 509
Is output to the input state designation flag 503.
Is stored.

Next, the operation of this embodiment will be described. FIG. 4 is a flowchart showing the operation of the CPU and its peripheral circuits in the embodiment. First, when the built-in program is executed by supplying power, the flag switching unit 111 causes the input / output designation flag 501 and the output to each of the power control signal terminal 106, the first control signal terminal 107, and the second control signal terminal 108. All the state designation flags 502 are set to “1”. Accordingly, HIGH is output to each of the power control signal terminal 106, the control signal terminal 107, and the control signal terminal 108 (step 30).
1).

Next, the flag switching means 111 controls the power control signal terminal 106, the first control signal terminal 107, and the second
The input / output designation flags 501 for each of the control signal terminals 108 are all set to “1”, and the output state designation flags 502 are all set to “0”. As a result, LOW is output to each of the power supply control signal terminal 106, the control signal terminal 107, and the control signal terminal 108 (step 302), and the power supply 112 is turned on, and both the first control target 113 and the second control target 114 are turned on. An electric current is supplied to control the first control target 113 and the second control target 114, respectively.

In this state, the remote control input terminal 10
3 is supplied with a power-off command (step 303).
The flag switching means 111 turns off the power supply 112 by setting "1" to the output state designation flag 502 for the power supply control signal terminal 106 (step 304).
Further, the first control signal terminal 107 and the second control signal terminal 1
By setting each of the input / output designation flags 501 to "0", the first control signal terminal 107 and the second control signal terminal 108 are set to Hiz (step 305).

Next, when a power-on command is supplied to the remote control input terminal 103 (step 306), the flag switching means 111 sets the output state designation flag 502 for the power control signal terminal 106 to "0", thereby turning off the power. 112 is turned on (step 307). Furthermore, the first
By setting the input / output designation flag 501 of each of the control signal terminal 107 and the second control signal terminal 108 to “1”, LOW is output to the first control signal terminal 107 and the second control signal terminal 108 (step 308). ).

As described above, in the present embodiment, during standby, both the PchMOS-FET 507 and the NchMOS-FET 508 are turned off, and the power control signal terminal 106 and the first control signal terminal 10 are turned off.
7 and the second control signal terminal 108 are in the Hiz state, respectively, whereby the CPU 1 is connected via the resistors R1, R2 and R3.
04 can be suppressed,
The power consumption inside U can be reduced.

In the present embodiment, the method of setting the control signal terminals 106 to 107 in the Hiz state by the program has been described. However, the present invention is not limited to this. The first control signal terminal 107 and the 2 control signal terminal 1
By setting 08 in the Hiz state in a circuit, the same effect as described above can be obtained. Further, the present embodiment can be similarly applied to an embedded CPU such as a television and a non-embedded CPU such as a personal computer.

In the conventional type configuration, the control signal terminal becomes HIGH or LOW during standby, so that the PchMOS-FET 5
Either 07 or NchMOS-FET 508 was always turned on. For this reason, power for turning on one MOS-FET is always consumed. For example, in the case of a CPU having 64 terminals, VDD, GND, oscillator IN, oscillator OUT,
When all of the 58 terminals except for the terminals which cannot be controlled by a program such as a reset input and the power supply control terminal are all LOW at the time of standby and the CPU is set to the Hiz state at the time of standby by applying the present invention, the current flowing through the pull-up resistor is reduced. Can be eliminated. This reduces power consumption (:
P1) is P1 = (square of voltage / pull-up resistance) × 58
Becomes

Further, by applying the present invention, the PchMOS-FET 50
The power consumption P2 reduced by turning off the NchMOS-FET 7 and the NchMOS-FET 508 is as follows: P2 = 1 power consumption of the FET having one terminal × 58. Therefore, the power consumption (: P3) that can be reduced is P3 = P1 + P2.

As described above, in the present embodiment, during standby, the control terminal is designated as the input terminal by the program to be in the Hiz state, or the output of the control terminal is hiz-circuited in a circuit.
By setting the state, the current flowing into the control signal terminals 106 to 108 is suppressed. Thus, in a built-in CPU such as a television or a non-built-in CPU such as a personal computer, the main oscillator 105 is used.
Is stopped and the sub oscillator 115 is used, or even when only the main oscillator 105 is provided, the inconvenience of the current flowing through the pull-up resistor to the control signal terminals 106 to 108 in standby is eliminated, and the power consumption is reduced. Can be reduced.

Although the present invention has been described based on the preferred embodiment, the central processing unit and the method for reducing the power consumption of the central processing unit of the present invention are limited only to the configuration of the above embodiment. Instead, a central processing unit in which various modifications and changes have been made from the configuration of the above-described embodiment and a method for reducing power consumption of the central processing unit are also included in the scope of the present invention.

[0038]

As described above, according to the central processing unit and the power consumption reducing method of the central processing unit of the present invention,
During standby of the control target, low power consumption can be realized by suppressing unnecessary current flowing into or out of the CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a CPU and its peripheral circuits according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a common circuit configuration near each control signal terminal in a CPU.

FIG. 3 is a truth table showing an operation state of each control signal terminal in FIG. 2;

FIG. 4 is a flowchart showing the operation of the CPU and its peripheral circuits in the embodiment.

[Explanation of symbols]

 102: reset IC 103: remote control input terminal 104: CPU 105: main oscillator 106: power control signal terminal 107: first control signal terminal 108: second control signal terminal 109: mode switching means 110: reset terminal 111: flag switching Means 112: power supply 113: first control target 114: second control target 115: sub oscillator 501: input / output designation flag 502: output state designation flag 503: input state designation flag 504: inverter 505: NAND gate 506: NOR Gate 507: PchMOS-FET 508: NchMOS-FET 509: Input / output terminal R1, R2, R3: Resistor

Claims (4)

[Claims] 1. A central processing unit having a control signal terminal that is pulled up to a power supply voltage via a resistor and connected to a control target, wherein the control signal terminal is connected when the control target enters a standby state. A central processing unit comprising setting means for setting a high impedance state. 2. The control signal terminal is connected to current paths of both a first conductivity type MOS transistor for high level output and a second conductivity type MOS transistor for low level output, and wherein the setting means includes Obtaining the high impedance state by switching off both the first and second conductivity type MOS transistors by switching a high level / low level of a signal applied to each gate of the first and second conductivity type MOS transistors. The central processing unit according to claim 1, wherein: 3. An inverter for inverting a potential state of an input / output designating flag, and an exclusive OR of the input / output designating flag and the output state designating flag for the first conductivity type MOS transistor. NAN to supply to gate
And a NOR gate for supplying an inverted value of the logical sum of the inverted value of the input / output designation flag and the output state designation flag to the gate of the second conductivity type MOS transistor. The central processing unit according to claim 2. 4. A method for reducing power consumption of a central processing unit having a control signal terminal which is pulled up to a power supply voltage via a resistor and connected to a control target, wherein the control target is in a standby state. A method for reducing power consumption of a central processing unit, wherein the control signal terminal is set to a high impedance state.