JPH11119844A - Power source voltage dropping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit which can reduce its area and also can make a sub-circuit selectively switched, by preparing a main voltage dropping circuit and a sub-voltage dropping circuit which can supply a small current to a dropped voltage application circuit and also can control its operation based on a sub-control signal. SOLUTION: The main voltage dropping circuit 1 which generates dropped voltage when a dropped voltage application circuit 3 has a normal operation, and the sub-voltage dropping circuit 5, which generates dropped voltage when the circuit 3 has its small power consumption in a standby state, etc., of the circuit 3. Then, the circuit 5 drops the voltage of a power supply 51 by an amount of an NchTr 52 in such a constitution where a source 52a and a gate 52c of the NchTr 52 are connected to the supply 51 with a drain 52b connected to a dropped voltage output terminal 55 respectively. Thereby, the dropped voltage can be kept at a constant level in a simple circuit constitution and in a standby mode of the circuit 3. As a result, the area of a power voltage dropping circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of operating a plurality of circuits operating at a power supply voltage of 3 V together with a circuit operating at a power supply voltage of 5 V, for example, by reducing the power supply voltage from 5 V to 3 V to reduce the power supply voltage to 3 V The present invention relates to a power supply voltage step-down circuit for supplying a plurality of circuits operating with a power supply voltage.

[0002]

2. Description of the Related Art An outline of a conventional power supply voltage step-down circuit (hereinafter abbreviated as a step-down circuit) will be described. The step-down circuit is
For example, a power supply voltage of 5 V is stepped down to a voltage of 3 V, and the stepped down voltage is supplied to the circuit. A circuit operating at a power supply voltage of 5 V operates directly at a voltage of 5 V from a power supply input and operates at a power supply voltage of 3 V. The circuit operates at a voltage of 3 V supplied from the step-down circuit. Such a step-down circuit is used by being incorporated in a semiconductor chip when a plurality of circuits operating at different power supply voltage values as described above are mounted on the semiconductor chip. If the voltage stepped down by the step-down circuit fluctuates, a plurality of circuits that use the stepped-down voltage as a power supply (hereinafter referred to as step-down voltage using circuits) may not operate properly. It is configured as follows. That is, the step-down circuit is configured to detect the fluctuation of the step-down voltage, increase the step-down voltage when the step-down voltage decreases, and decrease the step-down voltage when the step-down voltage increases, and supply a constant voltage to the step-down voltage using circuit. To be.

FIG. 12 is a circuit diagram showing a configuration of a conventional power supply voltage step-down circuit. In the figure, 1 is a main step-down circuit that generates a step-down voltage when the step-down voltage using circuit 3 operates normally, and 2 is a current consumption of the step-down voltage using circuit 3 as when the step-down voltage using circuit 3 is in a standby state. Is a sub-step-down circuit that generates a step-down voltage when the voltage is small, 3 is a step-down voltage using circuit that uses the step-down voltage from the main step-down circuit 1 or the sub-step-down circuit 2 as a power source, and 4 is a main step-down circuit This is a power supply of the step-down voltage using circuit 3 connected to each output.

In the main step-down circuit 1, reference numeral 11 denotes a power source,
Reference numeral 12 denotes a P-channel transistor (hereinafter abbreviated as PchTr). The source 12a of the PchTr 12 is connected to the power supply 11, the drain 12b is connected to the step-down voltage output terminal 16, and the gate 12c is connected to the output of the differential amplifier 13. It is connected. Reference numeral 13 denotes a differential amplifier for amplifying a difference voltage between a reference voltage for determining a step-down voltage value and an input voltage,
This differential amplifier 13 is connected to the drain 12 of the PchTr 12.
b (step-down voltage output terminal 16) to amplify the difference voltage between the input voltage from reference voltage 14 and gate 12 of PchTr 12
output to c. The differential amplifier 13 operates based on the differential amplifier valid signal 15. Reference numeral 16 denotes a step-down voltage output terminal connected to the drain 12 b of the PchTr 12. The step-down voltage output from the step-down voltage output terminal 16 is supplied to the step-down voltage use circuit 3.

In the sub step-down circuit 2, 21A, 21
B and 21C are power supplies, and 22A and 22B are PchTr. The source 22Aa of the PchTr 22A is
A, and the drain 22Ab is connected to the step-down voltage output terminal 2
5, and the gate 22Ac is connected to a connection point between the drain 22Bb of the PchTr 22B and the resistor 24A. The source 22Ba of the PchTr 22B is connected to the power supply 2
1B, and the drain 22Bb is connected to the PchTr 22A.
Is connected to a connection point between the gate 22Ac and the resistor 24A,
The gate 22Bc includes a resistor 24B and a drain 23b of an N-channel transistor (hereinafter abbreviated as NchTr) 23.
Is connected to the connection point. Reference numeral 23 denotes an NchTr, and a source 23a of the NchTr 23 is a ground 26.
The drain 23b is connected to a connection point between the gate 22Bc of the PchTr 22B and the resistor 24B, and the gate 23c is connected to a connection point between the resistors 24C and 24D.

24A, 24B, 24C and 24D are resistors, and the resistor 24A is connected to the gate 22Ac of the PchTr 22A.
(A connection point between the PchTr 22B and the drain 22Bb)
And the ground 26, and the resistor 24B is connected to the Pch
Connected between the gate 22Bc of the Tr 22B (and the connection point of the drain 23b of the NchTr 23) and the power supply 21C,
The resistor 24C is connected between the step-down voltage output terminal 25 (and the step-down voltage output terminal 16) and the gate 23c of the NchTr 23, and the resistor 24D is connected between the gate 23c of the NchTr 23 and the ground 26. 25 is PchT
A step-down voltage output terminal connected to the drain 22Ab of r22A. The step-down voltage output from the step-down voltage output terminal 25 is supplied to the step-down voltage use circuit 3. The step-down voltage output terminal 25 is connected to the step-down voltage output terminal 16. Reference numeral 26 denotes a ground connected to the resistor 24A, the source 23a of the NchTr 23, and the resistor 24D.

Next, the operation will be described. First, the step-down function of the main step-down circuit 1 will be described. When the voltage value of the step-down voltage output terminal 16 of the main step-down circuit 1 rises above a certain step-down voltage value determined by the reference voltage 14, the voltage value that has been differentially amplified by the differential amplifier 13 and output is equal to the previous voltage. Rise above the value. The current flowing through the PchTr 12 is the gate 12c
When the voltage value of the gate 12c of the PchTr 12 rises, the PchTr 12 tends to turn off, and the current flowing through the PchTr 12 is limited, so that the voltage value of the drain 12b of the PchTr 12 decreases, The voltage value of the output terminal 16 decreases. vice versa,
When the voltage value of the step-down voltage output terminal 16 of the main step-down circuit 1 falls below a certain step-down voltage value determined by the reference voltage 14, the voltage value output by the differential amplifier 13 falls below the previous voltage value. , PchTr12 tends to turn on, the voltage value of the drain 12b of the PchTr12 increases, and the voltage value of the step-down voltage output terminal 16 increases.

By such feedback control, the main step-down circuit 1 is controlled so that the voltage value of the step-down voltage output terminal 16 becomes a constant step-down voltage value determined by the reference voltage 14. Here, the differential amplifier 13 quickly changes the output with respect to the input change in time, so that the step-down voltage value of the main step-down circuit 1 can be quickly corrected. However, on the other hand, since the current consumption of the differential amplifier 13 is large, the current consumption of the main step-down circuit 1 increases. Therefore,
When the step-down voltage using circuit 3 is in a standby state (a state where the step-down voltage using circuit 3 is not operating), the differential amplifier 13 is invalidated by the differential amplifier enable signal 15 (without operating the differential amplifier 13). The current consumption of the main step-down circuit 1 is suppressed by eliminating the output voltage) and stopping the operation of the main step-down circuit 1 (stopping the step-down by the main step-down circuit 1).

Next, the step-down function of the sub-step-down circuit 2 will be described. When the voltage value of the step-down voltage output terminal 25 of the sub-step-down circuit 2 falls below a certain step-down voltage value, since the step-down voltage output terminal 25 of the sub-step-down circuit 2 is connected to the resistors 24C and 24D, the resistor 24C , 24D, that is, the input voltage of the gate 23c of the NchTr 23 decreases. When the input voltage of the gate 23c decreases, the NchTr
23 tends to turn off, and the resistor 24B and the NchTr2
3, the potential at the connection point of the drain 23b, that is, PchTr2
The input voltage of the 2B gate 22Bc increases. Gate 22
When the input voltage of Bc increases, the PchTr 22B tends to turn off, and the potential at the connection point between the drain 22Bb of the PchTr 22B and the resistor 24A, that is, the input voltage of the gate 22Ac of the PchTr 22A decreases. When the input voltage of the gate 22Ac decreases, the PchTr 22A tends to turn on, and the voltage value of the drain 22Ab of the PchTr 22A increases.

Conversely, when the voltage value of the step-down voltage output terminal 25 of the sub-step-down circuit 2 rises, the above-mentioned functions operate in reverse, so that the voltage value of the step-down voltage output terminal 25 decreases. With such an operation, the sub-step-down circuit 2 tries to return to the original voltage value when the voltage value fluctuates, and outputs the constant voltage thus held from the step-down voltage output terminal 25.

In the sub-step-down circuit 2, the response of the correction to the output fluctuation of the step-down voltage value is worse (slower) than the main step-down circuit 1 using the differential amplifier 13. However, on the other hand, the power supply 4 and the ground 2
6, the resistors 24A to 24D are inserted.
Since the current is limited by the resistance values of 4A to 24D, the current consumption of the sub-step-down circuit 2 is smaller than the current consumption of the main step-down circuit 1.

As described above, the conventional step-down circuit is composed of the main step-down circuit 1 and the sub-step-down circuit 2. The main step-down circuit 1 can supply a large current to the step-down voltage use circuit 3 and can use the step-down voltage use circuit. 3, the correction when the step-down voltage value fluctuates due to the current consumption can be promptly performed to reduce the step-down voltage fluctuation, but the main step-down circuit 1
It has the feature that its own current consumption also increases,
Contrary to the main step-down circuit 1, the sub-step-down circuit 2 can supply only a small current to the step-down voltage use circuit 3, and the correction of the fluctuation of the step-down voltage value is slow, but the current consumption of the sub-step-down circuit 2 itself is small. Having. Therefore, when the step-down voltage using circuit 3 is in the standby state, the current consumption of the step-down voltage using circuit 3 is small and the current consumption hardly fluctuates. The current consumption of the entire circuit including the step-down circuit and the step-down voltage using circuit 3 can be suppressed.

As prior art related to the present application, Japanese Patent Application Laid-Open Nos. 54-23340 and 58-10054 are disclosed.
No. 4 publication.

[0014]

The conventional power supply voltage step-down circuit is constructed as described above.
In this case, since the step-down voltage correction circuit is formed by using the resistors 24A to 24D, the current consumption becomes small. However, the current consumption in the standby state of the step-down voltage using circuit 3 is several tens nA to several μA.
In such a case, the resistance value must be on the order of several MΩ to several hundred MΩ in order to make the current consumption of the sub-step-down circuit 2 itself a current value of this level.
However, in general, CMOS which constitutes a semiconductor circuit chip
In order to make such a resistor in a circuit, it is made of field or polysilicon, but since the resistance value per unit length is only several Ω to several tens Ω, the circuit area is very large There was a problem that it would be.

In the step-down circuit, the main step-down circuit 1 is controlled by a differential amplifier enable signal 15 to enable or disable the differential amplifier 13 (main step-down circuit 1).
Is not configured to perform such control (the sub-step-down circuit 2 is always operating). For example, when the main step-down circuit 1 is operated and the sub-step-down If you want to distinguish when the circuit 2 is operating,
When it is desired to change the step-down voltage value of the sub-step-down circuit 2, there is a problem that the sub-step-down circuit 2 cannot be selectively switched.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a power supply voltage step-down circuit capable of reducing the circuit area and operating by selectively switching sub-circuits. And

[0017]

SUMMARY OF THE INVENTION A power supply voltage step-down circuit according to the present invention generates a main step-down voltage when a step-down voltage using circuit normally operates by stepping down a main power supply voltage. Main step-down circuit section capable of correcting fluctuations and maintaining the main step-down voltage at a constant value, supplying a large current to the step-down voltage using circuit, and controlling the operation based on the main control signal, and stepping down the sub power supply voltage As a result, the sub-step-down voltage is generated when the step-down voltage using circuit is in the standby state, and the sub-step-down voltage is maintained substantially constant even when the current consumption of the step-down voltage using circuit fluctuates. And a sub-step-down circuit unit which can be supplied and whose operation can be controlled based on the sub-control signal.

In the power supply voltage step-down circuit according to the present invention, the sub-step-down circuit section includes a sub-power supply, a source and a gate of an N-channel transistor connected to the sub-power supply, and a drain connected to the step-down voltage use circuit. Or the source of the P-channel transistor is connected to the sub-power supply side, and the drain and gate thereof are connected to the step-down voltage use circuit side, thereby reducing the sub-power supply voltage and reducing the current consumption of the step-down voltage use circuit. It comprises a power supply voltage step-down means for maintaining the step-down voltage substantially constant even if it fluctuates, and a switch means provided between the sub-power supply and the power supply voltage step-down means for controlling opening and closing based on a sub-control signal.

In the power supply voltage step-down circuit according to the present invention, the power supply voltage step-down means is configured by connecting N-channel transistors or P-channel transistors in multiple stages in series.

In the power supply voltage step-down circuit according to the present invention, the timing at which the main control signal changes from the invalid signal level to the valid signal level, and the timing at which the sub control signal changes from the valid signal level to the invalid signal level, are temporally determined at the valid signal level. At the same time, the timing at which the main control signal changes from the valid signal level to the invalid signal level and the timing at which the sub-control signal changes from the invalid signal to the valid signal level are temporally overlapped at the valid signal level.

The power supply voltage step-down circuit according to the present invention is configured such that a plurality of sub-step-down circuit units are connected in parallel, and each of the plurality of sub-step-down circuit units is individually controlled based on a sub-control signal. Things.

In the power supply voltage step-down circuit according to the present invention, one or a plurality of power supply voltage step-down means of the sub-step-down circuit section connected in parallel is constituted by connecting a plurality of N-channel transistors or P-channel transistors in series. is there.

In the power supply voltage step-down circuit according to the present invention, a plurality of sub-step-down circuit sections connected in parallel are arranged at a distance from each other on a semiconductor circuit chip.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a power supply voltage step-down circuit according to a first embodiment of the present invention. In the figure, reference numeral 1 denotes a main step-down circuit (main step-down circuit) for generating a step-down voltage when a step-down voltage using circuit 3 operates normally. Step-down circuit section), 3
Is a step-down voltage using circuit that uses a step-down voltage from the main step-down circuit 1 or the sub step-down circuit 5 as a power supply, and 4 is a step-down voltage using circuit 3 connected to respective outputs of the main step-down circuit 1 and the sub step-down circuit 2. Power supply. The main step-down circuit 1, the step-down voltage using circuit 3, and the power supply 4
In FIG. 12, the configuration is the same as that of the related art with the same reference numeral. Reference numeral 5 denotes a sub-step-down circuit (sub-step-down circuit unit) for generating a step-down voltage when the current consumption of the step-down voltage use circuit 3 is small, such as when the step-down voltage use circuit 3 is in a standby state. 5 corresponds to the sub-step-down circuit 2 in FIG.

In the main step-down circuit 1, reference numeral 11 denotes a power supply (main power supply) and reference numeral 12 denotes a P-channel transistor (hereinafter abbreviated as PchTr).
2 has a source 12a connected to the power supply 11 and a drain 12a.
b is connected to the step-down voltage output terminal 16, and the gate 12 c is connected to the output of the differential amplifier 13. Reference numeral 13 denotes a differential amplifier for amplifying a difference voltage between a reference voltage for determining a step-down voltage value and an input voltage.
The voltage from the drain 12 b (step-down voltage output terminal 16) of the Pch Tr 12 is fed back and input. The difference voltage between the input voltage and the reference voltage 14 is amplified and output to the gate 12 c of the PchTr 12. The differential amplifier 13 operates based on a differential amplifier valid signal (main control signal) 15. Reference numeral 16 denotes a step-down voltage output terminal connected to the drain 12 b of the PchTr 12. The step-down voltage output from the step-down voltage output terminal 16 is supplied to the step-down voltage use circuit 3. The internal configuration of the main step-down circuit 1 is the same as the conventional one and has the same features as the conventional one.

In the sub-step-down circuit 5, reference numeral 51 denotes a power supply (sub-power supply), 52 denotes an NchTr (power supply voltage step-down means), and a source 52a and a gate 52 of the NchTr 52.
c is connected to a power supply 51 (switch 53) and drain 5
2b is connected to the step-down voltage output terminal 55. Reference numeral 53 denotes a switch (switch means) inserted between the NchTr 52 and the power supply 51. The on / off of the switch 53 is controlled by a switch control signal (sub-control signal) 54. Reference numeral 55 denotes a step-down voltage output terminal. The step-down voltage output from the step-down voltage output terminal 55 is supplied to the step-down voltage using circuit 3. The step-down voltage output terminal 55 is connected to the step-down voltage output terminal 16 of the main step-down circuit 1.

Next, the operation will be described. First, the step-down function of the main step-down circuit 1 will be described. Since the main step-down circuit 1 is the same as the conventional one shown in FIG. 12, the voltage of the power supply 11 is stepped down by the same operation.
That is, when the voltage value of the step-down voltage output terminal 16 of the main step-down circuit 1 rises above a certain step-down voltage value determined by the reference voltage 14, the voltage value that has been differentially amplified and output by the differential amplifier 13 has been changed. Voltage value. When the voltage value of the gate 12c of the PchTr 12 increases, the PchTr 12 tends to turn off, the voltage value of the drain 12b of the PchTr 12 decreases, and the voltage value of the step-down voltage output terminal 16 decreases. Conversely, when the voltage value of the step-down voltage output terminal 16 of the main step-down circuit 1 falls below a certain step-down voltage value determined by the reference voltage 14, the voltage value output from the differential amplifier 13 becomes lower than the voltage value up to that time. By lowering, the PchTr 12 tends to turn on, the voltage value of the drain 12b of the PchTr 12 increases, and the voltage value of the step-down voltage output terminal 16 increases.

As described above, the main step-down circuit 1 operates to return to the original voltage value when the voltage value fluctuates due to the feedback control. In addition, since the differential amplifier 13 changes the output fluctuation with respect to the input fluctuation quickly in time, the step-down voltage value of the main voltage-down circuit 1 can be quickly corrected. Further, when the step-down voltage using circuit 3 is in the standby state, the differential amplifier 13 is disabled by the differential amplifier enable signal 15 (the output voltage is lost without operating the differential amplifier 13),
The current consumption of the main step-down circuit 1 is suppressed by not operating the main step-down circuit 1 (without stepping down by the main step-down circuit 1).

Next, the step-down function of the sub step-down circuit 5 will be described. FIG. 2 is a graph showing the relationship between the current value (output current) flowing from the drain 52b when the voltage value of the source 52a is 5V in the NchTr 52 and the voltage value (step-down voltage) of the drain 52b. As shown in FIG. 2, when the current value flowing through the NchTr 52 is 0.1 nA to 100 μA, the voltage value of the drain 52 b is a voltage value of about 3 V to 4 V (about 1 V to 2 V step-down from a voltage value of 5 V of the power supply 51). doing). Thus, in the sub-step-down circuit 5 of FIG.
Even if the current value of the step-down voltage using circuit 3 in the standby state fluctuates in a large range such as 0.1 nA to 100 μA, the step-down voltage of the sub-step-down circuit 5 fluctuates only within a range of 1 V or less. Therefore, the sub step-down circuit 5 of FIG. 2 always supplies the power supply voltage of 5 V even if the current consumption of the step-down voltage using circuit 3 fluctuates.
To a constant voltage (3 V to 4 V). Since the sub-step-down circuit 5 does not maintain a constant step-down voltage by performing feedback control as in the conventional sub-step-down circuit 2 shown in FIG. 12, it cannot control the change in the step-down voltage. However, when the step-down voltage using circuit 3 is in the standby mode, the current consumption hardly changes, so that there is no particular problem.

As described above, in the sub-step-down circuit 5, when the current value does not change so much as in the standby state of the step-down voltage using circuit 3, the step-down voltage is held at a constant value with a simple circuit configuration. And the circuit scale can be realized with a very small size as compared with the prior art. Further, since the current consumption flowing through the sub-step-down circuit 5 itself becomes the current consumption flowing through the step-down voltage using circuit 3, N
There is no extra current consumed by the sub-step-down circuit 5 other than the current consumed by the chTr 52 (that is, in the sub-step-down circuit 5, as in the conventional sub-step-down circuit 2, the step-down voltage is used to hold the step-down voltage at a constant value). There is no current consumption flowing through the feedback circuit (correction circuit)).

Next, the operation of the switch 53 provided in the sub step-down circuit 5 will be described. Switch 53 is Nch
The switch 53 is inserted between the Tr 52 and the power supply 51, and the switch 53 is controlled to open and close by a switch control signal 54. Therefore,
Only when it is desired to operate the sub step-down circuit 5, the switch 5
3 can be turned on and the switch 53 can be turned off when unnecessary, so that it is necessary to distinguish between the operation of the main step-down circuit 1 and the operation of the sub-step-down circuit 5 as in the case of circuit evaluation of a semiconductor circuit chip. Such a demand can be met when only the sub-step-down circuit 5 is to be operated, for example, when it is desired to selectively change the step-down voltage of the sub-step-down circuit 5 as shown in the following embodiments.

As described above, according to the first embodiment, the sub step-down circuit 5 is connected to the source 52a of the NchTr 52.
And the gate 52c is connected to the power supply 51, and the drain 52b
Is connected to the step-down voltage output terminal 55 so that the voltage of the power supply 51 is stepped down only by the Nch Tr 52. Therefore, the step-down voltage of the step-down voltage using circuit 3 at the time of standby can be maintained at a constant value with a simple circuit configuration. As a result, the circuit area of the power supply voltage step-down circuit can be reduced (particularly, the sub-step-down circuit 5 uses the resistors 24A to 24D as in the conventional sub-step-down circuit 2 shown in FIG. 12). Since it is not configured, the circuit scale can be made very small). In addition, since there is no extra current consumed by the sub step-down circuit 5 other than the consumed current of the NchTr 52,
The power consumption of the power supply voltage step-down circuit can be suppressed when the step-down voltage using circuit 3 is on standby. Also, the switch 53
Is inserted between the NchTr 52 and the power supply 51, when it is desired to distinguish between the operation of the main step-down circuit 1 and the operation of the sub-step-down circuit 5 as in the case of circuit evaluation of a semiconductor circuit chip, Such a request can be met even when it is desired to operate only the sub-step-down circuit 5 when the step-down voltage is to be selectively changed.

Embodiment 2 FIG. In the first embodiment, the sub step-down circuit 5 is configured using the NchTr 52, but may be configured using the PchTr. FIG. 3 shows a sub-step-down circuit 5 configured using such a PchTr.
FIG. 5 is a circuit diagram showing a PchTr
The source 56a of the Pch Tr 56 is connected to the power supply 51, and the drain 56b and the gate 56c are connected to a step-down voltage output terminal 55 (not shown in FIG. 3). In FIG. 3, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The switch 53 is omitted in the sub-step-down circuit 5 shown in FIG. FIG. 4 shows a case where the voltage of the source 56a of the PchTr 56 is 5V and the drain 56b
4 is a graph showing a relationship between a current value (output current) flowing from the transistor and a voltage value (step-down voltage) of a drain 56b. As shown in FIG. 4, even in the sub-step-down circuit 5 configured using the PchTr 56, the power supply voltage 5 is always maintained even when the current consumption of the step-down voltage using circuit 3 fluctuates, similarly to the NchTr 52 shown in FIG.
V can be reduced to maintain a constant voltage (3 V to 4 V).

Embodiment 3 In the first and second embodiments, the sub step-down circuit 5 is configured by connecting the NchTr 52 and the PchTr 56 in one stage. However, the NchTr 52 and the PchTr 56 are connected in multiple stages to form a sub-step-down circuit. You may make it. FIG.
Sets the sub-step-down circuit 5 to NchTr 52 or P
FIG. 5A is a circuit diagram showing a case in which NchTrs are provided in multiple stages, and FIG. 5B is a circuit diagram showing a case in which PchTrs are provided in multiple stages. . As described above, by connecting the NchTrs (power supply voltage step-down means) 521 and 522 or the PchTrs (power supply voltage step-down means) 561 and 562 in series in multiple stages to constitute the sub step-down circuit 5, a desired step-down voltage can be easily obtained. be able to. For example, as shown in FIG. 2 and FIG. 4, assuming that the stepped-down voltage per one stage of the NchTr 52 and the PchTr 56 is about 1 V to 2 V, the power supply voltage 10 V is reduced by 3 V, and the voltage 7 V is reduced to 7 V.
If you want to use NchTr 521,5
22 or PcHTr 561 and 562 may be connected to form sub-step-down circuit 5.

Embodiment 4 FIG. In the fourth embodiment, the operation timing of the differential amplifier enable signal 15 for controlling the operation of the differential amplifier 13 of the main step-down circuit 1 and the opening / closing of the switch 53 of the sub-step-down circuit 5 are controlled. The switching operation of the main step-down circuit 1 and the sub-step-down circuit 2 is performed in consideration of the switch timing of the switch control signal 54. FIG. 6 is a timing chart of the differential amplifier valid signal 15 and the switch control signal 54. In FIG. 6, the differential amplifier 13
Of the differential amplifier valid signal 15 and the switch control signal 54 of the switch 53 are both valid signal levels (signal levels for operating the differential amplifier 13 and closing the switch 53) and "L". The level is an invalid signal level (a signal level that does not operate the differential amplifier 13 and opens the switch 53).

As shown in FIG. 6, the differential amplifier valid signal 1
5 changes from the L level to the H level, and the switch control signal 5
4 changes from H level to L level (hereinafter referred to as
This timing is referred to as timing 1). At H level, there is a partial temporal overlap. Conversely, the differential amplifier valid signal 15 changes from H level to L level, and the switch control signal 54 changes from L level to H level. The changing timing (hereinafter, this timing is referred to as timing 2) has no temporal overlap.

At timing 1, the sub step-down circuit 5
When the main step-down circuit 1 changes from invalid to valid after the state changes from valid to invalid, there is a time when both the step-down circuits 1 and 5 become invalid, and the step-down voltage using circuit 3 operates at that time. If the current consumption suddenly increases, the step-down voltage may become unstable. Therefore, for safety, there is provided a time overlap in which both the step-down circuits 1 and 5 are effective. Conversely, at timing 2,
Even if the sub-step-down circuit 5 changes from invalid to valid after a certain period of time has elapsed since the main step-down circuit 1 changed from valid to invalid, the step-down voltage using circuit 3 changes to the standby state at this time and the current consumption is reduced. Becomes smaller, the electric charge held by the power supply 4 of the step-down voltage using circuit 3 depends on the voltage value of the step-down voltage output terminal 16 when the main step-down circuit 1 is operating, until the sub-step-down circuit 5 starts operating. Can hold the voltage for the time. For this reason, there is no need to set the time overlap of the signals as in the timing 1 at the timing 2, so that the differential amplifier valid signal 15 and the switch control signal 54 are simultaneously switched.

FIG. 7 is a block diagram showing a signal control circuit for generating the signal timing shown in FIG. 6. In FIG. 7, reference numeral 6 denotes a signal control circuit for generating the signal timing. And four inverter gates 62. A is the output of the fourth inverter 62 of the four inverter gates 62 connected in series. The differential amplifier valid signal 15 is input to the signal control circuit 6. This differential amplifier valid signal 15 branches into two signals, one of which is directly input to one input terminal of the NAND gate 61 and
Gate 62 in which four signals are connected in series
(The output A) is input to another input terminal of the NAND gate 61. And this NAND gate 6
The output of 1 becomes the switch control signal 54 of the sub step-down circuit 5.

Next, the fact that the signal timing shown in FIG. 6 can be generated by the signal control circuit 6 having such a circuit configuration will be described with reference to FIG. FIG. 8 is a diagram for explaining signal timing of the signal control circuit 6.
The output A of the fourth inverter gate 62 is a signal delayed from the differential amplifier valid signal 15 by the total delay time of each inverter gate 62 because the inverter gates 62 are connected in series. The NAND gate 61 that inputs these two signals outputs an L level only when both inputs are at the H level, and outputs an H level when one of the inputs is also at the L level. Can be provided between the differential amplifier valid signal 15 of the main step-down circuit 1 and the switch control signal 54 of the sub-step-down circuit 5.

As described above, according to the fourth embodiment, the timing of the switching operation between the main step-down circuit 1 and the sub-step-down circuit 2 is set such that the timing 1 overlaps the H level (valid signal level) with time. In the timing 2, the temporal overlap of the H level (effective signal level) is not provided (switched at the same time), so that there is no possibility that the step-down voltage becomes unstable, and the step-down voltage using circuit 3 operates stably. Can be.

Embodiment 5 FIG. In the fifth embodiment, a plurality of sub-step-down circuits 5 in the first embodiment are connected in parallel to form a sub-step-down circuit 5. FIG. 9 is a circuit diagram showing a configuration of such a sub-step-down circuit of a power supply voltage step-down circuit according to a fifth embodiment of the present invention. In the figure, reference numerals 5A and 5B denote sub-step-down circuits (sub-step-down circuits) respectively connected in parallel. Circuit unit), 51A and 51B are power supplies, 52
A and 52B are NchTr (power supply voltage step-down means), 53
A and 53B are switches, and 54A and 54B are switch control signals (sub-control signals). In FIG. 9, since the configurations of the main step-down circuit 1, the step-down voltage using circuit 3, and the power supply 4 are the same as those in FIG. 1, only the configuration of the sub step-down circuits 5A and 5B is shown. A plurality of sub step-down circuits 5A and 5B are connected in parallel, and switch control signals 54A and 54B for controlling the operation of each sub-step-down circuit 5A and 5B are individually controlled as sub-step-down circuits 5A and 5B. I can do it. Therefore, the sub-step-down circuits 5A and 5B which are enabled during the standby state of the step-down voltage using circuit 3
By selecting the number, the step-down voltage value can be changed.

Further, at the time of product evaluation of the step-down circuit, the number of sub-step-down circuits 5 to be made effective in this way is evaluated while being variously changed.
In the case of A), even when the required standby current cannot be supplied, the required standby current can be supplied by enabling the plurality of sub-step-down circuits (5A, 5B). In this case, the number of sub-step-down circuits 5 required to supply the standby current is enabled, and the other sub-step-down circuits 5
By disabling, the unnecessary current consumption can be suppressed.

In the fifth embodiment, the NchTr 52
, The sub-step-down circuit 5 is configured using the PchTr 56 as in the second embodiment.
May be configured.

Embodiment 6 FIG. In the sixth embodiment, a plurality of NchTrs 52 are connected in series in the plurality of sub-step-down circuits 5 connected in parallel in the fifth embodiment. FIG. 10 shows such a sixth embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a sub-step-down circuit of a power supply voltage step-down circuit according to FIG.
Tr (power supply voltage step-down means). The other configuration is the same as that shown in FIG. 9, and thus redundant description will be omitted.

In the fifth embodiment, a plurality of sub step-down circuits 5 with switches 53 are connected in parallel. In the sixth embodiment, switches 5 connected in parallel are connected.
One or more of the sub-step-down circuits 5 with 3
2A and 52B are connected in series. FIG. 10 shows only a plurality of NchTs for the sub-step-down circuit 5B.
This figure shows a configuration in which r521B and 522B are connected in series. With such a configuration, the switch control signals 54A, 54A,
By individually controlling the validity / invalidity of the 54B, the step-down voltage can be easily changed, and the step-down voltage value can be variously adjusted.

In the sixth embodiment, the NchTr 52
, The sub-step-down circuit 5 is configured using the PchTr 56 as in the second embodiment.
May be configured.

Embodiment 7 FIG. FIG. 11 is a configuration diagram showing a semiconductor circuit chip on which a power supply voltage step-down circuit is mounted. In the figure, 7 is a semiconductor circuit chip, 71 is a region where the main step-down circuit 1 of the semiconductor circuit chip 7 is disposed, 72 is a region where the sub-step-down circuit 5A is disposed, and 73 is a region where the step-down voltage using circuit 3 is disposed. , 74 are regions where another sub step-down circuit 5B is arranged, and 75 is a step-down output wiring.

The semiconductor circuit chip 7 shown in FIG. 11 has a plurality of sub-step-down circuits 5A and 5B connected in parallel as described in the fifth and sixth embodiments. Then, as shown in FIG. 11, the respective sub-step-down circuits 5A and 5B are arranged on the semiconductor circuit chip 7 at positions spaced apart from each other. By arranging the sub-step-down circuits 5A and 5B at positions separated from each other on the semiconductor circuit chip 7, even if the sub-step-down circuit 5A does not operate due to a defect in the formation of the semiconductor circuit chip 7, for example, 5B is spaced apart from the sub-step-down circuit 5A, the defect of the semiconductor circuit chip 7 does not affect,
The sub-step-down circuit 5B can be operated, and the yield of the semiconductor circuit chip 7 can be increased.

[0049]

As described above, according to the present invention, the main power supply voltage is stepped down to generate the main stepped-down voltage when the step-down voltage using circuit normally operates, and the fluctuation of the main stepped-down voltage is corrected. A main step-down circuit unit capable of supplying a large current to the step-down voltage using circuit which holds the main step-down voltage at a constant value and capable of controlling the operation based on the main control signal, and stepping down by lowering the sub power supply voltage The sub-step-down voltage is generated when the voltage using circuit is in the standby state, and the sub-step-down voltage is kept almost constant even if the current consumption of the step-down voltage using circuit fluctuates. And a sub-step-down circuit unit that can be operated based on the sub-control signal, so that the operation of the main step-down circuit unit and the operation of the sub-step-down circuit unit are distinguished. Or if you want, when you want to change selection step-down voltage of the sub-step-down circuit, there is an effect that can be operated only the sub step-down circuit.

According to the present invention, the sub-step-down circuit section is configured such that the sub-power supply, the source and the gate of the N-channel transistor are connected to the sub-power supply side, and the drain is connected to the step-down voltage use circuit side, or The source of the P-channel transistor is connected to the sub-power supply side, and the drain and gate thereof are connected to the step-down voltage use circuit side, so that the sub-power supply voltage is stepped down and the current consumption of the step-down voltage use circuit fluctuates. The power supply voltage step-down means for maintaining the step-down voltage substantially constant, and the switch means provided between the sub power supply and the power supply voltage step-down means for opening and closing control based on the sub-control signal. The step-down voltage at the time can be maintained at a constant value with a simple circuit configuration, and as a result, the circuit area of the power supply voltage step-down circuit can be reduced. There can be effectively. In addition, since the current consumption excessively consumed by the sub-step-down circuit section does not exist other than the current consumption of the N-channel transistor, there is an effect that the power consumption of the power supply voltage step-down circuit can be suppressed at the time of standby of the step-down voltage using circuit.

According to the present invention, the power supply voltage step-down means
Since an N-channel transistor or a P-channel transistor is connected in multiple stages in series, there is an effect that a desired step-down voltage can be easily obtained.

According to the present invention, the timing at which the main control signal changes from the invalid signal level to the valid signal level and the timing at which the sub-control signal changes from the valid signal level to the invalid signal level are temporally overlapped at the valid signal level. On the other hand, the timing at which the main control signal changes from the valid signal level to the invalid signal level and the timing at which the sub control signal changes from the invalid signal to the valid signal level are temporally overlapped at the valid signal level. Therefore, there is an effect that the step-down voltage using circuit can be operated stably.

According to the present invention, a plurality of sub-step-down circuit units are connected in parallel, and each of the plurality of sub-step-down circuit units is individually controlled based on the sub-control signal. By selecting the number of sub-step-down circuit sections that are valid at the time of standby of the used circuit, there is an effect that the step-down voltage value can be changed. In addition, by changing the number of sub-step-down circuit units to be enabled in various ways, even if one sub-step-down circuit unit cannot supply a necessary standby current, it is necessary to enable a plurality of sub-step-down circuit units to There is an effect that a standby current can be supplied.

According to this invention, one or more power supply voltage step-down means of the sub-step-down circuit unit connected in parallel is constituted by connecting a plurality of N-channel transistors or P-channel transistors in series. By individually controlling the validity / invalidity of each sub-control signal, there is an effect that the step-down voltage can be easily changed and the step-down voltage value can be variously adjusted.

According to the present invention, a plurality of sub-step-down circuit portions connected in parallel are arranged at positions spaced apart from each other on the semiconductor circuit chip. Even when the step-down circuit unit does not operate, another sub-step-down circuit unit is separated from one sub-step-down circuit unit in distance, so that the defect of the semiconductor circuit chip does not affect and another sub-step-down circuit unit operates. This has the effect of increasing the yield of semiconductor circuit chips.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power supply voltage step-down circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing a relationship between a current value (output current) flowing from a drain and a drain voltage value (step-down voltage) when a source voltage value is 5 V in an NchTr.

FIG. 3 is a circuit diagram showing a case where a sub-step-down circuit is configured using PchTr.

FIG. 4 is a graph showing a relationship between a current value (output current) flowing from a drain and a drain voltage value (step-down voltage) at a source voltage value of 5 V in the PchTr.

FIG. 5 shows a NchTr or PchTr sub-step-down circuit.
Is a circuit diagram configured by connecting in a multistage series.

FIG. 6 is a timing chart of a differential amplifier valid signal and a switch control signal.

FIG. 7 is a configuration diagram illustrating a signal control circuit that generates the signal timings of FIG. 6;

FIG. 8 is a diagram for explaining signal timing of a signal control circuit.

FIG. 9 is a circuit diagram showing a configuration of a sub-step-down circuit of a power supply voltage step-down circuit according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a sub-step-down circuit of a power supply voltage step-down circuit according to a sixth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a semiconductor circuit chip on which a power supply voltage step-down circuit is mounted.

FIG. 12 is a circuit diagram showing a configuration of a conventional power supply voltage step-down circuit.

[Explanation of symbols]

1 main step-down circuit (main step-down circuit), 3 step-down voltage using circuit, 5, 5A, 5B sub-step-down circuit (sub-step-down circuit), 7 semiconductor circuit chip, 11 power supply (main power supply), 15 differential amplifier valid signal (Main control signal), 51 power supply (sub power supply), 52, 52A, 52
B, 521, 522, 521B, 522B N-channel transistors (power supply voltage step-down means), 52a, 56a
Source, 52b, 56b Drain, 52c, 56c
Gate, 53 switch (switch means), 54, 54
A, 54B switch control signal (sub control signal), 5
6,561,562 P-channel transistor (power supply voltage step-down means).

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/822

Claims (7)

[Claims] 1. A step-down main power supply voltage is generated to generate a main step-down voltage when a step-down voltage using circuit normally operates, and a fluctuation of the main step-down voltage is corrected to maintain the main step-down voltage at a constant value. A main step-down circuit section capable of supplying a large current to the step-down voltage using circuit and capable of controlling the operation based on a main control signal, and a step-down state of the step-down voltage using circuit by stepping down a sub power supply voltage. The sub-step-down voltage is generated, and the sub-step-down voltage is maintained substantially constant even when the current consumption of the step-down voltage using circuit fluctuates. A small current can be supplied to the step-down voltage using circuit, and the sub control signal A power supply voltage step-down circuit comprising: a sub-step-down circuit unit whose operation can be controlled based on the power supply voltage. 2. The sub-step-down circuit section comprises a sub-power supply, a source and a gate of an N-channel transistor connected to the sub-power supply side, and a drain connected to a step-down voltage using circuit side, or a P-channel transistor. Is connected to the sub-power supply side, and its drain and gate are connected to the step-down voltage using circuit side, so that the sub-power supply voltage is stepped down and the current consumption of the step-down voltage using circuit fluctuates. A power supply voltage step-down means for maintaining a step-down voltage substantially constant, and a switch means provided between the sub-power supply and the power supply voltage step-down means for opening and closing control based on a sub-control signal. The power supply voltage step-down circuit according to claim 1. 3. The power supply voltage step-down circuit according to claim 2, wherein the power supply voltage step-down means is configured by connecting an N-channel transistor or a P-channel transistor in multiple stages in series. 4. The main control signal changes from an invalid signal level to a valid signal level, and the sub control signal changes from a valid signal level to an invalid signal level. 2. The power supply voltage according to claim 1, wherein the timing at which the signal changes from the valid signal level to the invalid signal level and the timing at which the sub-control signal changes from the invalid signal to the valid signal level have no temporal overlap in the valid signal level. Step-down circuit. 5. The power supply voltage according to claim 2, wherein a plurality of sub-step-down circuit units are connected in parallel, and each of the plurality of sub-step-down circuit units is individually controlled based on a sub-control signal. Step-down circuit. 6. The power supply voltage step-down means of one or more of the sub-step-down circuit sections connected in parallel is constituted by connecting a plurality of N-channel transistors or P-channel transistors in series. Power supply voltage step-down circuit. 7. The power supply voltage according to claim 5, wherein a plurality of sub-step-down circuit portions connected in parallel are arranged at positions spaced apart from each other on the semiconductor circuit chip. Step-down circuit.