JP2002305245A - Voltage-generating circuit, semiconductor device and control method of the voltage-generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage-generating circuit which can prevent generation of a punch through current in the case of transition to a power-down mode. SOLUTION: A voltage forming part 11 forms an internal voltage Vdd and outputs it, on the basis of input of a reference voltage Vg. A reference voltage clamping circuit 21 clamps the reference voltage Vg to be a first potential Vss, which makes the voltage forming part 11 inactive, on the basis of input of a power-down signal pd. An internal voltage clamping circuit 22 clamps the internal voltage Vdd to be a second potential Vss. A control part 12 operates the clamping circuit 22, after the voltage-forming part 11 is made inactive, on the basis of input of the power-down signal pd.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generation circuit mounted on a semiconductor device. Some semiconductor devices are equipped with a voltage generation circuit that generates an internal power supply voltage different from the external power supply voltage based on the supply of the external power supply and supplies the generated internal power supply voltage to an internal circuit. In a semiconductor device in which a voltage generation circuit is configured by a step-down circuit, it is possible to cope with a reduction in power consumption of an internal circuit or a reduction in a gate breakdown voltage and a drain-source breakdown voltage accompanying miniaturization of a transistor.
In a semiconductor device mounted in a system having a power-down mode, the operation of the voltage generation circuit is inactivated in the power-down mode, and current consumption in the internal circuit is cut off.

[0002]

2. Description of the Related Art FIG. 10 shows a voltage generating circuit constituted by a step-down circuit using N-channel MOS transistors. The external power supply Vcc is supplied to the drain of the step-down transistor Tr1 composed of an N-channel MOS transistor, and the reference voltage Vg supplied from the reference potential generation circuit is input to the gate.

The internal circuit 1 is connected to the source of the step-down transistor Tr1. Then, when the reference voltage Vg is supplied, the internal circuit 1 is supplied with the internal voltage Vdd obtained by lowering the reference voltage Vg by the threshold value Vthn of the transistor Tr1 as a power supply.

The gate of the transistor Tr1 and the power supply Vss
Is connected to a capacitor C1. This capacity C1
Is to reduce the coupling noise generated in the reference voltage Vg based on the fluctuation of the internal voltage Vdd.

A reference voltage clamping transistor Tr2 composed of an N-channel MOS transistor is connected between the gate of the transistor Tr1 and the power supply Vss. The power down signal pd is supplied to the gate of the transistor Tr2. Is entered.

Accordingly, as shown in FIG. 12, when the power down signal pd goes high in the power down mode, the transistor Tr2 is turned on, the reference voltage Vg is clamped at the power supply Vss level, and the transistor Tr1 is turned off. .

[0007] A capacitor C2 is connected between the internal voltage Vdd and the power supply Vss. This capacitor C2 stabilizes the internal voltage Vdd. The capacitance C2 includes the parasitic capacitance of the internal circuit 1.

An internal voltage clamping transistor Tr3 composed of an N-channel MOS transistor is connected between the internal voltage Vdd and the power supply Vss, and a power down signal pd is input to the gate of the transistor Tr3. .

Therefore, when the power down signal pd goes high, the transistor Tr3 is turned on with the transistor Tr1 turned off as described above, and the internal voltage Vdd is clamped to the power supply Vss level as shown in FIG. Is done.

By such an operation, the supply of the internal voltage Vdd is cut off in the power down mode, and the internal circuit 1 is turned off.
The current consumption at is cut off. FIG. 11 shows a P-channel MO
1 shows a voltage generation circuit formed by a step-down circuit using S transistors. The external power supply Vcc is supplied to the source of the step-down transistor Tr4 composed of a P-channel MOS transistor, and the reference voltage Vg supplied from the reference potential generation circuit is input to the gate.

The reference voltage Vg rises with the rise of the internal voltage Vdd and drops with the fall of the internal voltage Vdd due to the operation of the reference potential generating circuit, so that the internal voltage Vdd falls a predetermined voltage from the power supply Vcc. Set to be level.

The drain of the step-down transistor Tr4 has
The internal circuit 1 is connected. When the reference voltage Vg is supplied, the internal circuit 1 is supplied with the internal voltage Vdd as a power supply.

The gate of the transistor Tr4 and the power supply Vcc
Is connected to a reference voltage clamping transistor Tr5 composed of a P-channel MOS transistor. The gate of the transistor Tr5 has a power-down signal p
d is input via the inverter circuit 2.

Therefore, when the power down signal pd goes high in the power down mode, the transistor Tr5 is turned on, the reference voltage Vg is clamped at the power supply Vcc level, and the transistor Tr4 is turned off, as shown in FIG. .

A capacitor C4 is connected between the internal voltage Vdd and the power supply Vss. This capacitor C4 stabilizes the internal voltage Vdd. The capacitance C4 includes the parasitic capacitance of the internal circuit 1.

An internal voltage clamping transistor Tr6 composed of an N-channel MOS transistor is connected between the internal voltage Vdd and the power supply Vss, and a power down signal pd is input to the gate of the transistor Tr6. .

Accordingly, when the power down signal pd goes high, the transistor Tr6 is turned on with the transistor Tr4 turned off as described above, and the internal voltage Vdd is clamped to the power supply Vss level as shown in FIG. Is done.

By such an operation, the supply of the internal voltage Vdd is cut off in the power down mode, and the internal circuit 1
The current consumption at is cut off.

[0019]

In the step-down circuit shown in FIG. 10, when the power-down signal pd goes high in the power-down mode, the transistors Tr2 and Tr3 are turned on, and as shown in FIG. And internal voltage V
dd decreases.

At this time, since the capacitance value of the capacitor C1 and the capacitance value of the transistor Tr1 are very large with respect to the driving capability of the transistor Tr2, the reference voltage Vg is gradually reduced based on the CR time constant based on the ON operation of the transistor Tr2. descend.

Then, at time t1 until the potential difference between the reference voltage Vg and the internal voltage Vdd becomes equal to or less than the threshold value Vthn of the transistor Tr1, the transistors Tr1 and Tr3 are simultaneously turned on, and the through current flows from the power supply Vcc to the power supply Vss. Flows.

Therefore, the through current may cause a voltage drop of the power supply Vcc or malfunction of the internal circuit 1. Also in the step-down circuit shown in FIG. 11, when the power down signal pd goes high in the power down mode, the transistors Tr5 and Tr6 are turned on, and as shown in FIG. 13, the reference voltage Vg rises and the internal voltage Vdd falls. I do.

At this time, since the capacitance value of the transistor Tr4 is very large with respect to the driving capability of the transistor Tr5,
Based on the ON operation of the transistor Tr5, the reference voltage Vg
Rises slowly based on the CR time constant.

Then, at time t2 until the potential difference between the reference voltage Vg and the power supply Vcc becomes equal to or less than the threshold value Vthp of the transistor Tr4, the transistors Tr4 and Tr6 are simultaneously turned on, and a through current flows from the power supply Vcc to the power supply Vss. Flows.

Therefore, the through current may cause a voltage drop of the power supply Vcc or malfunction of the internal circuit 1. In each of the above conventional examples, the transistors Tr2, T
By increasing the size of r5 and increasing the current driving capability, the reference voltage Vg can be reduced or increased at high speed.

However, the capacitance C1 and the transistors Tr1, T
If the size of the transistors Tr2 and Tr5 is increased so as to secure a load driving capability corresponding to the capacity of r4, there is a problem that the circuit area increases and hinders high integration.

An object of the present invention is to provide a voltage generating circuit capable of preventing generation of a through current when shifting to a power down mode.

[0028]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the voltage generator 11 outputs the reference voltage V
Based on the input of g, generate and output the internal voltage Vdd,
The reference voltage clamp circuit 21 clamps the reference voltage Vg to a first potential Vss for inactivating the voltage generation unit 11 based on the input of the power down signal pd. The internal voltage clamp circuit 22 clamps the internal voltage Vdd to the second potential Vss, and the control unit 12 controls the voltage generation unit 11 based on the input of the power down signal pd after inactivating the voltage generation unit 11. The internal voltage clamp circuit 22 is operated.

[0029]

(First Embodiment) FIG. 2 shows a first embodiment of a voltage generating circuit embodying the present invention. This embodiment includes a step-down circuit 11a and a control unit 12a that controls the operation of the step-down circuit 11a in the power down mode. The step-down circuit 11a is configured as shown in FIG.
Since the configuration is the same as that of the conventional example shown in FIG.

The control unit 12a includes a reference voltage detection unit 13a
And a clamp signal generator 14a. In the reference voltage detecting section 13a, the source of the P-channel MOS transistor Tr11 is connected to the power supply Vcc, and the drain is connected to the N-channel MOS transistor Tr12, via a resistor R1.
Connected to the drain of Tr13. The resistance value of the resistor R1 is set to a value sufficiently larger than the ON resistance of the transistor Tr12.

The power down signal pd is input to the gates of the transistors Tr11 and Tr13 via the inverter circuit 15a, and the gate of the transistor Tr12 is
The reference voltage Vg is input.

Therefore, in the reference voltage detecting section 13a, when the power down signal pd is at L level, the transistor T
Since transistor r11 is turned off and transistor Tr13 is turned on, transistor Tr1 is turned on regardless of reference voltage Vg.
2. The node N1, which is the drain potential of Tr13, is at L level.

When the reference voltage Vg is higher than the power supply Vss by more than the threshold value Vthn of the transistor Tr12 when the power-down signal pd goes high, the transistor Tr11 is turned on and the transistor Tr is turned on.
Since 123 is turned on, node N1 is at L level.

When the power down signal pd goes high and the reference voltage Vg goes low, the transistor Tr11 is turned on and the transistors Tr12 and Tr12 are turned on.
Since Tr13 is turned off, the node N1 goes high.

The node N1 is input to the inverter circuit 15b, and the output signal of the inverter circuit 15b is output as the node N2 to the clamp signal generator 14a.
The clamp signal generation unit 14a includes the NAND circuits 16a, 1
6b and an inverter circuit 15c.

The output signal of the inverter circuit 15b is
Input to NAND circuit 16a. The NAND circuit 1
The output signal of 6a is input to the NAND circuit 16b, and the power down signal pd is input to the NAND circuit 16b.

The output signal of the NAND circuit 16b is N
The signal is input to the AND circuit 16a and to the inverter circuit 15c. And the inverter circuit 15c
Is input to the gate of the internal voltage clamping transistor Tr3 of the step-down circuit 11a.

Therefore, when the power down signal pd is at L level, the output signal of the NAND circuit 16b goes to H level, the node N3 goes to L level, and the transistor T
r3 is turned off.

When the power down signal pd goes high and the node N1 goes high, the input signals of the NAND circuit 16b both go high and the NAND circuit 16b goes high.
The output signal of D circuit 16b attains L level, and node N3
Becomes H level, and the transistor Tr3 is turned on.

Next, the operation of the voltage generating circuit configured as described above will be described with reference to FIG. When the L-level power down signal pd is input in the normal mode, the transistor Tr2 in the step-down circuit 11a is turned off, and the node N3 is set to the L level, so that the transistor Tr3
Is turned off, and based on the input of the reference voltage Vg, the internal voltage V
dd is output to the internal circuit 1.

When the mode shifts from the normal mode to the power down mode, the input of the reference voltage Vg is stopped, and when the power down signal pd goes to the H level, the transistor Tr2 is turned on by the step-down circuit 11a, and the charge of the capacitor C1 is reduced. The reference voltage V is discharged and input to the gate of the transistor Tr1.
g gradually decreases.

When the potential difference between the reference voltage Vg and the internal voltage Vdd becomes equal to or less than the threshold value Vthn of the transistor Tr1, the transistor Tr1 is turned off. In the reference voltage detecting section 13a, the transistor Tr11 is turned on and the transistor Tr13 is turned off.

At this time, if the reference voltage Vg is higher than the power supply Vss by more than the threshold value Vthn of the transistor Tr12, the transistor Tr12 is turned on.
Node N1 is maintained at L level, and node N2 is maintained at H level. Therefore, the node N3 is maintained at the L level, and the transistor Tr3 is kept turned off.

Next, when the potential difference between the reference voltage Vg and the power supply Vss becomes equal to or less than the threshold value Vthn of the transistor Tr12,
The transistor Tr12 is turned off, the node N1 goes high, and the node N2 goes low.

Then, both the input signals of the NAND circuit 16b become H level, the node N3 becomes H level, and the transistor Tr3 is turned on. Then, based on the ON operation of the transistor Tr3, the internal voltage Vdd is
Decrease to ss level.

With the internal voltage generating circuit configured as described above, the following operation and effect can be obtained. (1) In the power down mode, the transistor Tr1 is turned off by the step-down circuit 11a, and the transistor T1 is turned off.
By turning on r3, the internal voltage Vdd can be reduced to the power supply Vss level. Therefore, in the power down mode, unnecessary current consumption in the internal circuit 1 can be reduced. (2) When transitioning from the normal operation to the power-down mode, the operation of the control unit 12a turns off the transistor Tr1 and then turns on the transistor Tr3 to lower the internal voltage Vdd to the power supply Vss level.
Therefore, the through current from the power supply Vcc to the power supply Vss in the step-down circuit 11a can be cut off. (3) In the normal mode, the current consumption in the reference voltage detector 13a can be cut off. (Second Embodiment) FIG. 4 shows a second embodiment of a voltage generation circuit embodying the present invention. This embodiment includes a control unit 12b and a step-down circuit 11a, and the step-down circuit 11a is the same as in the first embodiment.

The control unit 12b includes a reference voltage detection unit 13b
And a clamp signal generator 14b. The reference voltage generator 13b is formed of a differential amplifier, and the sources of the P-channel MOS transistors Tr14 to Tr16 are connected to a power supply Vcc.
It is connected to the.

The gates of the transistors Tr14 and Tr15 are connected to each other and to the drain of the transistor Tr14, and the drain of the transistor Tr14 is connected to the drain of the N-channel MOS transistor Tr17.

The drains of the transistors Tr15 and Tr16 are connected to an N-channel MOS transistor T
Connected to the drain of r18. The sources of the transistors Tr17 and Tr18 are connected to a power supply Vss via an N-channel MOS transistor Tr19.

The reference voltage Vg is input to the gate of the transistor Tr17, and the power down signal pd is input to the gates of the transistors Tr16 and Tr19. The node N6 is connected to the gate of the transistor Tr18. The node N6 is connected to a power supply Vcc via a resistor R2, and a resistor R3 and an N-channel MOS transistor T
Connected to power supply Vss via r20. The power down signal pd is input to the gate of the transistor Tr20.

Therefore, when the power down signal pd goes high and the transistor Tr20 is turned on, a voltage obtained by dividing the potential difference between the power supply Vcc and the power supply Vss by the resistors R2 and R3 is input to the gate of the transistor Tr18. , The voltage of which is substantially set to the threshold value Vthn of the transistor Tr17.

The node N4 is connected to the clamp signal generator 1
4b, and the output signal of the inverter circuit 15d is input to the gate of the transistor Tr3 of the step-down circuit 11 as the node N5.

Next, the operation of the voltage generating circuit configured as described above will be described with reference to FIG. When the L-level power down signal pd is input in the normal mode, the transistor Tr2 in the step-down circuit 11a is turned off. Also,
In the reference voltage detector 13b, the transistor Tr16 is turned on, the node N4 goes to the H level, and the node N5
Becomes L level, the transistor Tr3 is turned off, and the internal voltage Vdd is changed to the internal circuit 1 based on the input of the reference voltage Vg.
Is output to

In the power down mode, when the input of the reference voltage Vg is stopped and the power down signal pd goes to the H level, the transistor Tr2 is turned on in the step-down circuit 11a, and the charge of the capacitor C1 is discharged. When the reference voltage Vg input to the gate of the transistor Tr1 gradually decreases, and the potential difference between the reference voltage Vg and the internal voltage Vdd becomes equal to or less than the threshold value Vthn of the transistor Tr1, the transistor Tr1
1 is turned off.

In the reference voltage detector 13b, the transistor Tr16 is turned off and the transistor Tr1 is turned off.
9, Tr20 is turned on. Then, the reference voltage detector 13b
Is activated, and a constant voltage is generated at node N6.

At this time, if the reference voltage Vg is at a higher level than the node N6, the transistor Tr17 is turned on, so that the node N4 is maintained at the H level,
5 is maintained at the L level. Therefore, the transistor Tr3
Keeps off.

When the reference voltage Vg becomes lower than the node N6, the transistor Tr17 is turned off, the transistor Tr18 is turned on, the node N4 goes low, the node N5 goes high, and the transistor T17 goes high.
r3 is turned on. Then, based on the ON operation of the transistor Tr3, the internal voltage Vdd decreases to the power supply Vss level.

In the internal voltage generating circuit configured as described above, the same operation and effect as those of the first embodiment can be obtained, and the following operation and effect can be obtained. (1) The reference voltage detector 13b is inactivated during normal operation, so that unnecessary current consumption during normal operation can be reduced. (Third Embodiment) FIG. 6 shows a voltage generating circuit according to a third embodiment of the present invention. In the control unit 12c of this embodiment, the node N6 is connected to the power supply Vcc via the resistor R4 and to the power supply Vss via the diode-connected N-channel MOS transistor Tr21 in the reference voltage detection unit 13c. I have. Other Configuration of Reference Voltage Detector 13c and Clamp Signal Generator 1
4c is the same as in the second embodiment.

Accordingly, the node N6 is always set to a level higher than the power supply Vss by the threshold value Vthn of the transistor Tr21 based on the power-on of the power supplies Vcc and Vss. With such a configuration, it is possible to obtain the same functions and effects as those of the second embodiment. Note that, in order to set the potential of the node N6, the resistor R4 and the transistor Tr21 are switched from the power supply Vcc.
, A current consumption flowing to the power supply Vss is generated, so that the current consumption is larger than that in the second embodiment. (Fourth Embodiment) FIG. 7 shows a fourth embodiment of the voltage generation circuit embodying the present invention. The step-down circuit 11b of this embodiment has the same configuration as that of the step-down circuit shown in FIG. 11, and the same reference numerals are given and the detailed description is omitted.

Reference voltage detector 1 constituting controller 12d
In 3d, the sources of the P-channel MOS transistors Tr22 and Tr23 are connected to the power supply Vcc, and the drain is connected to the drain of the N-channel MOS transistor Tr24 via the resistor R5. The source of the transistor Tr24 is a power supply Vs
Connected to s.

The resistance value of the resistor R5 is determined by the transistor T
Set to a sufficiently large value for the on-resistance of r24. The power down signal pd is input to the gates of the transistors Tr23 and Tr24, and the reference voltage Vg is input to the gate of the transistor Tr22.

Therefore, in the reference voltage detecting section 13d, when the power down signal pd is at L level, the transistor T
Since the transistor Tr23 is turned on while the transistor Tr24 is turned off, the transistor Tr2 is turned on regardless of the reference voltage Vg.
2. The node N7, which is the drain potential of Tr23, goes high.

Even if the power down signal pd goes high, if the potential difference between the reference voltage Vg and the power supply Vcc is greater than or equal to the threshold value Vthp of the transistor Tr22, the transistor Tr24 is turned on and the transistor Tr22 is turned on. Since it is turned on, the node N7 becomes H level.

When the power down signal pd goes high and the potential difference between the reference voltage Vg and the power supply Vcc falls below the threshold value Vthp of the transistor Tr22, the transistor Tr24 is turned on and the transistors Tr22 and Tr22 are turned off.
Since r23 is turned off, the node N7 goes low.

The clamp signal generator 14d has a configuration in which the input stage inverter circuit is omitted from the clamp signal generator 14a of the first embodiment, and operates using the node N7 and the power down signal pd as input signals. Then, the node N8 which is an output signal is output to the gate of the transistor Tr6 of the step-down circuit 11b.

Next, the operation of the voltage generating circuit configured as described above will be described with reference to FIG. When the L-level power-down signal pd is input in the normal mode, the transistor Tr5 in the step-down circuit 11b is turned off, the node N8 of the clamp signal generation unit 14d is maintained at the L level, and the transistor Tr6 is turned off. The internal voltage Vdd is output to the internal circuit 1 based on the input of Vg.

When the mode shifts from the normal mode to the power down mode, the input of the reference voltage Vg is stopped, and when the power down signal pd goes to the H level, the transistor Tr5 is turned on by the step-down circuit 11b, and the input to the gate of the transistor Tr4 is made. The reference voltage Vg gradually increases, and the potential difference between the reference voltage Vg and the power supply Vcc becomes the threshold Vthp of the transistor Tr4.
When the following occurs, the transistor Tr4 is turned off. Also,
In the reference voltage detector 13d, the transistor Tr24 is turned on, and the transistor Tr23 is turned off.

At this time, if the reference voltage Vg is lower than the power supply Vcc by at least the threshold value Vthp of the transistor Tr22, the transistor Tr22 is turned on.
Node N7 is maintained at H level. Therefore, node N
8 is maintained at the L level, and the transistor Tr6 continues to be turned off.

Next, when the potential difference between the reference voltage Vg and the power supply Vcc becomes equal to or less than the threshold value Vthp of the transistor Tr22,
The transistor Tr22 is turned off, the node N7 goes low, the node N8 goes high, and the transistor Tr6 is turned on. Then, based on the ON operation of the transistor Tr6, the internal voltage Vdd decreases to the power supply Vss level.

In the internal voltage generating circuit configured as described above, the same functions and effects as those of the first embodiment can be obtained. (Fifth Embodiment) FIG. 9 shows a fifth embodiment. In this embodiment, the power down signal pd is input to the control unit 12 and the delay circuit 17.

The control section 12 is one of the control sections 12a to 12d of the first to fourth embodiments, and its output signal is input to the AND circuit 18. The delay circuit 17
The power down signal pd is output after being delayed for a predetermined time, and the output signal is input to the AND circuit 18.

The output signal of the AND circuit 18 is input to the gate of the internal voltage clamping transistor of the step-down circuit 11a or 11b. With such a configuration, when a transition is made from the normal operation to the power down mode, after the output signal of the control unit 12 and the output signal of the delay circuit 17 both become H level after the power down signal pd becomes H level, the internal voltage The clamp transistor can be turned on.

Therefore, by appropriately setting the delay time of the delay circuit 17, it is possible to reliably prevent the occurrence of a through current in the step-down circuits 11a and 11b. Further, the internal voltage clamping transistor can be turned on by an output signal of only the delay circuit 17.

The above embodiment can be modified as follows. -In the second embodiment, the transistor Tr20 may be omitted. In the power down mode, the internal voltage Vdd may be set to an intermediate level between a predetermined internal voltage level and the low potential side power supply Vss. In this case, when shifting from the power down mode to the normal mode, the internal voltage Vdd can be quickly returned to a predetermined level. In the first to third embodiments, in the power down mode, the reference voltage Vg may be set to an intermediate level between a predetermined reference voltage level and the low potential side power supply Vss. In this case, when shifting from the power down mode to the normal mode,
The reference voltage Vg can be promptly returned to a predetermined level. In the fourth embodiment, in the power down mode, the reference voltage Vg may be set to an intermediate level between the predetermined reference voltage level and the high potential side power supply Vcc. In this case,
When shifting from the power down mode to the normal mode, the reference voltage Vg can be quickly returned to a predetermined level.

[0075]

As described above in detail, the present invention can provide a voltage generating circuit capable of preventing generation of a through current when shifting to the power down mode.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a waveform chart showing an operation of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment.

FIG. 5 is a waveform chart showing the operation of the second embodiment.

FIG. 6 is a circuit diagram showing a third embodiment.

FIG. 7 is a circuit diagram showing a fourth embodiment.

FIG. 8 is a waveform chart showing the operation of the fourth embodiment.

FIG. 9 is a block circuit diagram showing a fifth embodiment.

FIG. 10 is a circuit diagram showing a conventional example.

FIG. 11 is a circuit diagram showing a conventional example.

FIG. 12 is a waveform chart showing the operation of the conventional example.

FIG. 13 is a waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 11 voltage generation unit (step-down circuit) 12 control unit 21 reference voltage clamp circuit 22 internal voltage clamp circuit Vg reference voltage Vdd internal voltage pd power down signal Vss first potential, second potential Vd detection signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/00 H01L 27/04 F (72) Inventor Shuichi Saito 2-844-2 Kozoji-cho, Kasugai-shi, Aichi F-term in Fujitsu VSI Co., Ltd. (reference)

Claims (10)

[Claims] A voltage generation unit configured to generate and output an internal voltage based on an input of a reference voltage; and
A reference voltage clamp circuit that clamps to a first potential that inactivates the voltage generator, an internal voltage clamp circuit that clamps the internal voltage to a second potential, and, based on the input of the power-down signal, A control unit for operating the internal voltage clamp circuit after the voltage generation unit is inactivated. 2. A voltage generating unit for outputting an internal voltage obtained by stepping down an external power supply voltage based on an input of a reference voltage, and the reference voltage based on an input of a power down signal.
A reference voltage clamp circuit that clamps to a first potential that inactivates the voltage generator, an internal voltage clamp circuit that clamps the internal voltage to a second potential, and, based on the input of the power-down signal, And a control unit that operates the internal voltage clamp circuit after the output of the internal voltage from the voltage generation unit is stopped. 3. The control section, comprising: a reference voltage detection section for outputting a detection signal when the reference voltage reaches a predetermined clamp level; and a control section for operating an internal voltage clamp circuit based on the detection signal. 3. The voltage generation circuit according to claim 1, further comprising a clamp signal generation unit that outputs a clamp signal. 4. The power supply according to claim 1, wherein the voltage generator includes a MOS transistor that outputs a step-down voltage based on the input of the reference voltage, and the reference voltage detector detects the reference voltage based on the input of the power-down signal. 4. The voltage generation circuit according to claim 3, wherein the detection signal is output when a potential difference between the first potential and the first potential is equal to or less than a threshold value of the MOS transistor. 5. The method according to claim 1, wherein the first and second potentials are low-potential-side external power supplies, and the voltage generator is configured by an N-channel MOS transistor that outputs a step-down voltage based on the input of the reference voltage. 5. The reference voltage detector according to claim 4, wherein the reference voltage detector outputs the detection signal when a potential difference between the reference voltage and a low-potential-side external power supply becomes equal to or less than a threshold value of the N-channel MOS transistor. Voltage generation circuit. 6. The first potential is a high-potential-side external power supply, the second potential is a low-potential-side external power supply, and the voltage generator outputs a step-down voltage based on the input of the reference voltage. The reference voltage detector outputs the detection signal when a potential difference between the reference voltage and a high-potential-side external power supply becomes equal to or smaller than a threshold value of the P-channel MOS transistor. 5. The voltage generation circuit according to claim 4, wherein: 7. The voltage generation circuit according to claim 2, wherein the control unit is configured by a delay circuit that delays the power-down signal and outputs the power-down signal as a clamp signal for operating the internal voltage clamp circuit. . 8. The control unit includes: the delay circuit; the reference voltage detection unit and a clamp signal generation unit; and a logic circuit that outputs a logical sum of output signals of the delay circuit and the clamp signal generation unit. The voltage generation circuit according to claim 3, wherein: 9. An internal circuit that operates using an internal voltage output from the voltage generation circuit according to claim 1 as a power supply and that is inactivated based on the supply of the second potential. A semiconductor device. 10. Based on an input of a power down signal,
The reference voltage input to the voltage generator is clamped to inactivate the voltage generator, the voltage level of the reference voltage is detected, and after the reference voltage reaches a predetermined clamp level, A method for controlling a voltage generation circuit, comprising clamping an output internal voltage to a level that inactivates an internal circuit.