JPH07153802A - Semiconductor device - Google Patents

Abstract

PURPOSE:To visually monitor the amount of isotropic etching which is used at the time of opening contact holes, through holes, etc., by using a microscope. CONSTITUTION:In a monitor pattern 1 for isotropic etching, 4mum through holes are formed at constant intervals of 67mum in the length direction, and at 1mum step intervals from 1mum to 5mum in the width direction. By using a reticle having the monitor pattern 1 on scribe lines, PR of through holes is performed, and then through holes are etched by using isotropic etching. The check pattern after PR and etching becomes circular. Etching patterns having intervals corresponding with the etching amount of isotropic etching come into contact with points. Since the check pattern is arranged in a matrix type, it is excellent in visual observation property, and the etching amount can be easily visually detected by using a microscope.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a test pattern for visually recognizing the degree of etching, etching dimension accuracy and the like is arranged on the surface of a semiconductor substrate.

[0002]

2. Description of the Related Art In a visual inspection of a photolithography (PR) process in a semiconductor substrate manufacturing process, the dimensional accuracy directly affects the device performance. Therefore, a test pattern is appropriately provided and the dimensional measurement of this pattern is performed.
This test pattern is used in order to control the impurity diffusion based on this measured value and to prevent the increase of leak current and the decrease of current gain in the case of a contact hole.

[0003]

[Patent Document 1] Japanese Patent Application Laid-Open No. 60-132337 showing a pattern used for such conventional measurement.
With reference to the publication, as shown in FIGS. 3 to 6 of the publication, each of them is composed of a large number of rectangular patterns, and one side of a pattern having a specific positional relationship is aligned on a straight line. The technique to make good by lining up is shown. With reference to FIG. 5 showing this state, one side of the pattern 14 at the center of each of the upper, middle and lower steps is described as a straight line. Although it is said that such a state is easily visible, it is completely unknown how accurately such a mask pattern is actually projected on the semiconductor substrate, and therefore, the pattern on the semiconductor substrate is not known. There is a drawback in that the criterion itself is not constant.

Further, since the PR pattern of the through hole is actually circular, it cannot be in a straight line and appears wavy, which makes it difficult to judge by visual inspection with a microscope or the like. Particularly, in the staggered pattern arrangement as shown in FIG. 6 of the publication, not only the visibility is poor, but also the eyes are excessively fatigued and the productivity is not improved.

An object of the present invention is to solve the above problems and to provide a semiconductor device having a pattern shape which has extremely good visibility and can be accurately judged.

[0006]

According to the structure of a semiconductor device of the present invention, a plurality of pattern groups are formed in parallel with each other by arranging a large number of patterns on a straight line while sequentially increasing pitch dimensions by a predetermined value. The test pattern is provided on the semiconductor substrate.

1 is a plan view showing a reticle prepared in a semiconductor device according to a first embodiment of the present invention, and FIG. 2 shows a state in which a PR pattern is formed on a semiconductor substrate using this reticle and etching is performed. FIG.

In FIG. 1, the reticle prepared in this embodiment has a total of 24 square through-hole patterns 1 each having a size of 4.0 μm, four vertically and six horizontally. Each through-hole pattern 1 has a longitudinal direction of 6.0.
The grooves are formed at equal intervals of μm and are formed at a pitch (interval) of 1.0 μm from 1.0 μm on the left side to 5.0 μm on the right side in the horizontal direction. The pattern 1 of these through holes is created in the scribe line region or in the vicinity thereof. That is, a vacant area other than the circuit wiring and pad area is used.

Using this reticle, the size of the reticle is reduced to 1/5 by the lithography method, and the PR pattern of the through hole is formed on the silicon substrate. Referring to FIG. It has been expanded about twice. The square pattern 2 shown by the dotted line is a one-fifth reduction of the reticle pattern shown in FIG. 1. In this case, the through-hole PR pattern actually has a circular shape, and the diameter of this circle is PR to about 1.0 μm
Pattern 3 is formed. This 1.0 μm dimension is in a state in which the patterns 3 on the left side are in contact with each other, and it is easy to confirm. Whether or not such a PR pattern has a desired size is measured by a dedicated length measurement. A device or the like may be used.

After that, the isotropic etching method is used to advance the etching of the through-hole pattern 3, and the progress is visually inspected by a microscope. Alternatively,
Inspection is performed immediately after etching is completed. Here, although not shown, a desired pattern is formed in a circuit portion or the like on the semiconductor wafer, and whether or not good etching is performed is monitored by this pattern.

As the etching progresses, the patterns 3 gradually come in contact with each other from the left side to the right side. However, when the fourth to third patterns 3 from the left side come into contact with each other, the pattern of the best dimension is defined as the certification standard of the best product. Set to 4. If the etching is insufficient, the third pattern from the left is 3
In the case of over-etching, the patterns 3 which are the fifth or more from the left side are in contact with each other.

Since the arrangement of the patterns 4 is the same in all four columns, the line 10 enclosing the rightmost contact point among the contacts between the patterns 4 is ideally a vertical straight line. This envelope 10 was found to be extremely visible through a microscope. Further, the line 11 that envelopes the separated portion is also a portion that is easily visible. It is understood that the array pattern 4 as described above can be easily recognized by a computer without visually recognizing it, and it has a great possibility for automation.

If the line 10 is a broken line,
The diagonal line means that the cause of local excess or deficiency of etching occurred. The semiconductor chip in such a state is immediately discarded as a defective product and is not passed through the subsequent steps as a semiconductor device.

FIG. 3 is a plan view of a reticle used in the second embodiment of the present invention, and FIG. 4 is a plan view showing a state in which a PR pattern is formed and etched using this reticle. Descriptions of parts common to FIG. 2 are omitted.

In FIG. 3, this reticle has a total of 32 square contact hole patterns 1 of 5.0 μm square, four in the horizontal direction and eight in the vertical direction. Each pattern 1 has 1.0 μm to 7.0 μm in the vertical direction and 1.0 μm to 7.0 μm in the vertical direction at equal intervals.
They are arranged at intervals of μm step difference. These reticle patterns 1 are reduced to one-fifth by a lithography method to form a contact hole PR pattern in a scribe line region or the like on a silicon substrate, and as shown in FIG. The 1/5 reduction pattern 2 is a square, but the PR pattern 3 is a circle, and the diameter of this circle is formed to be about 1.2 μm. At this time, PR pattern 3 of the contact hole
Whether or not the pattern has a desired size can be measured with a length measuring device, but it can be immediately recognized because the patterns 3 on the uppermost stage and the next stage are in contact with each other on the circumference.

After that, etching is performed, and the contact between the patterns 3 is visually checked with a microscope. If the line 10 enveloping the contact point at the bottom is a straight line and the five patterns 4 are in contact with and overlap with each other, an ideal state is achieved. At this time, the line 11 enveloping between the separated patterns 4
You may visually recognize based on.

Although the first and second embodiments have been described above, these embodiments may be used together on a single semiconductor substrate.
In this case, the presence or absence of planar anisotropy can be known. The pitch is not limited to 1.0 μm, and may be 0.5 μm or 1.5 μm. Further, if it is desired to visually recognize a finer degree of etching progress, many patterns may be arranged vertically and horizontally. Any etching liquid, film to be etched, or the like used in this embodiment can be applied.

[0017]

As described above, according to the present invention, since the test patterns for monitoring the etching amount of the through holes, the contact holes, etc. are arranged in rows or columns, there is an effect that it is very easy to see with a microscope.

[Brief description of drawings]

FIG. 1 is a plan view of a reticle pattern used in a semiconductor device according to a first embodiment of the present invention.

2 is a plan view showing a state in which a PR pattern is formed on a semiconductor substrate using the reticle pattern of FIG. 1 and etched.

FIG. 3 is a plan view of a reticle pattern used in the second embodiment of the present invention.

FIG. 4 is a plan view showing a state in which a PR pattern is formed on a semiconductor substrate using the reticle pattern of FIG. 3 and etched.

FIG. 5 is a plan view showing a conventional mask pattern.

[Explanation of symbols]

 1,14 Through-hole reticle pattern 2 Reticle pattern reduced to one-third 3 Through-hole PR pattern 4 Pattern after isotropic etching 10, 11 Envelope line

Claims (2)

[Claims] 1. A semiconductor substrate is provided with a test pattern in which a plurality of pattern groups, each of which is formed by arranging a large number of patterns on a straight line while sequentially increasing a pitch dimension by a predetermined value, are formed in parallel with each other. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the pattern has a circular shape.