JPH07153669A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the quality of an epitaxial growth layer in the manufacture of a semiconductor device. CONSTITUTION:In the manufacturing method of a semiconductor device, a polysilicon film 2 for an alignment mark is formed in a region used as an alignment mark on the surface of a P-type silicon substrate 1, and an N-type buried layer 6 is then formed. Then, an epitaxial growth layer 7 is formed, and, at the same time, a polysilicon growth layer 2a is formed on the surface of the polysilicon film 2 for the alignment mark. Then, a P-type isolation diffused layer 8 is formed. At this time, as a photo-lithographic process for formation of the P-type isolation diffused layer 8, the polysilicon growth layer 2a is utilized as the alignment mark. Thereby, it is possible to prevent a drop in the film quality of the epitaxial growth layer 7 and to prevent the deformation of a pattern, and the semiconductor device which is made fine and which is integrated highly is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Generally, a plurality of photolithography steps are required in a manufacturing process of a semiconductor device, and it is required to set mutual positions with high accuracy between these plurality of steps. It When a semiconductor integrated circuit is formed on a semiconductor substrate, a plurality of photolithography processes are superposed on each other based on a reference alignment mark (called a parent mark) in order to set positions in the mutual processes. Be seen. The formation of the parent mark is a very important task because the precision of the position of the parent mark determines the overlay precision in the subsequent photolithography process.

As this setting method, for example, when a bipolar transistor is formed on a semiconductor substrate,
As shown in FIG. 2A, an insulating film 5b having a required opening window is formed on the P-type silicon substrate 1, and the insulating film 5b is formed.
Is masked and N-type impurities are introduced by an ion implantation method or a thermal diffusion method. Next, the P-type silicon substrate 1 is heat-treated at a high temperature to push in the impurities to be electrically activated and to form the N-type buried layer 6 having a desired junction depth and layer resistance. Next, as shown in FIG. 2B, the insulating film 5b on the entire surface of the P-type silicon substrate 1 is formed.
Is removed, and the N-type silicon layer 7a which becomes the collector region of the bipolar transistor is grown by the epitaxial growth method. Then, a P-type isolation diffusion layer 8 which becomes an inter-element isolation diffusion layer reaching the P-type silicon substrate 1 is formed. The P-type isolation diffusion layer 8 forms a silicon oxide film 5c by oxidizing the surface of the N-type silicon layer 7a.
Using the photoresist as a mask, the silicon oxide film 5 is formed.
After selectively etching c and removing the photoresist, the silicon oxide film 5c is used as a mask to introduce boron into the N-type silicon layer 7a by a thermal diffusion method and push it in to form. When patterning the photoresist, the N-type buried layer 6 is used.
After confirming the planar shape of, the mask is aligned by using this as an alignment mark.

However, in the above method,
In forming the P-type isolation diffusion layer 8, the N-type buried layer 6 is used as an alignment mark. The N-type buried layer 6 is a single crystal N-type silicon layer 7a formed thereon. At the time of growing, the pattern formed on the surface is not perpendicular to the growth direction but is inclined, so that the growth rate is different, which causes pattern deformation called pattern shift distortion. For this,
As shown in FIG. 2C, the planar shape of the N-type buried layer 6 is deformed, and it becomes difficult to align the mask by the P-type separation diffusion layer 8 with high accuracy. That is, when the P-type separation diffusion layer 8 is formed using the pattern-aligned alignment mark as a reference, the P-type separation diffusion layer 8 is displaced from a predetermined position as shown in FIG. In such a situation, the junction breakdown voltage is deteriorated and the element isolation becomes impossible, resulting in a defect in the element characteristics.

Conventionally, as a method for preventing the deformation of the alignment mark and improving the accuracy, for example, Japanese Patent Laid-Open Publication No.
A method of manufacturing a semiconductor device is proposed in Japanese Patent Publication No. 8-4965. In this proposal, after the step of forming the alignment mark, an insulator is selectively formed on the area where the alignment mark is formed, and then the step of growing the N-type silicon layer 7a is performed to perform the alignment. The polycrystal growth layer is grown only in the mark portion, and the pattern deformation is prevented by the alignment mark made of the polycrystal growth layer which does not depend on the crystal growth direction. That is, as shown in FIG. 3, the alignment mark silicon oxide film 5d is formed again on the surface of the N-type buried layer 6, and a photoresist is formed on the surface of the alignment mark silicon oxide film 5d. Form. Next, the alignment mark silicon oxide film 5d on the surface of the P-type silicon substrate 1 is removed by etching, and the photoresist formed on the alignment mark silicon oxide film 5d is removed. Then, the N-type silicon layer 7a is formed on the surface of the P-type silicon substrate 1, and the polysilicon growth layer 2a is formed on the alignment mark silicon oxide film 5d. In this case, a silicon nitride film for the alignment mark may be formed on the surface of the N-type buried layer 6 for the alignment mark, instead of the silicon oxide film 5d for the alignment mark.

[0006]

In the conventional method for manufacturing a semiconductor device described above, in the formation of the epitaxial growth layer by the vapor phase growth method, the reaction gas reacts with the silicon oxide film or the silicon nitride film of the alignment mark,
Alternatively, sufficient measures have not been taken against deterioration of crystallinity of the epitaxial growth layer due to decomposition of the silicon oxide film or the silicon nitride film due to high temperature.

That is, the silicon oxide film in the epitaxial growth process is decomposed by hydrogen gas, hydrogen chloride gas, or hydrochloric acid gas generated by the reduction reaction of silicon tetrachloride, which is a source gas. For example, the reaction represented by the following formula occurs.

H ₂ + SiO ₂ → SiO + H ₂ O ………………………… (1) 4HCL + SiO ₂ → SiCL ₄ + 2H ₂ O ………… (2) SiCL ₄ + 2H ₂ → Si + 4HCL ………… (3) The oxidizing agent of SiO or H ₂ O in the above formula becomes a nucleus for forming silicon particles in the gas phase after diffusing into the reaction gas phase. The formation of such silicon particles causes the silicon particles to be deposited on the semiconductor substrate by diffusion from the gas phase, which hinders the surface migration of silicon atoms, disturbs the epitaxial growth mechanism, and improves the quality of the growth layer. Greatly reduce. The deterioration of the film quality is due to the occurrence of defects such as dislocations, stacking faults or hillocks, which limits the crystal integrity of the epitaxial growth layer. The degree of this limitation is particularly remarkable in the vicinity where the oxide film is located. When hydrogen gas is used as a carrier gas and the source gas is silicon tetrachloride, the permissible level of oxidizers such as SiO and H ₂ O is 5 to 10 ppm. Further, in the case of monosilane, the permissible level of the oxidizing agent is 2 ppm or less, which makes it susceptible to the influence of the oxidizing agent.

As described above, the use of the silicon oxide film for the alignment mark causes the deterioration of the film quality of the epitaxial growth layer and causes the electrical short circuit due to the formation and transition of the generation / recombination level in the epitaxial layer. Therefore, there is a drawback in that the device characteristics of the semiconductor device cannot be sufficiently satisfied after manufacturing. Further, in order to avoid such an obstacle, it is necessary to arrange the alignment mark and the element at a sufficiently large distance, which results in a large element area, which hinders high integration. There is.

[0010]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an alignment mark on the surface of a semiconductor substrate, a step of performing epitaxial growth by vapor phase growth, and an alignment for the alignment mark. In the method of manufacturing a semiconductor device having a post-process for carrying out a predetermined process, a step of forming a polycrystalline growth layer on a surface portion of a region used as an alignment mark on the surface of a semiconductor substrate, Forming a vapor phase growth layer on the surface of the semiconductor substrate to form only a region used as the alignment mark as a polycrystalline growth layer.

A polysilicon growth layer may be used as the polycrystalline growth layer.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

1 (a), (b), (c), (d),
(E) And (f) is a figure which shows the cross section of the semiconductor device which shows one Example of this invention in order of process.

First, as shown in FIG. 1A, a P-type silicon substrate 1 having a specific resistance of about 10 Ωcm is formed on, for example, L
Using a P-CVD apparatus, the alignment mark polysilicon film 2 is deposited to a thickness of 3000 angstroms by thermal decomposition of monosilane in a reaction tube having a temperature of 600 ° C. The thickness of the alignment mark polysilicon film 2 needs to be set to have a sufficient alignment sensitivity in the photolithography process. Next, in a reaction tube having a temperature of, for example, 780 ° C., a silicon nitride film 3 is deposited to a thickness of about 2000 angstrom by a reduction reaction of ammonia and dichlorosilane. Next, a photoresist 4 is formed into a desired pattern to form a photoresist mask, and this is used as a mask to immerse the photoresist mask in a phosphoric acid solution to form the silicon nitride film 3
Is selectively etched.

Next, as shown in FIG. 1B, after removing the photoresist mask of the photoresist 4, a heat treatment is performed in an oxidizing atmosphere at a temperature of 1140 ° C. in an oxidizing furnace. , A silicon oxide film 5 for forming an N-type buried layer having a thickness of 8000 angstrom is formed. At this time, as the thickness of the N-type buried layer forming silicon oxide film 5, the alignment mark polysilicon film 2 other than the portion covered by the silicon nitride film 3 is formed.
However, a thickness that can be completely oxidized is required. For example, in this embodiment, since the thickness of the alignment mark polysilicon film 2 is 3000 angstroms, in order to satisfy the film thickness of about 45% of the silicon oxide film thickness, silicon of at least about 6700 angstroms or more is required. An oxide film thickness is required.

Then, as shown in FIG. 1C, a photoresist is patterned using the silicon nitride film 3 as an alignment pattern, and the photoresist is used as a mask.
The region of the N-type buried layer forming silicon oxide film 5 is selectively etched. Then, after removing the photoresist, antimony (Sb) or arsenic (As) is formed in the opened region of the N-type buried formation silicon oxide film 5.
Is thermally diffused at a temperature of 1200 ° C. to form the N-type buried layer 6. The sheet resistance of the N-type buried layer 6 is about 20Ω / □. As a method of forming the N-type buried layer 6, a combination of an ion implantation method other than the above and heat treatment may be used.

Next, as shown in FIG. 1D, for example, after removing the silicon oxide film on the surface of the silicon nitride film 3 with an aqueous solution of hydrofluoric acid, the silicon nitride film 3 is immersed in a phosphoric acid solution. To remove. After that, the P-type silicon substrate 1 is again immersed in the hydrofluoric acid aqueous solution to remove the N-type buried layer forming silicon oxide 5 over the entire surface. As a result, after the completion of this step, the surface of the P-type silicon substrate 1 is exposed and the polysilicon layer 2 is left in the alignment mark portion.

Then, as shown in FIG. 1 (e), for example, a gaseous silane compound such as silicon tetrachloride and monosilane and a phosphorus compound are subjected to hydrogen reduction or thermal decomposition at a high temperature of 900 to 1200 ° C. By reacting, an N-type epitaxial growth layer 7 having a thickness of 5 μm and a specific resistance of 0.5 Ωcm is formed on the entire surface of the P-type silicon substrate 1, and the polysilicon growth film 2 a is formed on the alignment mark polysilicon film 2. To form. Since the polysilicon growth layer 2a does not depend on the crystal growth direction during epitaxial growth, it is faithfully reproduced as an alignment mark.

Next, as shown in FIG. 1F, for example, heat treatment is performed in an oxidizing atmosphere at a temperature of 1140 ° C. to form a P-type isolation diffusion layer-forming silicon oxide film having a thickness of 5000 angstroms. 5a is formed. After that, a photoresist is formed into a desired pattern and immersed in an aqueous solution of hydrofluoric acid to etch the silicon oxide film 5a for forming the P-type isolation diffusion layer. Then, the photoresist is removed. In the photolithography at this time, the polysilicon growth layer 2a is used as an alignment mark. After that, using the silicon oxide film 5a for forming the P-type isolation diffusion layer as a mask, a boron compound gas such as boron trichloride is reacted at a temperature of 1100 ° C., and the P-type epitaxial growth layer 7 is exposed from the surface thereof. Boron is diffused in the silicon substrate 1. Further, the diffused boron is pushed to a desired depth at a temperature of 1200 ° C. to form a P-type isolation diffusion layer 8 which is an element isolation region. The sheet resistance of the P-type separation diffusion layer 8 thus formed is about 15Ω / □.

As described above, according to the manufacturing method of the present invention, the presence of a silicon oxide film or the like on the surface of the semiconductor substrate can be eliminated in the epitaxial growth process, so that the generation of nuclei due to the formation of silicon particles is prevented, This makes it possible to form a crystal with high integrity and improve the alignment accuracy.
There is an effect that miniaturization and high integration of elements in a semiconductor device can be realized.

[0021]

As described above, according to the present invention, in order to prevent the deterioration of the film quality in the epitaxial growth layer, which has been a problem in the past, the alignment mark is formed by the polysilicon layer and the single crystal silicon is formed on the mark. By eliminating the formation of the pattern, it is possible to prevent the occurrence of pattern distortion in the alignment mark, and it is possible to improve the alignment accuracy, which enables miniaturization and high integration of the elements of the semiconductor device. It has the effect that it can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view of a semiconductor device showing a conventional example in the order of manufacturing steps and a cross-sectional view showing a defect.

FIG. 3 is a cross-sectional view of a semiconductor device showing a manufacturing process of another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Polysilicon film for alignment marks 2a Polysilicon growth layer 3 Silicon nitride film 4 Photoresist 5 N-type buried layer forming silicon oxide film 5a P-type isolation diffusion layer forming silicon oxide film 5b Insulating film 5c Silicon oxide film 5d Silicon oxide film for alignment mark 6 N-type buried layer 7 Epitaxial growth layer 7a N-type silicon layer 8 P-type isolation diffusion layer

Claims (2)

[Claims] 1. A step of forming an alignment mark on the surface of a semiconductor substrate, a step of performing epitaxial growth by vapor phase growth, and a post-step of performing alignment with respect to the alignment mark and performing a predetermined process. In a method of manufacturing a semiconductor device, a step of forming a polycrystalline growth layer on a surface portion of a region used as an alignment mark on the surface of a semiconductor substrate, and forming a vapor phase growth layer on the surface of the semiconductor substrate. Accordingly, a step of forming only a region used as the alignment mark as a polycrystalline growth layer, and a method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a polysilicon growth layer is used as the polycrystalline growth layer.