JPH0714806A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0714806A
JPH0714806A JP14246993A JP14246993A JPH0714806A JP H0714806 A JPH0714806 A JP H0714806A JP 14246993 A JP14246993 A JP 14246993A JP 14246993 A JP14246993 A JP 14246993A JP H0714806 A JPH0714806 A JP H0714806A
Authority
JP
Japan
Prior art keywords
scribe line
film
integrated circuit
semiconductor integrated
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP14246993A
Other languages
Japanese (ja)
Inventor
Nagayoshi Toyoda
修至 豊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamaguchi Ltd
Original Assignee
NEC Yamaguchi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamaguchi Ltd filed Critical NEC Yamaguchi Ltd
Priority to JP14246993A priority Critical patent/JPH0714806A/en
Publication of JPH0714806A publication Critical patent/JPH0714806A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To avoid either the uneven film thickness at the parts near scribe line or the cracking reaching semiconductor elements in the dicing step by a method wherein a part of the scribe line, the films formed in the manufacturing step are entirely removed while the residual parts are made flush with the inactive regions in the semiconductor element. CONSTITUTION:In order to manufacture a semiconductor integrated circuit, within a scribe line region 1 corresponding to the boundary of respective element formation regions 2, the regions 4 wherein the films to be formed in the manufacturing step i.e., a LOCOS oxide film 6, a layer insulating film 7, an interwiring layer 8 and a passivation film 9, etc., are entirely etched away in the width of e.g. about 50mum, and are formed in parallel with the scribe line at the interval of e.g. about 50mum in two rows. Through these procedures, either the running phenomenon of the liquid film used in the manufacturing step into the scribe line or the cracking in the element formation regions 2 in the dicing step can be avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層配線構造を有する
半導体集積回路装置に関し、特にフォトリソグラフィ技
術のレジスト塗布工程や配線層間膜の平坦化等に用いら
れるSOG膜塗布工程での均一な塗布性を得る技術に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a multi-layer wiring structure, and more particularly, to uniform coating in a resist coating step of photolithography technique and an SOG film coating step used for flattening a wiring interlayer film. Technology to gain sex.

【0002】[0002]

【従来の技術】従来、半導体集積回路装置に於けるスク
ライブ線は、図3に示す様に、ダイシング時に生じる半
導体チップ内へのクラックを防止する為に、シリコン基
板が露出する様、製造工程で形成された膜が均一にエッ
チング除去されているか、もしくは、特定の膜のみを残
して、均一にエッチング除去され、半導体チップ部分よ
り、段差が低くなる様に形成されている。また、この従
来法では前述した段差により、レジストや液状絶縁膜の
形成時、すなわち塗布により膜を形成する工程で、液が
スクライブ線に沿って流れる為、半導体チップの周辺部
で膜が極端に薄くなる等、膜厚の不均一性を生じる為、
対策としてスクライブ線を設けない方法もある。
2. Description of the Related Art Conventionally, as shown in FIG. 3, a scribe line in a semiconductor integrated circuit device is manufactured in a manufacturing process such that a silicon substrate is exposed in order to prevent a crack in a semiconductor chip which occurs during dicing. The formed film is uniformly removed by etching, or it is formed by removing the specific film only and etching it uniformly so that the step difference is lower than that of the semiconductor chip portion. Further, in this conventional method, the liquid flows along the scribe line during the formation of the resist or the liquid insulating film, that is, in the step of forming the film by coating due to the above-mentioned step, so that the film is extremely formed in the peripheral portion of the semiconductor chip. Since it causes non-uniformity of film thickness such as thinning,
As a countermeasure, there is also a method of not providing a scribe line.

【0003】[0003]

【発明が解決しようとする課題】前述した従来法による
スクライブ線構造では、従来の技術の項で述べた様に、
回転塗布を用いた方法で膜を形成する工程で膜厚の不均
一性を生じてしまう。
In the above-mentioned conventional scribe line structure, as described in the section of the prior art,
Non-uniformity of the film thickness occurs in the process of forming the film by the method using spin coating.

【0004】また、スクライブ線を設けない方法では、
半導体チップ(素子形成領域)へのダイシング時のクラ
ックの危険性がある。
Further, in the method without the scribe line,
There is a risk of cracks during dicing on the semiconductor chip (element formation region).

【0005】本発明の目的は、半導体集積回路装置の製
造工程で用いられる液状の膜に於いて、スクライブ線近
くで生じる膜厚ムラを防ぎ均一な膜厚を得ることがで
き、かつダイシング時にクラックが半導体素子へ達する
ことを防ぐことができる半導体集積回路を提供すること
にある。
An object of the present invention is to prevent a film thickness unevenness that occurs near the scribe line in a liquid film used in a manufacturing process of a semiconductor integrated circuit device and to obtain a uniform film thickness, and to prevent cracks during dicing. An object of the present invention is to provide a semiconductor integrated circuit capable of preventing a semiconductor from reaching a semiconductor element.

【0006】[0006]

【課題を解決するための手段】本発明の半導体集積回路
装置は、スクライブ線を選択的に形成し、その構造とし
て、製造工程で形成される膜が全て除去される領域が、
スクライブ線上に10μm以下の一定幅で、スクライブ
線と平行にかつダイシング幅以上の間隔をもって2列存
在しているか、もしくは、製造工程で形成される膜が全
て除去される領域が、スクライブ線と同一幅で形成さ
れ、かつ、素子形成ペレットの一辺内で製造工程で形成
される膜により2つ以上の領域に分離されている。
In the semiconductor integrated circuit device of the present invention, a scribe line is selectively formed, and as a structure of the scribe line, a region where all the films formed in the manufacturing process are removed is
There are two rows on the scribe line with a constant width of 10 μm or less, parallel to the scribe line and at an interval of the dicing width or more, or the region where the film formed in the manufacturing process is completely removed is the same as the scribe line. The film is formed to have a width and is separated into two or more regions by a film formed in one side of the element formation pellet by a manufacturing process.

【0007】[0007]

【実施例】次に本発明について、図面を参照して説明す
る。図1は本発明の一実施例を示す平面図及びそのA−
A線部分の断面図である。既存の方法により半導体集積
回路を製造する際に、各素子形成領域(半導体ペレッ
ト)2の境界に当るスクライブ線領域1に於いて、製造
工程で形成される膜、すなわち、LOCOS酸化膜6,
層間絶縁膜7,配線層間絶縁膜8及びパッシベーション
膜9等が全てエッチング除去される領域4を数μm例え
ば5μm程度の幅で、スクライブ線と平行に、かつダイ
シング幅以上の例えば50μm程度の間隔をもって2列
形成する。
The present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an embodiment of the present invention and its A-
It is sectional drawing of the A line part. When a semiconductor integrated circuit is manufactured by the existing method, a film formed in the manufacturing process, that is, the LOCOS oxide film 6, in the scribe line region 1 that corresponds to the boundary of each element formation region (semiconductor pellet) 2.
The region 4 where the interlayer insulating film 7, the wiring interlayer insulating film 8 and the passivation film 9 are all removed by etching has a width of several μm, for example, about 5 μm, and is parallel to the scribe line and at a distance of, for example, about 50 μm which is equal to or larger than the dicing width. Form two rows.

【0008】この方法により形成されたスクライブ線に
於いては、製造工程で用いられる液状の膜、例えばレジ
スト膜やSOG膜が塗布時に素子形成領域の端から、ス
クライブ線に流れる等の現象が起きず、均一な膜厚が得
られる。また、膜が全層エッチングされる領域4をスク
ライブ線と平行に設けている為、ダイシング時に、素子
形成領域(半導体ペレット)2へクラックが発生するこ
ともない。
In the scribe line formed by this method, there occurs a phenomenon that a liquid film used in the manufacturing process, for example, a resist film or an SOG film, flows from the end of the element forming region to the scribe line during coating. In addition, a uniform film thickness can be obtained. In addition, since the region 4 where the film is entirely etched is provided in parallel with the scribe line, no crack is generated in the element forming region (semiconductor pellet) 2 during dicing.

【0009】図2は、本発明の他の実施例を示す平面図
である。第1の実施例と同様、既存の方法により半導体
集積回路を製造する際に、スクライブ線領域1に於い
て、製造工程で形成される膜が全てエッチングされる領
域4をスクライブ線幅と同一幅、例えば150μm幅
で、分離させて形成する。この際、分離領域である製造
工程で形成される膜が全て残される領域3の幅は一定で
なくてよい。
FIG. 2 is a plan view showing another embodiment of the present invention. Similar to the first embodiment, when a semiconductor integrated circuit is manufactured by the existing method, in the scribe line region 1, the region 4 in which the film formed in the manufacturing process is entirely etched has the same width as the scribe line width. , For example, with a width of 150 μm, they are formed separately. At this time, the width of the region 3, which is the isolation region, in which all of the film formed in the manufacturing process remains is not required to be constant.

【0010】本実施例の場合、前記実施例1に比べ、液
状の膜の流れをより効果的に防ぐことができ、均一な膜
厚が得やすくなる。
In the case of the present embodiment, the flow of the liquid film can be more effectively prevented and the uniform film thickness can be easily obtained, as compared with the first embodiment.

【0011】また、スクライブ線領域は幅のせまい分離
領域を除いて製造工程で形成される膜が全てエッチング
除去されているので、ダイシング時にクラックが半導体
素子に達することがない。
Further, in the scribe line region, since the film formed in the manufacturing process is completely removed by etching except the narrow isolation region, cracks do not reach the semiconductor element during dicing.

【0012】[0012]

【発明の効果】以上説明した様に、本発明ではスクライ
ブ線構造を変えることで製造工程で用いる液状の膜、例
えばレジスト膜やSOG膜、及びポリイミド膜が膜形成
時(塗布時)に素子形成領域の端からスクライブ線に流
れる等の現象が起きず、均一な膜厚が得られる為、スク
ライブ線近くの素子パターンで異常幅を生じたり、膜厚
異常を生じ信頼性上問題になることがなくなる。
As described above, according to the present invention, by changing the scribe line structure, the liquid film used in the manufacturing process, for example, the resist film, the SOG film, and the polyimide film is formed as an element when the film is formed (at the time of coating). Since a phenomenon such as flowing from the edge of the region to the scribe line does not occur and a uniform film thickness can be obtained, an abnormal width may occur in the element pattern near the scribe line, or an abnormal film thickness may occur, resulting in a reliability problem. Disappear.

【0013】また、本発明によるスクライブ線の構造で
は、ダイシング時の半導体チップへのクラックの危険性
もない。
Further, in the structure of the scribe line according to the present invention, there is no risk of cracks in the semiconductor chip during dicing.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の要部の平面図及びそのA−
A線の断面図である。
FIG. 1 is a plan view of an essential part of an embodiment of the present invention and its A-
It is sectional drawing of the A line.

【図2】本発明の他の実施例の要部の平面図である。FIG. 2 is a plan view of an essential part of another embodiment of the present invention.

【図3】従来の半導体集積回路のスクライブ線領域を示
す平面図である。
FIG. 3 is a plan view showing a scribe line region of a conventional semiconductor integrated circuit.

【符号の説明】[Explanation of symbols]

1 スクライブ線領域 2 素子形成領域(半導体ペレット) 3 形成される膜が全て残される領域 4 形成される膜が全てエッチングされる領域 5 シリコン基板 6 酸化膜 7 層間絶縁膜 8 配線層間絶縁膜 9 パッシベーション膜 1 scribe line region 2 element forming region (semiconductor pellet) 3 region where all formed film is left 4 region where all formed film is etched 5 silicon substrate 6 oxide film 7 interlayer insulating film 8 wiring interlayer insulating film 9 passivation film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路装置のスクライブ線構造
に於いて、スクライブ線の一部は、製造工程で形成され
る膜が全て除去され、残りの部分は、半導体素子中の非
活性領域と同一の高さである事を特徴とする半導体集積
回路装置。
1. In a scribe line structure of a semiconductor integrated circuit device, a part of the scribe line is formed by removing the film formed in the manufacturing process, and the remaining part is the same as the inactive region in the semiconductor element. A semiconductor integrated circuit device characterized by being the height of the semiconductor integrated circuit device.
【請求項2】 製造工程で形成される膜が全て除去され
る領域が、スクライブ線上に、10μm以下の一定幅で
スクライブ線と平行に、かつ、一定の間隔をもって2列
存在する事を特徴とする半導体集積回路装置。
2. A region in which all the film formed in the manufacturing process is removed is present in two rows on the scribe line with a constant width of 10 μm or less, parallel to the scribe line, and at regular intervals. Integrated circuit device.
【請求項3】 製造工程で形成される膜が全て除去され
る領域が、スクライブ線と同一幅で形成され、かつ、素
子形成ペレットの一辺内で2つ以上の領域に分離されて
いる事を特徴とする半導体集積回路装置。
3. A region in which all the film formed in the manufacturing process is removed is formed to have the same width as the scribe line and is divided into two or more regions within one side of the element forming pellet. A characteristic semiconductor integrated circuit device.
JP14246993A 1993-06-15 1993-06-15 Semiconductor integrated circuit device Withdrawn JPH0714806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14246993A JPH0714806A (en) 1993-06-15 1993-06-15 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14246993A JPH0714806A (en) 1993-06-15 1993-06-15 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0714806A true JPH0714806A (en) 1995-01-17

Family

ID=15316047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14246993A Withdrawn JPH0714806A (en) 1993-06-15 1993-06-15 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0714806A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0874398A2 (en) * 1997-04-21 1998-10-28 Nec Corporation Semiconductor integrated circuit
EP0899788A2 (en) * 1997-08-29 1999-03-03 Nec Corporation Semiconductor device and method with improved flat surface
GB2365621A (en) * 2000-01-24 2002-02-20 Nec Corp Semiconductor device with protection film
US9508774B2 (en) 2012-11-30 2016-11-29 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0874398A2 (en) * 1997-04-21 1998-10-28 Nec Corporation Semiconductor integrated circuit
EP0874398A3 (en) * 1997-04-21 1999-10-13 Nec Corporation Semiconductor integrated circuit
CN1113394C (en) * 1997-04-21 2003-07-02 日本电气株式会社 Semiconductor integrated circuit
EP0899788A2 (en) * 1997-08-29 1999-03-03 Nec Corporation Semiconductor device and method with improved flat surface
EP0899788A3 (en) * 1997-08-29 2000-09-13 Nec Corporation Semiconductor device and method with improved flat surface
GB2365621A (en) * 2000-01-24 2002-02-20 Nec Corp Semiconductor device with protection film
US6465872B2 (en) 2000-01-24 2002-10-15 Nec Corporation Semiconductor device
GB2365621B (en) * 2000-01-24 2004-07-14 Nec Corp Semiconductor device
US9508774B2 (en) 2012-11-30 2016-11-29 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US10411056B2 (en) 2012-11-30 2019-09-10 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same

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Effective date: 20000905