JPH07147349A - Multilayer circuit board and its manufacture - Google Patents

Multilayer circuit board and its manufacture

Info

Publication number
JPH07147349A
JPH07147349A JP5315791A JP31579193A JPH07147349A JP H07147349 A JPH07147349 A JP H07147349A JP 5315791 A JP5315791 A JP 5315791A JP 31579193 A JP31579193 A JP 31579193A JP H07147349 A JPH07147349 A JP H07147349A
Authority
JP
Japan
Prior art keywords
layer
circuit board
multilayer circuit
heat
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5315791A
Other languages
Japanese (ja)
Inventor
Toshio Ogawa
敏夫 小川
Shuji Kato
修治 加藤
Noritaka Kamimura
典孝 神村
Mitsuru Hasegawa
長谷川  満
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5315791A priority Critical patent/JPH07147349A/en
Publication of JPH07147349A publication Critical patent/JPH07147349A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To provide a multilayer circuit board in which a low-resistance conductor interconnection is built, whose thermal resistance is low and which is used for a small and high-density hybrid IC. CONSTITUTION:A multilayer circuit board has a structure wherein a conductor pattern 11 which forms a desired electric circuit is arranged on an insulator 18 and the conductor pattern 11 is connected electrically, by wires 19, to a heat-generating electronic circuit component 17. In the multilayer circuit board, a glass is used as the insulator 18, and a metallized layer 13, for discharging, which is electrically independent or which is connected to a grounding layer is formed in other surface parts excluding the conductor pattern arranged on the surface. The metallized layer is constituted preferably by using at least one out of Au, Ag, Cu, Pt and Pd as a main component, its ratio of area occupied to the surface area of the multilayer circuit board is preferably at least 20%, and its thickness is preferably 5 to 80mum.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、民生用やコンピュータ
用など電子工業に用いられる多層回路基板に係り、詳し
くは低抵抗性導体配線を内蔵し、かつ熱放散性が良好な
高密度多層回路基板及びその製法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer circuit board used in the electronics industry such as for consumer use and computers, and more specifically, it has a high-density multi-layer circuit containing low resistance conductor wiring and good heat dissipation. Substrate and manufacturing method thereof.

【0002】[0002]

【従来の技術】近年のハイブリッドICは、より小型
化、高密度化の要求から、グリーンシート上に電極パタ
ーンを印刷形成し、これらを積層、焼結することによっ
て、もしくは、スクリーン印刷の繰返しによって多層化
し、焼結することによって、基板内部に配線パターンを
持つセラミック多層配線基板が用いられてきた。その基
板を大別すると次の二つがある。その一つとして、例え
ば、特公平3−78798号公報の従来技術として記載
されるように、WやMoを配線導体として使用し、15
00〜1600℃の高い温度で同時焼成するセラミック
ス多層基板がある。
2. Description of the Related Art In recent years, hybrid ICs have been required to be smaller and have a higher density, by forming electrode patterns on a green sheet by printing, laminating and sintering them, or by repeating screen printing. A ceramic multilayer wiring board having a wiring pattern inside the board by multilayering and sintering has been used. There are two main types of substrates. As one of them, for example, W and Mo are used as wiring conductors as described in Japanese Patent Publication No. 3-78798.
There is a ceramic multilayer substrate that is co-fired at a high temperature of 00 to 1600 ° C.

【0003】他の一つとして、例えば、特開昭63−2
44899号公報に開示されるように、通常1000℃
以下の比較的低い温度で絶縁体の焼結ができる低温焼結
性セラミックス基板がある。上記の高温で焼成される基
板は、導体の抵抗率が大きく、高周波用回路への適用に
難があると共に、配線抵抗が大きくなってしまうので微
細配線化による回路の高密度化ができないという欠点が
あった。
As another one, for example, JP-A-63-2
As disclosed in Japanese Patent No. 44899, usually 1000 ° C.
There are low-temperature sinterable ceramic substrates that can sinter the insulator at the following relatively low temperatures. The above-mentioned substrate fired at a high temperature has a high resistivity of the conductor, which makes it difficult to apply to a high-frequency circuit, and the wiring resistance increases, so that the circuit density cannot be increased by fine wiring. was there.

【0004】一方、低温焼結性の基板では、焼成温度が
低いので、同時焼成する内蔵配線用導体材料として、A
u、Ag、Cuなどのいわゆる低抵抗性導体材料が使用
できる。その為、前述の導体抵抗率に関する問題点は解
決できる。しかしながら、この種低温焼結体基板には絶
縁材料として通常ガラスが使用される。この低温焼結性
ガラスは、例えばアルミナ基板に比較して熱伝導性が極
めて低い。そのため発熱性の電子部品、例えば消費電力
の大きいLSIチップなどを搭載すると基板の温度が上
昇しやすく、回路としての所望の特性を発揮しにくい。
高密度化された基板では発熱密度が高くなり、この問題
がいっそう顕著である。
On the other hand, since a low temperature sinterable substrate has a low firing temperature, it is possible to use A as a conductor material for internal wiring to be fired at the same time.
So-called low resistance conductor materials such as u, Ag and Cu can be used. Therefore, the above-mentioned problem regarding the conductor resistivity can be solved. However, glass is usually used as an insulating material for this kind of low temperature sintered body substrate. This low temperature sinterable glass has extremely low thermal conductivity as compared with, for example, an alumina substrate. Therefore, if a heat-generating electronic component such as an LSI chip with large power consumption is mounted, the temperature of the substrate is likely to rise, and it is difficult to exhibit desired characteristics as a circuit.
This problem is even more prominent in a substrate having a high density because the heat generation density is high.

【0005】[0005]

【発明が解決しようとする課題】以上記したように、低
抵抗性導体配線を内蔵し、表面に発熱性電子回路を配置
した多層回路基板では充分な放熱特性を得にくいという
問題があった。本発明はこうした問題点を解決し、かつ
低抵抗性の導体配線を内蔵した、小型かつ高密度の、高
周波用途を含む電子工業用多層回路基板とその製法を提
供することを課題とする。
As described above, there is a problem that it is difficult to obtain sufficient heat dissipation characteristics in a multilayer circuit board having a low resistance conductor wiring built-in and a heat generating electronic circuit arranged on the surface thereof. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a small-sized, high-density, multi-layer circuit board for the electronic industry including high-frequency applications, which has a built-in conductor wire having low resistance, and a manufacturing method thereof.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
に、本発明では、絶縁体上に所望の電気回路を形成する
導体パターンが配置され、該導体パターンと発熱性の電
子回路部品が電気的に接続された構造を有する多層回路
基板において、前記絶縁体としてガラスを用い、表面に
配置された該導体パターンを除く他の表面部分に、電気
的に独立するか又はグランド層と接続して放電用のメタ
ライズ層を形成することとしたものである。
In order to solve the above problems, according to the present invention, a conductor pattern forming a desired electric circuit is arranged on an insulator, and the conductor pattern and the heat-generating electronic circuit component are electrically connected. In a multi-layer circuit board having an electrically connected structure, glass is used as the insulator, and is electrically independent or connected to a ground layer on the other surface portion excluding the conductor pattern arranged on the surface. The metallization layer for discharge is formed.

【0007】上記多層回路基板において、発熱性電子回
路部品は、幾何学的に連続する前記メタライズ層上の一
部に載置されているのがよく、また、メタライズ層は、
前記多層回路基板の表面積に占める割合が少なくとも2
0%であり、厚さが5〜80μmであるのがよく、その
材質は、Au、Ag、Cu、Pt、Pdのうちの少なく
とも1つを主成分として構成されるのがよい。
In the above-mentioned multilayer circuit board, the heat-generating electronic circuit component is preferably placed on a part of the geometrically continuous metallization layer, and the metallization layer is
The multilayer circuit board has a surface area ratio of at least 2
The thickness is preferably 0%, the thickness is 5 to 80 μm, and the material is preferably composed mainly of at least one of Au, Ag, Cu, Pt, and Pd.

【0008】また、上記他の課題を解決するために、本
発明では、ガラス材料で構成される絶縁体層に導体層が
配置され、所望の電気的特性を実現する電子回路を有す
る多層電子回路基板の製法において、該電子回路と電気
的に絶縁され、かつ該基板の表面に占める面積比が少な
くとも20%の面積を有するメタライズ層を表層部に形
成し、かつ該メタライズ層上に発熱性電子部品を載置す
ることとしたものである。
Further, in order to solve the above-mentioned other problems, in the present invention, a multilayer electronic circuit having an electronic circuit in which a conductor layer is arranged on an insulating layer made of a glass material and which realizes desired electric characteristics. In the method for producing a substrate, a metallized layer that is electrically insulated from the electronic circuit and has an area ratio of at least 20% to the surface of the substrate is formed in the surface layer portion, and the heat-generating electron is formed on the metallized layer. The parts are to be placed.

【0009】上記のように、本発明では、絶縁性材料を
積層した基板の表層部に、Au、Ag、Cuなどの高熱
伝導性の、放熱用メタライズ層を、所定の電気回路を構
成する導体パターンとは電気的に絶縁して配置すること
により、基板からの熱放散を容易ならしめ、高精度の電
気的特性を有する、小型かつ高密度の、高周波用途を含
む電子工業用多層回路基板を実現するものである。
As described above, in the present invention, the metallization layer for heat dissipation having high heat conductivity such as Au, Ag, and Cu is provided on the surface layer portion of the substrate on which the insulating material is laminated, which constitutes a predetermined electric circuit. A multilayer circuit board for the electronic industry, which is small in size, has a high density, and has high-frequency applications, has a highly accurate electrical characteristic by facilitating heat dissipation from the board by arranging it electrically isolated from the pattern. It will be realized.

【0010】前記絶縁性材料は前述したように通常、軟
化点の低い低温焼結性ガラスで構成され、配線導体と同
時焼成される。前記表層部の放熱用メタライズ層の形成
にあたっては、次の二つの方法がある。一つは、表層回
路パターンが存在しない基板表面部分に、前記放熱用の
メタライズ層を直接形成する方法である。他の一つは、
表層回路パターン上にまず被覆用の絶縁層を形成し、そ
の上に該メタライズ層を形成する方法である。前者は簡
便法であり、後者はパターン設計上の自由度が高く、放
熱効果もより大きい。本発明による上記放熱用メタライ
ズ層を積層回路基板の表面に形成することにより、基板
からの熱放散が容易となり、高精度の電気的特性を有
し、かつ低抵抗性導体配線を内蔵する高密度の多層回路
基板が得られる。
As described above, the insulating material is usually made of low temperature sinterable glass having a low softening point and is fired at the same time as the wiring conductor. There are the following two methods for forming the heat dissipation metallization layer in the surface layer portion. One is a method of directly forming the metallization layer for heat dissipation on the surface portion of the substrate where the surface layer circuit pattern does not exist. The other one is
In this method, an insulating layer for coating is first formed on the surface circuit pattern, and then the metallized layer is formed thereon. The former is a simple method, and the latter has a high degree of freedom in pattern design and has a larger heat dissipation effect. By forming the heat dissipation metallization layer on the surface of the laminated circuit board according to the present invention, heat dissipation from the board is facilitated, high-precision electrical characteristics are achieved, and high-density conductive wiring with low resistance is built in. The multilayer circuit board of is obtained.

【0011】例えば、本発明による多層回路基板の内層
用絶縁体材料として、ほうけい酸鉛系ガラスを用いるこ
とによって、850℃程度の温度でも焼結できるので、
低抵抗性導体配線の内蔵が可能となり、その表層部にA
u、Ag、Cuなどの高熱伝導性の材料による前記放熱
用メタライズ層を設けることにより、放熱特性の向上を
図ることができる。そして、本発明で得られる多層回路
基板は、表層部に放熱用メタライズ層を包含し、かつ低
抵抗内蔵導体配線を有しているので、携帯用のカメラ一
体型ビデオ装置並びに信号を高速化した通信用電子機器
やコンピュータなどを構成する電子回路基板として有効
活用できる。
For example, by using lead borosilicate glass as the insulating material for the inner layer of the multilayer circuit board according to the present invention, it is possible to sinter even at a temperature of about 850 ° C.
Low resistance conductor wiring can be built in, and
By providing the heat dissipation metallized layer made of a material having high thermal conductivity such as u, Ag, or Cu, heat dissipation characteristics can be improved. Since the multilayer circuit board obtained by the present invention includes the metallization layer for heat dissipation in the surface layer and has the conductor wiring with the built-in low resistance, the portable camera-integrated video device and the signal are speeded up. It can be effectively used as an electronic circuit board that constitutes a communication electronic device or a computer.

【0012】[0012]

【作用】本発明は、低抵抗性の導体配線を内蔵し、その
表面に放熱用メタライズ層を形成して発熱性電子部品を
配置する構造である。従って、該電子回路で発生した熱
が局所に停滞する傾向が改善され、大面積に分散して、
大気中に効率良く放熱することができる。このことは、
熱伝導率は、絶縁体として用いるガラスが2W/mkで
あるのに対し、本発明で用いる放電用メタライズ層が4
20W/mkであることによる。ちなみに、熱伝導率は
AlNが200W/mk、BeOが300W/mkであ
り、これらを絶縁体として用いる場合はメタライズ層は
必要がない。従って、回路の高密度化にも有効である。
また、基板表層部に形成された該メタライズ層は不要輻
射電波を吸収、低減する作用がある。
The present invention has a structure in which a conductor wire having a low resistance is built in, a heat dissipation metallization layer is formed on the surface of the conductor wire, and a heat-generating electronic component is arranged. Therefore, the tendency for the heat generated in the electronic circuit to stagnate locally is improved, and the heat is dispersed over a large area,
It can dissipate heat efficiently into the atmosphere. This is
Regarding the thermal conductivity, the glass used as the insulator has a thermal conductivity of 2 W / mk, while the discharge metallized layer used in the present invention has a thermal conductivity of 4 W / mk.
Because it is 20 W / mk. Incidentally, the thermal conductivity of AlN is 200 W / mk and BeO is 300 W / mk, and when these are used as the insulator, the metallization layer is not necessary. Therefore, it is also effective for increasing the circuit density.
Further, the metallized layer formed on the surface layer of the substrate has a function of absorbing and reducing unnecessary radiation waves.

【0013】[0013]

【実施例】以下、本発明を実施例により具体的に説明す
る。 実施例1 図1及び図2に本発明の一実施例を示す。図1では本発
明による多層回路基板の発熱性電子部品を含む部分断面
図を示し、図2にはその平面図を示している。上記多層
回路基板は次のようにして製造する。まず、ほうけい酸
鉛ガラス粉と耐熱性フリットとしてのアルミナ粉末に、
ポリビニルブチラール等の有機溶媒を加えてかくはん
し、泥しょう化状態にする。この泥しょうを、ドクター
ブレードを用いたキャスティング成膜法によってグリー
ンシートとし、未焼成の電気絶縁性グリーンシートを複
数枚形成する。
EXAMPLES The present invention will be specifically described below with reference to examples. Embodiment 1 FIGS. 1 and 2 show an embodiment of the present invention. FIG. 1 shows a partial cross-sectional view including a heat-generating electronic component of a multilayer circuit board according to the present invention, and FIG. 2 shows a plan view thereof. The multilayer circuit board is manufactured as follows. First, lead borosilicate glass powder and alumina powder as heat resistant frit,
Add an organic solvent such as polyvinyl butyral and stir to make a sludge. This sludge is made into a green sheet by a casting film forming method using a doctor blade, and a plurality of unfired electrically insulating green sheets are formed.

【0014】次に、前記グリーンシートをステンレス等
から成る金型を入れ、外形と複数個の孔部(ビアホー
ル)とを同時にパンチングして形成する。このグリーン
シート上に、通常3μmΩ−cmより低い抵抗率が得ら
れる銀を主成分とする導体ペーストを、スクリーン印刷
法によって塗布して、表層パターン11もしくは内層導
体配線14を形成すると共にビアホール16を充填す
る。同様に作成した複数のグリーンシートを用いて順次
積み重ねる。次いで、熱プレス機等を用いて温度120
℃、圧力200kg/cm2 の条件で上下面から熱圧着
して、グリーンシートの積層体を得る。
Next, the green sheet is formed by inserting a mold made of stainless steel or the like and punching the outer shape and a plurality of holes (via holes) at the same time. On this green sheet, a conductor paste containing silver as a main component, which usually has a resistivity lower than 3 μm Ω-cm, is applied by a screen printing method to form a surface layer pattern 11 or an inner layer conductor wiring 14 and a via hole 16. Fill. It stacks up sequentially using a plurality of similarly prepared green sheets. Then, using a heat press machine or the like, a temperature of 120
A green sheet laminate is obtained by thermocompression bonding from the upper and lower surfaces under the conditions of ° C and pressure of 200 kg / cm 2 .

【0015】この成形体を、空気中、温度350℃で約
1時間脱脂した後、やはり空気中で800−1000
℃、約10分の焼成によって、低抵抗性の内層導体配線
部14を低温焼結性のガラスセラミック組成部18に内
蔵した多層回路基盤を得る。この基板上の、チップ部品
もしくは受動素子等を配置する部分を除く表層部に、被
覆用絶縁層20を形成し、その上に導体ペーストを用い
てスクリーン印刷−乾燥後焼成して放熱用メタライズ層
13を形成する。さらに、この基板上の所定位置にRu
2 を主体とする抵抗体12をスクリーン印刷によって
形成した後、乾燥−焼成して厚膜抵抗体を構成する。通
常は、さらにこの抵抗体上にガラスペーストを印刷−乾
燥し、600℃以下の低い温度で焼成して、保護ガラス
皮膜15を形成して、多層回路基板とする。この基板上
に発熱性のLSIチップを含む電子部品17を搭載し、
必要に応じてワイヤボンディング19などの手段によっ
て電気的に接続し、多層回路基板が完成する。
This molded body was degreased in air at a temperature of 350 ° C. for about 1 hour, and then 800-1000 in air as well.
By firing at 10 ° C. for about 10 minutes, a multi-layer circuit board in which the low-resistance inner-layer conductor wiring portion 14 is embedded in the low-temperature sinterable glass-ceramic composition portion 18 is obtained. A coating insulating layer 20 is formed on a surface layer portion of the substrate other than a portion where a chip component, a passive element or the like is arranged, and a conductor paste is used for screen printing-drying and firing to radiate a metallizing layer for heat radiation. 13 is formed. Further, Ru is placed at a predetermined position on this substrate.
After forming the resistor 12 mainly composed of O 2 by screen printing, it is dried and baked to form a thick film resistor. Usually, a glass paste is further printed-dried on this resistor and baked at a low temperature of 600 ° C. or lower to form a protective glass film 15 to form a multilayer circuit board. An electronic component 17 including a heat-generating LSI chip is mounted on this substrate,
If necessary, they are electrically connected by means such as wire bonding 19 to complete the multilayer circuit board.

【0016】本実施例では、LSIチップの接続方法と
して、ワイヤボンディング19を用いた例を示したが、
他の方法例えば、TCP(Tape Carrier Package) もし
くはCCB(Chip Carier Bonding)もしくはLCC(Le
adless Chip Carier) などの手段であってもよい。ま
た、内層の導体材料として、Agを用いた例について詳
細に記してきたが、Au、Pt、Pd及びこれらの合金
についても同様に使用可能である。Cuについても、不
活性ガス中で焼成することにより同様に適用可能であ
る。
In this embodiment, the wire bonding 19 is used as an LSI chip connecting method.
Other methods such as TCP (Tape Carrier Package) or CCB (Chip Carier Bonding) or LCC (Le
It may be a means such as adless Chip Carier). Further, although an example using Ag as the conductor material of the inner layer has been described in detail, Au, Pt, Pd and alloys thereof can also be used in the same manner. Similarly, Cu can be applied by firing in an inert gas.

【0017】実施例2 実施例1と同様の手順によって、低抵抗性の内層導体配
線部14を低温焼結性のガラスセラミック組成部18に
内蔵した多層回路基盤を得る。この基板上の、LSIチ
ップを接続する表層部の全面に、無電解めっき法によっ
て厚さ約2μmの銅皮膜を形成する。さらに、電解めっ
き法により該銅皮膜の膜厚を約25μmまで厚くする。
この皮膜表面に感光性レジンを塗布してパターニングす
るいわゆるホトレジスト法を用いて所望の形状を有する
放熱用メタライズ層13を含む、層数5層、50mm
角、厚さ0.8mmの、多層基板を作製した。このよう
に、放熱用メタライズ層13を、めっき法によって形成
することで、良好な該皮膜の膜厚制御性及び表面平滑性
が得られる。
Example 2 By the same procedure as in Example 1, a multi-layer circuit board in which the low-resistance inner layer conductor wiring portion 14 was embedded in the low temperature sinterable glass ceramic composition portion 18 was obtained. A copper coating having a thickness of about 2 μm is formed on the entire surface of the surface layer portion connecting the LSI chip on this substrate by electroless plating. Further, the thickness of the copper coating is increased to about 25 μm by the electrolytic plating method.
Number of layers: 5 layers, 50 mm, including a heat dissipation metallization layer 13 having a desired shape by using a so-called photoresist method in which a photosensitive resin is applied to the surface of the film and patterned.
A multilayer substrate having a corner and a thickness of 0.8 mm was produced. Thus, by forming the heat dissipation metallization layer 13 by the plating method, good film thickness controllability and surface smoothness of the film can be obtained.

【0018】実施例3 実施例1と同様の手順によって、低抵抗性の内層導体配
線部14を低温焼結性のガラスセラミック組成部18に
内蔵した多層回路基盤を得る。この基板上の、LSIチ
ップを接続する表層部に、直接銅箔を接合する、いわゆ
るダイレクトボンディング法を用いることによりメタラ
イズ層13を形成する。この方法は、銅箔の表面に生成
する酸化銅と、セラミック基板を形成する酸化物とを化
学反応によって結合するもので、通常、接合プロセス温
度は酸化銅の共晶点(1065℃)以上、銅の融点(1
083℃)以下である。ここで使用する銅箔は、表面の
全面を被覆するものでもよく、あるいは予め任意にパタ
ーニングされたものでもよい。前者の場合には実施例2
と同様に、ホトレジスト法を用いて所望の形状を有する
放熱用メタライズ層13を形成する。
Example 3 By the same procedure as in Example 1, a multi-layer circuit board in which the low-resistance inner layer conductor wiring portion 14 was incorporated in the low temperature sinterable glass ceramic composition portion 18 was obtained. The metallized layer 13 is formed by using a so-called direct bonding method in which a copper foil is directly bonded to the surface layer portion of the substrate to which the LSI chip is connected. In this method, the copper oxide formed on the surface of the copper foil and the oxide forming the ceramic substrate are bonded by a chemical reaction. Usually, the bonding process temperature is equal to or higher than the eutectic point (1065 ° C.) of the copper oxide, Melting point of copper (1
083 ° C) or lower. The copper foil used here may cover the entire surface, or may be optionally patterned in advance. Example 2 in the former case
Similarly, the metallization layer 13 for heat radiation having a desired shape is formed by using the photoresist method.

【0019】実施例4 実施例1と同様の手順によって、導体層数5層、50m
m角、厚さ0.8mmの、放熱用メタライズ層13を含
む多層基板を作製した。この時、放熱用メタライズ層1
3の占める面積率を、片側の基板表面積に対して7.8
%、15%、30%、50%、75%の5段階に調節し
てパターン形成し、その膜厚はいずれも15μm一定と
した。その基板中央部に11.6mm角、消費電力1.
7WのLSI17を1個搭載し、ワイヤボンディング1
9によって基板の所定部位に接続した。
Example 4 According to the same procedure as in Example 1, the number of conductor layers was 5 and the length was 50 m.
A multi-layer substrate having an m-square and a thickness of 0.8 mm and including the heat dissipation metallization layer 13 was produced. At this time, the heat dissipation metallization layer 1
The area ratio occupied by 3 is 7.8 with respect to the surface area of the substrate on one side.
%, 15%, 30%, 50%, and 75% were adjusted in five stages to form a pattern, and the film thickness was constant at 15 μm. 11.6mm square, power consumption 1.
One 7W LSI 17 is mounted for wire bonding 1
9 was used to connect to a predetermined portion of the substrate.

【0020】これら5種類の基板について、それぞれL
SIに定格電力を付加し、基板表面に風速2m/秒の送
風条件下でLSI表面の定常温度を測定した。その結
果、メタライズ層13の面積率が低い順に温度が高く、
それぞれ77.5℃、75℃、68.5℃、48℃、4
1.5℃であった。この結果より、面積率20%以下で
は熱放散効果が不十分と言え、実用的にはそれ以上、す
なわち少なくとも20%の面積率を有する放熱用メタラ
イズ層13を形成することが好ましい。
For each of these five types of substrates, L
The rated power was added to SI, and the steady-state temperature of the LSI surface was measured under the condition that the air velocity was 2 m / sec on the substrate surface. As a result, the temperature is higher in the ascending order of the area ratio of the metallized layer 13,
77.5 ° C, 75 ° C, 68.5 ° C, 48 ° C, 4
It was 1.5 ° C. From this result, it can be said that the heat dissipation effect is insufficient when the area ratio is 20% or less, but practically, it is preferable to form the heat dissipation metallization layer 13 having an area ratio of more than 20%.

【0021】実施例5 実施例2と同様の手順によって放熱用メタライズ層の基
板全体に対する面積率50%を有するテストサンプルを
作製した。この時、スクリーン印刷条件を変えることに
よってこのメタライズ層の膜厚を3μm−200μmの
範囲で10段階に調節した。完成したサンプルを実施例
2と同様に放熱効果を評価した。その結果膜厚5μm以
下では熱放散効果が不十分であった。一方、膜厚が80
μm以上ではメタライズ層の強度がセラミック基板との
比較で相対的に上昇し、基板自体が変形してしまうとい
う現象が有り、好ましくない。従って、セラミック基板
の強度及び放熱効果の両面を考慮してメタライズ層の膜
厚を設定する必要が有る。本実施例の条件では膜厚5μ
m−80μmが選定可能な適正膜厚範囲といえる。
Example 5 A test sample having an area ratio of the heat dissipation metallized layer to the entire substrate of 50% was prepared by the same procedure as in Example 2. At this time, the film thickness of this metallized layer was adjusted in 10 steps in the range of 3 μm to 200 μm by changing the screen printing conditions. The heat dissipation effect of the completed sample was evaluated in the same manner as in Example 2. As a result, the heat dissipation effect was insufficient when the film thickness was 5 μm or less. On the other hand, the film thickness is 80
When the thickness is more than μm, the strength of the metallized layer is relatively increased as compared with the ceramic substrate, and the substrate itself is deformed, which is not preferable. Therefore, it is necessary to set the film thickness of the metallized layer in consideration of both strength and heat dissipation effect of the ceramic substrate. Under the conditions of this embodiment, the film thickness is 5 μm.
It can be said that m-80 μm is the selectable proper film thickness range.

【0022】実施例6 本発明の一応用例を図3に示す。図は通信用電子交換機
システムの構成模式図を示している。発熱性のLSIチ
ップ素子34を含む本発明による回路モジュール35を
構成する。回路モジュール35を搭載した、多層プリン
ト基板によるマザーボード33を筐体32に装着して一
連の交換機回路システムを構成する。筐体32の上下部
位に設置したファン31による上昇方向の空気流で、回
路から発生する熱は系外に排出される。
Embodiment 6 FIG. 3 shows an application example of the present invention. The figure shows a schematic diagram of the configuration of a communication electronic exchange system. A circuit module 35 according to the present invention including a heat generating LSI chip element 34 is constructed. A mother board 33, which is a multilayer printed circuit board on which the circuit module 35 is mounted, is mounted on the housing 32 to form a series of exchange circuit systems. The heat generated from the circuit is discharged to the outside of the system by the upward airflow of the fans 31 installed in the upper and lower parts of the housing 32.

【0023】本実施例では空気流による冷却方式の例を
示したが、例えばこれが水冷式もしくはヒートパイプを
用いて、回路モジュール35に形成した放熱用メタライ
ズ層13から直接冷却する方式などにより、さらに高い
冷却効果が期待できる。以上の実施例は、いずれもセラ
ミック多層回路基板の例を示したが、例えば絶縁体材料
としてガラスエポキシを用いたプリント配線基板などに
も、本発明の適用が可能である。また、放熱用メタライ
ズ層の形成手段として厚膜による例及びめっきもしくは
銅箔の直接接合の例を示したが、これらを複合化した手
段の適用も可能である。
In the present embodiment, an example of the cooling method by the air flow is shown. However, for example, this is a water cooling type or a method of directly cooling from the heat radiation metallization layer 13 formed in the circuit module 35 by using a heat pipe. High cooling effect can be expected. Although all of the above examples show examples of ceramic multilayer circuit boards, the present invention can be applied to, for example, a printed wiring board using glass epoxy as an insulating material. Further, as the means for forming the metallizing layer for heat dissipation, an example using a thick film and an example of plating or direct joining of copper foils are shown, but means combining these are also applicable.

【0024】[0024]

【発明の効果】本発明によれば、低抵抗性導体配線を内
蔵し、かつ低熱抵抗性多層回路基板とすることができる
ので、導体パターンの微細配線化が可能となることに加
え、基板からの放熱特性が良好であるので、電子回路の
小型化もしくは高密度化に貢献でき、特に高速化又は高
周波化回路に有効使用できる。さらに、不要輻射電波に
よるノイズを低減する効果がある。
According to the present invention, since a low-resistance conductor wiring can be built-in and a low-heat resistance multilayer circuit board can be formed, it is possible to make the conductor pattern finer and to reduce the wiring from the board. The excellent heat dissipation property can contribute to downsizing or high density of electronic circuits, and can be effectively used especially for high speed or high frequency circuits. Furthermore, there is an effect of reducing noise due to unnecessary radiated radio waves.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による多層回路基板の断面構
成図。
FIG. 1 is a cross-sectional configuration diagram of a multilayer circuit board according to an embodiment of the present invention.

【図2】図1の多層回路基板の平面構成図。FIG. 2 is a plan configuration diagram of the multilayer circuit board of FIG.

【図3】本発明を用いる通信用電子交換機システムの構
成模式図。
FIG. 3 is a schematic configuration diagram of a communication electronic exchange system using the present invention.

【符号の説明】[Explanation of symbols]

11:表層導体パターン、12:膜厚抵抗体、13:放
熱用メタライズ層、14:内層導体、15:保護ガラス
皮膜、16:ビア、17:発熱性電子部品、18:絶縁
体ガラスセラミック組成部、19:ボンディングワイ
ヤ、20:被覆用絶縁層、31:ファン、32:筐体、
33:マザーボード、34:発熱性LSIチップ、3
5:回路モジュール、36:リードピン
11: surface layer conductor pattern, 12: film thickness resistor, 13: heat dissipation metallized layer, 14: inner layer conductor, 15: protective glass film, 16: via, 17: heat generating electronic component, 18: insulator glass ceramic composition part , 19: bonding wire, 20: insulating layer for coating, 31: fan, 32: housing,
33: Motherboard, 34: Exothermic LSI chip, 3
5: Circuit module, 36: Lead pin

───────────────────────────────────────────────────── フロントページの続き (72)発明者 長谷川 満 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuru Hasegawa 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 絶縁体上に所望の電気回路を形成する導
体パターンが配置され、該導体パターンと発熱性の電子
回路部品が電気的に接続された構造を有する多層回路基
板において、前記絶縁体としてガラスを用い、表面に配
置された該導体パターンを除く他の表面部分に、電気的
に独立するか又はグランド層と接続して放電用のメタラ
イズ層を形成したことを特徴とする多層回路基板。
1. A multi-layer circuit board having a structure in which a conductor pattern for forming a desired electric circuit is arranged on an insulator, and the conductor pattern and a heat-generating electronic circuit component are electrically connected to each other. A multi-layer circuit board characterized in that glass is used as a substrate, and a metallization layer for discharge is formed on the other surface portion excluding the conductor pattern arranged on the surface, either electrically independent or connected to a ground layer. .
【請求項2】 前記発熱性電子回路部品が、幾何学的に
連続する前記メタライズ層上の一部に載置されているこ
とを特徴とする請求項1記載の多層回路基板。
2. The multilayer circuit board according to claim 1, wherein the heat-generating electronic circuit component is mounted on a part of the geometrically continuous metallization layer.
【請求項3】 前記メタライズ層は、前記多層回路基板
の表面積に占める割合が少なくとも20%であることを
特徴とする請求項1又は2記載の多層回路基板。
3. The multilayer circuit board according to claim 1, wherein the metallized layer occupies at least 20% of the surface area of the multilayer circuit board.
【請求項4】 前記メタライズ層が、Au、Ag、C
u、Pt、Pdのうちの少なくとも一つを主成分として
構成されることを特徴とする請求項1、2又は3記載の
多層回路基板。
4. The metallized layer is made of Au, Ag, C
The multilayer circuit board according to claim 1, 2 or 3, wherein at least one of u, Pt, and Pd is a main component.
【請求項5】 前記メタライズ層は、厚さが5〜80μ
mであることを特徴とする請求項1〜4のいずれか1項
記載の多層回路基板。
5. The metallized layer has a thickness of 5 to 80 μm.
The multilayer circuit board according to any one of claims 1 to 4, wherein m is m.
【請求項6】 ガラス材料で構成される絶縁体層に導体
層が配置され、所望の電気的特性を実現する電子回路を
有する多層電子回路基板の製法において、該電子回路と
電気的に絶縁され、かつ該基板の表面に占める面積比が
少なくとも20%の面積を有するメタライズ層を表層部
に形成し、かつ該メタライズ層上に発熱性電子部品を載
置することを特徴とする多層回路基板の製法。
6. A method for producing a multi-layer electronic circuit board, wherein a conductor layer is arranged on an insulator layer made of a glass material, and the conductor layer is electrically insulated from the electronic circuit in a method of manufacturing the same. And a metallization layer having an area ratio of at least 20% to the surface of the substrate is formed in the surface layer portion, and a heat-generating electronic component is placed on the metallization layer. Manufacturing method.
JP5315791A 1993-11-24 1993-11-24 Multilayer circuit board and its manufacture Pending JPH07147349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5315791A JPH07147349A (en) 1993-11-24 1993-11-24 Multilayer circuit board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5315791A JPH07147349A (en) 1993-11-24 1993-11-24 Multilayer circuit board and its manufacture

Publications (1)

Publication Number Publication Date
JPH07147349A true JPH07147349A (en) 1995-06-06

Family

ID=18069603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5315791A Pending JPH07147349A (en) 1993-11-24 1993-11-24 Multilayer circuit board and its manufacture

Country Status (1)

Country Link
JP (1) JPH07147349A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1388916A1 (en) * 2002-08-09 2004-02-11 Agilent Technologies, Inc. - a Delaware corporation - Optoelectronic package
US6879488B2 (en) 2002-01-10 2005-04-12 Hitachi, Ltd. Radio frequency module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879488B2 (en) 2002-01-10 2005-04-12 Hitachi, Ltd. Radio frequency module
US7362576B2 (en) 2002-01-10 2008-04-22 Hitachi, Ltd. Radio frequency module
EP1388916A1 (en) * 2002-08-09 2004-02-11 Agilent Technologies, Inc. - a Delaware corporation - Optoelectronic package
US6841799B2 (en) 2002-08-09 2005-01-11 Agilent Technologies, Inc. Optoelectronic package

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