JPH0713876A - Ready signal control circuit - Google Patents

Abstract

PURPOSE:To prevent a process by a CPU from being interrupted with a ready signal. CONSTITUTION:When a peripheral device is accessed, a control signal 14 from a NAND(NOT-AND) gate 1 becomes HIGH and the ready signal 21 of the CPU is made active. At the same time, a counter circuit 3 starts a reset instruction and outputs a control signal 17 which is HIGH when a counter value reaches a specific value. When the control signal (carrier signal) 17 becomes HIGH, a control circuit 4 forcibly makes the ready signal 21 of the CPU inactive even when any one of ready signals 18, 19, and 20 from respective peripheral devices is active.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ready signal control circuit, and more particularly to a ready signal control circuit for reading and writing data from a CPU to peripheral devices.

[0002]

2. Description of the Related Art Conventionally, a ready signal control circuit of a CPU is
When reading and writing data from the CPU to each peripheral device, the peripheral device with a slow access time is transmitted from each peripheral device in order to insert a wait state signal in the cycle of the CPU. Each ready signal is directly used as a ready signal input to the CPU.

[0003]

In the conventional ready signal control circuit, each ready signal from each peripheral device is directly
Since the CPU ready signal is input, while the CPU is reading and writing data from and to each peripheral device (that is, the ready signal from the peripheral device is active), the ready signal is generated due to a failure of the peripheral device. When the signal does not become inactive (data reading and writing between the peripheral device and the CPU have finished executing), the ready signal is not inactive in the CPU, and the CPU wait cycle is inserted endlessly (Halt state). ) Take.

For this reason, it becomes impossible for the CPU to finish the reading process and the writing process to the peripheral device by itself. Further, there arises a problem that the execution of the program is stopped.

[0005]

The gist of the ready signal control circuit according to the present invention for solving the above problems lies in the following two items.

[1] In the ready signal control circuit, which is one of the input / output synchronization control methods of the CPU, which is the central processing unit of the computer for performing calculation and control, using the system clock signal as the synchronization clock, NAND gate (1) for receiving selection signals (11, 12, 13) to a plurality of peripheral devices for reading and writing and outputting the operation result, and NAND
An output pulse of a mono-multi circuit (2) that receives an output signal (14) of a (NAND) gate (1) and generates a pulse signal (15) having a predetermined time width. A reset command is given by the signal (15), the system clock signal is counted, and a count value is obtained.
A counter circuit (3) that outputs a control signal (carry signal) (17) when a predetermined count value is reached, and a ready signal (18, 19, 2) from a plurality of the peripheral devices.
0), the output signal (14) of the NAND (1) gate and the carry signal (17) of the counter circuit (3), and generate the wait state signal for the cycle of the CPU. A ready signal control circuit comprising a control circuit (4) for outputting a ready signal (21) of a CPU for causing the operation.

[2] An AND (logical product) gate (31) in which the control circuit (4) receives a ready signal (18, 19, 20) from each peripheral device and performs a logical product operation.
And the output of the AND (logical product) gate (31) and the control signal (carrier signal) (17) from the counter circuit (3).
AND (NO) gate (32) for performing a NOR operation with the output of the NOR (NOR) gate (32) and the control signal (carrier signal) (14) 2. A ready signal according to claim 1, comprising a NAND (Negative AND) gate (33), and an output (21) from the NAND (Negative AND) gate (33) is used as a ready signal of the CPU. Control circuit.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram of a control circuit 4 in FIG. 1, and FIG. 3 is a diagram of the first embodiment. It is a timing diagram.

Select signals 11, 12, 1 to a plurality of peripheral devices for the CPU to read and write data
NAND that receives 3 and outputs the operation result (Negative AND)
The gate 1 and the output signal 14 of the NAND (NAND) gate 1 are received, and the pulse signal 15 having a predetermined time width is received.
The reset signal is issued by the mono-multi circuit 2 which generates the signal and the output pulse signal 15 of the mono-multi circuit 2, the system clock signal is counted to obtain the count value, and when the count value is reached, the control signal (carry signal ) 17
A counter circuit 3 which outputs a signal and a ready signal 18, 19, 20 from a plurality of the peripheral devices,
Control circuit 4 which receives the output signal 14 of the gate 1 and the carry signal 17 of the counter circuit 3 and outputs the ready signal 21 of the CPU for generating the wait state signal for the cycle of the CPU. Composed of.

In FIG. 1, a NAND (Negative AND) gate 1 is a selection signal for all peripheral devices that require the insertion of a wait state signal because the access time is slow when reading and writing data from the CPU. Receiving 11, 12, and 13, the NAND operation is performed and the control signal 14 is output.

The mono-multi circuit 2 receives the control signal 14 from the NAND (Negative AND) gate 1 and receives the control signal 14
Generates a pulse signal 15 having a LOW level for a predetermined time, with a timing of rising from a LOW level to a HIGH level as a trigger.

The counter circuit 3 receives the pulse signal 15 output from the mono-multi circuit 2 as a reset command signal, counts the count value in synchronization with the clock signal 16 after completion of the reset command, and determines a predetermined value. When it becomes, a control signal (carrier signal) 17 which becomes a HIGH level pulse signal for one clock is output.

The control circuit 4 receives the ready signals 18, 19, 20 from the peripheral devices and performs an AND operation, and an AND (logical product) gate 31 and an output of the AND (logical product) gate and a counter. NOR for performing a NOR operation with the control signal (carrier signal) 17 from the circuit 3
A NAND (Nor) gate 32 for performing a NAND operation of the output of the (Nor) gate 32 and the output of the NOR (Nor) gate 32 and the control signal (carrier signal) 14.
Composed of and.

A NAND (Negative AND) gate (3
The output 21 from 3) becomes the ready signal of the CPU.

The control circuit 4 receives the ready signals 18, 19, 20 from the peripheral devices, receives the control signal (carrier signal) 14 from the NAND (Negative AND) gate 1, and the control signal (from the counter circuit 3). Carrier signal) 1
7, when the control signal 14 is at the LOW level or the control signal (carrier signal) 17 is at the HIGH level, the ready signal 21 of the CPU is set to the HIGH level regardless of the ready signals 18, 19, 20 from each peripheral device, and control is performed. When the signal 14 is HIGH level and the control signal (carrier signal) 17 is LOW level, when one of the ready signals 18, 19, 20 from each peripheral device is LOW level, the ready signal 21 of the CPU is LOW level. Output as.

The operation of the circuit of the first embodiment will be described more specifically with reference to FIG.

When reading and writing data from the CPU, the peripheral input to the NAND (Negative AND) gate 1 is processed at the time of processing with the peripheral device which does not need to insert the wait state signal for the CPU cycle. Since the device selection signals 11, 12, and 13 are all unselected (HIGH level), the control signal 14 output from the NAND (Negative AND) gate 1 becomes LOW level, and the control circuit 4 outputs the ready signal 21 of the CPU. To the inactive (HIGH level) state and output.
As a result, in this case, the wait state signal is not inserted for the CPU cycle from the external ready input.

When data is read from or written in by the CPU, the peripheral input to the NAND (Negative AND) gate 1 is processed at the time of processing with a peripheral device in which a wait state signal needs to be inserted for the CPU cycle. For example, the peripheral device selection signal 11 is selected (LOW level) among the device selection signals 11, 12, and 13, and the control signal 14 output from the NAND (Negative AND) gate 1 is in an active (HIGH level) state. .

Upon receiving the control signal 14, the control circuit 4 outputs the ready signals 18, 19 and 20 as the ready signal 21 of the CPU without changing the logical sum operation result.

For example, the ready signal 18 is active (L
LOW level), the ready signal 21 of the CPU becomes active (LOW level) in synchronization with the ready signal 18. If the ready signal 18 from the selected peripheral device becomes inactive (HIGH level) after a lapse of a predetermined time, the ready signal 21 of the CPU also becomes inactive (HIGH level) at the same time, and one cycle of the CPU is completed. Process shifts to the cycle.

Ready signal 1 from the selected peripheral device
8 is inactive (HIGH
When it does not reach the level), the ready signal 21 of the CPU also remains in the active (LOW level) state.

When the halt state is continued, the CPU cannot move to the next processing.

In order to avoid this state, it is necessary to force the ready signal 21 of the CPU to be inactive (HIGH level) after a certain period of time. The counter circuit 3 measures this fixed time. In the counter circuit 3, the control signal 1 from the NAND (Negative AND) gate 1
4 is reset by the pulse signal 15 output from the monomulti circuit 2 at the timing when 4 changes from the LOW level to the HIGH level, and then the clock signal 16
Counts in synchronization with.

For example, when counting for four clocks, the counter circuit 3 outputs a control signal (carrier signal) 17 of HIGH level for one clock when counting for four clocks. When the control signal (carrier signal) 17 becomes HIGH level, the control circuit 4 does not depend on the states of the ready signals 18, 19, 20 from the peripheral devices, and the CPU
Ready signal 21 of inactive (HIGH level)
State. As a result, the CPU finishes the insertion of the wait state signal and shifts the processing to the next cycle.

[0026]

As described above, in the ready signal control circuit according to the present invention, when the ready signal from the peripheral device is not recovered from the active state due to the failure of the peripheral device, the ready signal is forcibly inactivated after a certain time elapses. By this, there is an effect that the interruption of the CPU processing can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a control circuit 4 in FIG.

3 is a timing diagram for the first embodiment of FIG. 1. FIG.

[Explanation of symbols]

 1 NAND (Negative AND) Gate 2 Mono Multi Circuit 3 Counter Circuit 4 Control Circuit 11 Peripheral Device Selection Signal 12 Peripheral Device Selection Signal 13 Peripheral Device Selection Signal 14 Control Signal 15 Pulse Signal 16 Clock Signal 17 Control Signal (Carrier Signal) 18 Ready signal 19 Ready signal 20 Ready signal 21 CPU ready signal 31 AND (logical product) gate 32 NOR (negative logical sum) gate 33 NAND (negative logical product) gate

Claims (2)

[Claims] 1. A CPU which is a central processing unit of a computer which performs calculation and control by using a system clock signal as a synchronous clock, and a peripheral device (magnetic disk, RA).
M, ROM, etc.) is a ready signal control circuit for determining whether or not data is ready to be sent or received, and a selection signal to the plurality of peripheral devices for the CPU to read and write data. Receiving the output signal of the NAND (Negative AND) gate,
A mono-multi circuit that generates a pulse signal of a predetermined time width, a reset command is issued by the output pulse signal of the mono-multi circuit, the system clock signal is counted to obtain a count value, and a predetermined count value is reached. And a counter circuit that outputs a control signal (carry signal) when receiving, and the ready signals from the plurality of peripheral devices,
It is inserted in the machine cycle of the CPU to receive the output signal of the NAND gate and the carry signal of the counter circuit and to match the speed with the peripheral device (magnetic disk, RAM, ROM, etc.). And a ready signal control circuit for outputting the ready signal for generating a wait state signal. 2. An AND circuit in which the control circuit receives a ready signal from each of the peripheral devices and performs a logical product operation.
A (logical product) gate, a NOR (negative logical sum) gate for performing a negative logical sum operation of the output of the AND (logical product) gate and the control signal (carrier signal) from the counter circuit, and the NOR (negative logic) NAND for performing a NAND operation of the output of the (OR) gate and the control signal (carrier signal)
2. A ready signal control circuit according to claim 1, wherein said ready signal control circuit comprises a NAND gate, and an output from said NAND gate is used as a ready signal for the CPU.