JPH0713755A - Instruction decoding device - Google Patents

Abstract

PURPOSE:To reduce the power consumption of an instruction decoding device by using a clock output selector circuit which divides a microinstruction storing ROM into plural blocks and at the same time selects a relevant block out of the ROM when a microinstruction is carried out to supply a clock only to the selected block. CONSTITUTION:The instruction register output 5 and the state register output 6 serve as the address inputs of microinstruction storing ROM 3-1-3-n. The output 6 is also supplied to a clock output selector circuit 11, and the circuit 11 decodes the output 6 and selects an output destination corresponding to the state register value out of clock signals 12-1-12-n to supply it to a clock CK 9. The supply of clocks is continuously stopped to the clock output signals other than the selected one. Then an operating clock is supplied only to a microinstruction storing ROM 3-q corresponding to the executing state value by the signals 12-1-12-n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction decoding device inside a microcomputer.

[0002]

2. Description of the Related Art In recent years, low power consumption has become an important issue in the design of microcomputer application systems in the fields of industry and home appliances. In order to realize low power consumption of this system, low power consumption of the microcomputer, which is the center of the system, is an important key.

FIG. 4 is a block diagram showing the structure of a conventional instruction decoding device inside a microcomputer. Figure 4
Medium 1 is an instruction register. Reference numeral 2 is a state register that holds the execution state value of the instruction. 3 is a microinstruction storage R for storing microinstructions that describe the operation of the instruction
OM. Reference numeral 4 is an instruction input signal to the instruction register. Reference numeral 5 is an output signal of the instruction register. Reference numeral 6 is a state register output. The instruction register output signal 5 and the state register output 6 are used to store a micro instruction R
The address on the OM is specified. Reference numeral 7 is an output signal of the microinstruction storage ROM, which is a microinstruction output signal for instructing the operation of another block of the microcomputer. 8
Is also the output signal of the microinstruction storage ROM and the next execution state signal indicating the state value of the next execution state. Further, 9 is an operation clock CK of the instruction decoding unit.
The next execution state signal 8 is latched in the state register 2 in synchronization with the operation clock CK9. An instruction latch enable signal 10 is turned on only when the initial value of the state indicating the first state of the instruction is set in the state register 2.

FIG. 5 is a block diagram showing the structure of the address designation field and output field of the instruction storage ROM of the instruction decoding device. The addressing field is i
The instruction input of bits, the execution state value of j bits, and the output field consist of the microinstruction output of m bits and the next execution state value of p bits.

The operation of the conventional instruction decoder constructed as above will be described below.

In general, an instruction to a microcomputer is executed as a microcomputer instruction having a plurality of states synchronized with a basic clock inside the microcomputer. In FIG. 4, the microinstruction is stored in the microinstruction storage ROM 3, and the state register 2 stores the execution state value.
Now, if an instruction is decoded by the instruction decoding unit,
Micro instruction storage ROM in the final state of instruction decoding
As the next execution state signal 8 of 3, the initial value of the state indicating the first state of the instruction is output. The next execution state signal 8 causes the state register 2 to set an initial value in the next state in synchronization with the clock CK9. Also, the instruction latch enable signal 10 is turned on, and the instruction latch enable signal 10 causes the instruction register 1 to latch a newer instruction than the instruction input signal 4. In addition, micro instruction storage RO
In M3, the operating clock CK9 is supplied to the entire microinstruction storage ROM, and the microinstruction in the first state of the instruction having the address contents designated by the instruction register output 5 and the state register output 6 is clocked by the clock CK9.
Is output from the microinstruction output 7 in synchronism with. At the same time, the state value of the second state of the instruction is output to the next execution state signal 8 and set in the state register 2 in the next cycle in synchronization with the clock CK9. In the next cycle, similarly, the microinstruction storing ROM 3 outputs the microinstruction in the second state of the instruction. The same operation is repeated as many times as the number of states of the microinstruction forming the instruction.

[0007]

In the instruction decoding device having the conventional precharge type micro instruction storage ROM, the operation clock CK9 is constantly supplied to the entire micro instruction storage ROM, resulting in a large power consumption. There was a problem.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to realize low power consumption of an instruction decoding device having a precharge type micro instruction storage ROM.

[0009]

The present invention has the following constitution in order to solve the above-mentioned object. That is, in a microcomputer instruction decoding device having a precharge type micro instruction storage ROM, an instruction register holding an instruction to be decoded, a state register holding an execution state value of the instruction, an output of the instruction register and the A microinstruction storage ROM divided into a plurality of blocks addressed by the output of the state register, a clock output selection circuit that decodes the output of the state register, and a corresponding block is selected from the microinstruction storage ROM when the microinstruction is executed. And a clock supply selecting means for supplying a clock only to the corresponding block,
And a register circuit for holding the next microinstruction storage block designating signal during the next state period by a clock. Specifically, a circuit configuration is adopted in which the microinstruction storage ROM is divided into a plurality of blocks, and when the microinstruction is executed, the corresponding block is selected from the microinstruction storage ROM and a clock output selection circuit that supplies a clock only to the corresponding block is adopted. It was done. The block dividing means of the microinstruction storage ROM is a block dividing means that divides each instruction execution state value, and the clock supply selecting means decodes the output of the state register that holds the instruction execution state value. It is a means. The block dividing means of the microinstruction storing ROM is a block dividing means for dividing the stored data of the microinstruction storing ROM by providing a field indicating a block in which the next microinstruction is stored, and the clock supply selecting means is A clock supply selecting means for holding the output of the field by a holding circuit and decoding and selecting the contents in the next cycle.

[0010]

With the above construction, in the instruction decoding device of the microcomputer having the precharge type microinstruction storing ROM, the microinstruction storing R divided into a plurality of pieces.
Since the operation clock is supplied to only the corresponding block in the OM to operate, low power consumption can be realized.

Further, the microinstruction storage block can be selected by dividing the microinstruction storage ROM into a plurality of blocks and decoding the output of the state register which indicates the execution state value of the microinstruction.

After the second state of instruction execution, the microinstruction storing ROM can be divided into arbitrary plural blocks, the output of the field is held by the holding circuit, and the contents are decoded in the next cycle. This enables effective division of the micro instruction storage ROM and selection of the micro instruction storage block.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

First, the first embodiment will be described. Figure 1
FIG. 1 is a block diagram showing a configuration of an instruction decoding device according to a first embodiment of the present invention. 1, the same parts as those in FIG. 4 are designated by the same reference numerals 1, 2, 3, 4, 5, 6, 7, 8, 9, 10. However, 3-1 to 3-n are micro-instruction storage ROM 3 (micro-instruction storage ROM 3) divided into blocks
3-1 to ROM 3 -n) for storing microinstructions, which are divided into blocks for each execution state. Reference numeral 11 is a clock output selection circuit that selects a corresponding block and supplies an operation clock only to the corresponding block. 12-1 to 12-n are the clock output signal 1 to the clock output signal 1-n of the clock output selection circuit 11, which are the operation clocks of the microinstruction ROM 1 to the microinstruction ROM 1-n, respectively. 7-1 to 7-n
Is a micro instruction storage ROM block (3-1 to 3-n)
, 8-1 to 8-n are the next execution instruction signals of the micro instruction storing ROM blocks (3-1 to 3-n).

The operation of the instruction decoding unit according to this embodiment having the above-described structure will be described below.

Now, the qth state (q = 1 ...
It is assumed that n) has been decoded by the instruction decoding unit. The instruction register output 5 and the state register output 6 serve as address inputs of the micro instruction storage ROM 3-1 to the micro instruction storage ROM 3-n. Further, the state register output 6 is input to the clock output selection circuit 11. The clock output selection circuit 11 decodes the state register output 6 and outputs the output destination corresponding to the state register value to the clock output signal 1
One is selected from 2-1 to 12-n and the clock CK9 is supplied. For clock output signals other than the selected clock output signal, clock supply is still stopped. By the clock output signals 12-1 to 12-n, the corresponding micro instruction storage R corresponding to the execution state value is stored.
The operation clock is supplied only to OM3-q. As a result, the microinstruction and the next execution state signal are output from the microinstruction output 7-q and the next execution state signal 8-q only for the corresponding block. In addition, the microinstruction output of the microinstruction storage ROM 3 other than the corresponding block and the next execution state signal are in the high impedance state,
The micro instruction output 7-q is output to the micro instruction output 7 and the next execution state signal 8-q is output to the next execution state signal 8.

In the next state, the clock CK9
The next execution state value of the previous state is set in the state register by the input, and similarly, the operation clock is supplied only to the corresponding block and only the corresponding block operates.

Then, in the final state of the instruction, the initial value of the state indicating the first state of the instruction is output to the next execution state signal 8. And clock CK9
In synchronization with, the state register is initialized to the first state value, the instruction latch enable signal 10 is turned on, and a new instruction is set in the instruction register 1 from the instruction input signal 4. Thereafter, a sequence of microinstructions corresponding to the next instruction is similarly executed. In this way, the block in which the microinstruction is stored can be specified by the state register value, so that the read operation of only that block is possible.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the instruction decoding device according to the second embodiment of the present invention. 2 that are the same as those in FIGS. 1 and 4 have the same reference numerals 1, 2, 3-1 to 3-n, 4, 5,
6, 7, 7-1 to 7-n, 8, 8-1 to 8-n, 9, 11,
12-1 to 12-n and 10 are attached. 13 (13-1
13-n) is the output of the micro instruction storage ROM,
It is a next microinstruction storage block designating signal indicating a storage block in the next state. Reference numeral 14 is a register circuit, which holds the next micro instruction storage block designating signal 13 during the next state period by the clock CK9.

FIG. 3 shows an instruction storage ROM of the instruction decoding device.
Of the address specification field and output field, the address specification field is i-bit instruction input, j-bit execution state value, and the output field is m-bit microinstruction output, n-bit next micro. An instruction storage block designating bit and a p-bit next execution state signal. The next microinstruction storage block designating bit is a bit that designates a storage destination block of a microinstruction to be executed next. In the final state (kth state) of the instruction, the storage destination block of the first state common to each instruction is set. specify. In the first state to the (k-1) th state, it is possible to specify an arbitrary next micro instruction storage destination block.

The operation of the instruction decoding unit according to this embodiment having the above-described structure will be described below.

Now, it is assumed that the qth state of an instruction is decoded by the instruction decoding unit. The instruction register output 5 and the state register output 6 are the micro instruction storage ROM 3-1.
~ Address input to microinstruction storage ROM 3-n.
The register circuit 14 holds the content of the next micro instruction storage block designating signal 13 in the previous execution state, and the output of the register circuit 14 is input to the clock output selection circuit 11. The clock output selection circuit 11 decodes the output of the register circuit 14 and selects one of the clock output signals 12-1 to 12-n as the output destination corresponding to the bit value of the next microinstruction storage block designated by one state. Select and supply clock CK9. For clock output signals other than the selected clock output signal, clock supply is still stopped. By the clock output signals 12-1 to 12-n, the operation clock is supplied only to the corresponding microinstruction storage ROMq (q = 1 to n) corresponding to the next microinstruction storage block designating signal of one state before. As a result, the microinstruction, the next microinstruction storage block designating bit, and the next execution state signal only for the corresponding block are the microinstruction output 7-q, the next microinstruction storage block designating signal 13-q, and the next execution state signal 8-, respectively. The output from q, the microinstruction output of the microinstruction storage ROM 3 other than the corresponding block, the next microinstruction storage block designating signal, and the next execution state signal are in the high impedance state. Therefore, the microinstruction output 7-q becomes the microinstruction output 7, the next microinstruction storage block designating signal 13-q becomes the next microinstruction storage block designating signal 13, and the next execution state signal 8
-q is output to the next execution state signal 8. In the next state, the next execution state signal 8 of the previous state is latched in the state register by the input of the clock CK9, and the operation clock is supplied only to the corresponding block and only the corresponding block operates as described above.

Then, in the final state of the instruction, the initial value of the state indicating the first state of the instruction is output to the next execution state signal 8. Further, the next micro instruction storage block designating signal 13 outputs the storage destination block in the first state. Then, in the next state, the state register is initialized by the next execution state signal 8 in synchronization with the clock CK9, the instruction latch enable signal 10 is turned on, and a new instruction is set in the instruction register 1 from the instruction input signal 4. . Further, the register circuit 14 outputs the storage block number of the first state, and the clock output selection circuit 11 supplies the operation clock only to the storage block of the first state, so that only the block operates.

Thereafter, a sequence of micro-instructions corresponding to the next instruction is similarly executed. As described above, after the second state of instruction execution, the micro instruction storage ROM can be divided into arbitrary plural blocks, the output of the field is held by the holding circuit, and the contents are decoded in the next cycle. This enables effective division of the micro instruction storage ROM and selection of the micro instruction storage block.

[0025]

As is apparent from the above embodiments, according to the present invention, a precharge type micro instruction storage ROM is provided.
In the instruction decoding device of the microcomputer having the above, it is not necessary to supply the operation clock to the entire micro instruction storage ROM, and it is possible to significantly reduce the power consumption by supplying only the corresponding block.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an instruction decoding device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an instruction decoding device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an address designation field and an output field of an instruction storage ROM according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a circuit configuration of a conventional instruction decoding device.

FIG. 5 is a diagram showing a configuration of an address designation field and an output field of a conventional instruction storage ROM.

[Explanation of symbols]

 1 instruction register 2 state register 3 micro instruction storage ROM 4 instruction input signal 5 instruction register output signal 6 state register output signal 7 micro instruction output signal 8th execution state signal 9 instruction decoding unit operation clock CK 10 instruction latch enable signal 11 clock output Selection circuit 12 Clock output signal 13th micro instruction storage block designation signal 14 Register circuit

Claims (1)

[Claims] 1. A precharge type micro instruction storage RO.
In a microcomputer instruction decoder having M, an instruction register holding an instruction to be decoded, a state register holding an execution state value of the instruction, an output of the instruction register and an output of the state register are addressed. Microinstruction storage ROM divided into a plurality of blocks, a clock output selection circuit for decoding the output of the state register, a corresponding block is selected from the microinstruction storage ROM when the microinstruction is executed, and a clock is supplied only to the corresponding block. An instruction decoding device comprising: a clock supply selecting means; and a register circuit which holds a next micro instruction storage block designating signal by a clock during a next state period.