JPH0962505A - Address variable register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an address variable register which can be utilized as a hardware common for various systems and can be constructed by setting a new address even when newly adding an I/O. SOLUTION: This address variable register is composed of an address decode part 2 for decoding the address of an address setting register part 3 from address data from a CPU 1, an address setting register part 3, with which register address data from the CPU are temporarily stored and outputted, having plural register select terminals 32 to be sequentially selected, a plural register address data latch parts 4 which are to be selected by the register select terminals 32, store the register address data from the address setting register part 3 at the time of initial setting and output comparison signals in comparison with the address data from the CPU 1 at the time of ordinary operating, and a plural registers 5 to be selected by the compare signals and to be accessed from the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register used in a device having a CPU such as a personal computer, and more particularly to a CP.
The present invention relates to a device whose address can be changed under the control of U.

[0002]

2. Description of the Related Art Conventionally, a register used in a device such as a personal computer equipped with a CPU has its address fixed as an I / O, and operates and is used with each role. However, in order to use it as hardware common to various systems, the method of setting and constructing addresses must be the same, and if only some of the addresses are different, there is a problem that they cannot be shared. In addition, when a new I / O is added to the existing system, there is a problem that the fixed address cannot add the address and thus cannot handle it.

[0003]

The present invention solves the above-mentioned problems and can be used as hardware common to various systems, and even when a new I / O is added,
It is intended to provide an address variable register that can set and construct a new address.

[0004]

In order to solve the above-mentioned problems, the first invention is an address decoding section for decoding an address of an address setting register section from address data from a CPU, and the address decoding section. An address setting register unit which has a plurality of register selection terminals which are sequentially switched by a decode signal from the unit and which selects a plurality of address data latch units, and which temporarily stores and outputs register address data from the CPU; The register address data selected from the plurality of register selection terminals of the setting register unit is stored in the address setting register unit at the time of initial setting. During normal operation, the stored address data is compared with the address data from the CPU for comparison. A plurality of the address data latch units that output signals, and the address data latch units. It is selected by the comparison signal from the data latch section and composed of a plurality of registers to be accessed from the CPU. According to a second aspect of the present invention, the address decoding unit that decodes the address of the address setting register unit from the address data from the CPU, and the data from the CPU are temporarily stored by the decode signal from the address decoding unit, and are stored. An address setting register section having register selection terminals for outputting register address data and write position data from data, and decoding register number data to select a plurality of address data latch sections; and the address setting register section The register address data selected from the register selection terminal is stored based on the write position data at the time of initial setting, and the stored address data is compared with the address data from the CPU during normal operation. Output multiple comparison signals A register address data latch unit is selected by the comparison signal from the register address data latch unit, and composed of a plurality of registers to be accessed from the CPU.

[0005]

According to the address variable register of the first aspect of the present invention, the address data of a plurality of registers sequentially selected by the address setting register is input from the CPU to the address setting register when the system is activated. , Register address data is sequentially stored in the address data latch unit sequentially selected from the address setting register, thereby setting addresses of a plurality of registers,
According to the address variable register of the second aspect of the present invention, when the system is started up, a register number is arbitrarily designated from the CPU via the address setting register, and the address data is stored in the address data latch section. After setting the address and after starting, the address data from the CPU is compared with the register address data stored in the address data latch unit, the address data latch unit storing the same address data selects the corresponding register, and the CPU It is accessible.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An address variable register according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of an address variable register according to the present invention. In the figure, reference numeral 1 denotes a CPU, which outputs various signals in accordance with a program and controls writing and reading of data. An address decoding unit 2 decodes an address of an address setting register unit 3 described later and outputs a decoded signal. Reference numeral 3 denotes the address setting register section, which counts the number of times the address decoding section 2 decodes the address of the address setting register section 3 and counts up every two times to output count data. A plurality of register selection terminals 32 that output selection signals according to the count data from 31
, A first AND circuit 34 for inputting register address data from the CPU 1 in response to the address decode signal, and an 8-bit setting register 35 for temporarily storing the input data.
And a register address data output terminal 36 for outputting register address data from the setting register 35. An address data latch unit 4 includes a second AND circuit 41 for inputting register address data from the register address data output terminal 36 in response to a selection signal from the register selection terminal 32, and a data latch for storing the register address data. The comparison unit 43 compares the latched data with the address data from the CPU 1 and outputs a register selection signal if they are the same.
It consists of: Reference numeral 5 denotes a register, which is the comparison unit 43.
Is connected to the data line from the CPU.

FIG. 2 is a principal block diagram showing another embodiment of the address variable register according to the present invention. In the figure, those having the same functions as those in FIG. 1 use the same symbols. In the case of the present embodiment, the address setting register unit 3 sets the upper 4 bits of the setting register 35 having an 8-bit structure to the register address data unit 35a. , A register address data output terminal 36 for outputting the register address data from the register address data section 35a by dividing the upper 2 bits of the lower 4 bits into a write position data section 35b and the lower 2 bits into a register number data section 35c. , A write position data output terminal 37 for outputting the write position data from the write position data section 35b, a number decoding section 38 for decoding the register number data from the register number data section 35c, and a plurality of the number decoding sections 38. Register selection terminal 32 for outputting each decoded signal
And the first AND circuit 34.

The address data latch unit 4 also outputs a second AND circuit 41 for inputting register address data from the register address data output terminal 36 in response to a selection signal from the register selection terminal 32 and the write position data output. A write position decoder 44 that decodes the write position data from the terminal 37, and four third AND circuits 45 (which gate the register address data from the second AND circuit by a decode signal from the write position decoder 44 ( 45a, 45b, 45
c, 45d) and four 4-bit data latches 42 (42a, 42b. 42c, 42d) respectively storing register address data from the four third AND circuits.
And the comparing section 43 for comparing the data of the four data latches 42 and the address data from the CPU 1.

FIG. 3 is a block diagram of essential parts showing another embodiment of the address variable register according to the present invention. In the figure, the same symbols as those in FIGS. 1 and 2 use the same symbols. In the case of this embodiment, the setting register 35 of the address setting register unit 3 uses two 8-bit configuration registers. The address data part 35a uses 8 bits of one setting register 35, the write position data part 35b uses the upper 1 bit of the other register 35,
The register number data section 35c uses the lower 7 bits. The number of third AND circuits 45 in the address data latch unit 4 is two.

In the above structure, the operation will be described below.
First, the embodiment of FIG. 1 will be described. When the power is turned on and the system is started up, first, the CPU 1 sequentially sets the addresses of the registers 5 in accordance with the initial setting program. Therefore, the address of the address setting register unit 3, for example, 000F (HEX display) is used as the address data. By outputting to the line, the address decoder unit 2 decodes this address, opens the gate of the first AND circuit, and when this address decode signal is input three times, the counter 31 counts up and counts. Each time an up signal is output and the counter counts up, the selection output of the sequential selector 33 is sequentially switched. In the initial state, the first register selection terminal 32a is selected.
To choose. Next, the CPU outputs predetermined address data of each register 5 to the data line so that the address data is sequentially stored in the setting register 35 and output through the first AND circuit having the gate opened. Have control over.

Referring to FIG. 3, in the embodiment shown in FIG. 1, the CPU displays the address of the first register 5a in the HEX display 123.
No. 2 at 4H address (addresses below are HEX display)
When the address of the 5th register 5b is set to the address 5678H, the data to be sequentially sent to the setting register 35 is shown. The upper 4 bits of the first 8-bit data are 1 (0001) of the address 1234H, The lower 4 bits are 2 (0010), and the upper 4 bits of the next 8-bit data are 3 (0 of the address 1234H).
011) and the lower 4 bits indicate 4 (0100). When the first 8-bit data is set in the setting register 35, this 8-bit data is sent to the address data latch unit 4. First address data latch unit 4
The first register selection terminal 32a selected by the sequential selector is connected to a, the gate of the second AND circuit 41a is opened, and the 8-bit data from the setting register 35 is data latched. Part 4
2a is input and stored. In this manner, by sequentially sending 8-bit data to the setting register of the address setting register 3, the address 1234H of the first register is stored in the first address data latch unit 4a. It

Further, since the address of the second register 5b is set to the address 5678H, the CPU 1 outputs the address of the address setting register unit 3, 000F (HEX display) to the address data line and the address decoder decodes it. Since the address decode signal counts up the counter 31 and selects the selection output of the sequential selector 33 to the second register selection terminal 32b, the second address data latch unit 4b to which the register selection terminal 32b is connected is connected. The gate of the second AND circuit 41b is opened, and the setting register 35 is opened.
The 8-bit data is input to and stored in the data latch unit 42b. In this manner, by sequentially sending 8-bit data to the setting register of the address setting register 3, the address 5678H of the second register is stored in the second address data latch unit 4b. It Similarly, the address of each register 5 is stored in each address data latch unit 4.

When the initial setting is completed, the CPU 1 performs a normal operation according to a normal program. For example, in order to access the first register, the CPU outputs the address 1234H set in the first register to the address line. Then, the comparison unit 43 compares the address data stored in the data latch unit 42 with the same address 123.
The output of the comparator 43a of the first address data latch unit 4a in which the 4H address is stored becomes H, and the register 5a corresponding to this becomes accessible.

The operation of the embodiment shown in FIG. 2 will be described below. In the case of FIG. 2, when the CPU outputs the address of the address setting register 3 as the initial setting operation, the gate of the first AND circuit opens, and C
The data from the PU is stored in the setting register. In the case of the present embodiment, the data from the CPU is the 8-bit data, and the upper 4 bits are the upper 1st data of the register address data, as shown in FIG. , The lower 4 bits specify the writing position, and the upper 2 bits of the lower 4 bits are storage position data indicating the storage position of the setting register 42,
The lower 2 bits indicate the register number. Therefore, C
The PU can set the address of one register by sending out 8-bit data four times.
When the address of the first register 5a is set to 1234H, the 8-bit data transmitted four times is (00011101), (00101001),
(00110101) and (00010001).

The register address data section 35a of the address setting register section 3 outputs register address data composed of upper 4 bits, and the write position data section 3
5b outputs the write position data of the upper 2 bits of the 4 bits. Also, the inner 4 bits of the inner 4 bits
The register number data from the register number data section 35c that stores bits is decoded by the number decoding section 38, and the selected output terminals 32a, 32 are sequentially output from the first.
b, 32c and 32d respectively output. In the case of FIG. 4, the gate of the second AND circuit of the first address data latch unit 4a to which the selection output terminal 32a is connected is opened, the register address data is input, and the write position decoding unit is also provided. The write position data is decoded at 44, the write position of the address data latch unit 42 is selected by the third AND circuit 45,
The register address data input to a predetermined position is stored. The subsequent normal operation is the same as that of the embodiment shown in FIG.

Next, the operation of the embodiment shown in FIG. 3 will be described. In the case of FIG. 3, when the CPU outputs the address of the address setting register 3 as the initial setting operation, as in the case of FIG. 2, the gate of the first AND circuit opens, and C
The data from the PU is stored in the setting register. In the case of this embodiment, the data from the CPU is the register address data for the first 8-bit data and the upper 1-bit of the next 8-bit data as shown in FIG. Is the write position data, and the lower 7 bits are the register number data. Up to four register numbers can be set in the embodiment of FIG. 2, but 128 can be set in this example. The following operation is similar to that of the embodiment shown in FIG.

In the above embodiment, the object whose address is changed is a register, but various I's are used instead of the register.
Needless to say, it can be replaced with / O.

[0018]

As described above, according to the address variable register of the first invention, the address data of a plurality of registers sequentially selected by the address setting register is input from the CPU to the address setting register when the system is activated. , Register address data is sequentially stored in the address data latch unit sequentially selected from the address setting register, thereby setting addresses of a plurality of registers,
According to the address variable register of the second aspect of the present invention, when the system is started up, a register number is arbitrarily designated from the CPU via the address setting register, and the address data is stored in the address data latch section. After setting the address and after starting, the address data from the CPU is compared with the register address data stored in the address data latch unit, the address data latch unit storing the same address data selects the corresponding register, and the CPU Since writing and reading are performed according to the control, it can be used as common hardware for various systems, and even when adding a new I / O, it is possible to set a new address and build. It is possible to provide an address variable register that can be used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an address variable register according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the address variable register according to the present invention.

FIG. 3 is a block diagram showing another embodiment of the address variable register according to the present invention.

4 is a diagram showing a bit configuration of data set in an address setting register of the embodiment shown in FIG.

5 is a diagram showing a bit configuration of data set in the address setting register of the embodiment shown in FIG.

6 is a diagram showing a bit configuration of data set in the address setting register of the embodiment shown in FIG.

[Explanation of symbols]

 1 CPU 2 Address Decoder 3 Address Setting Register 4 Register Address Data Latch 5 Register 31 Counter 32 Register Select Terminal 33 Sequential Selector 34 First AND Circuit 35 Setting Register 36 Register Address Data Output Terminal 37 Writing Position Data Output Terminal 41 Fourth 2 AND circuit 42 Data latch unit 43 Comparison unit

Claims (8)

[Claims] 1. An address decoding unit for decoding an address of an address setting register unit from address data from a CPU, and a plurality of address data latch units that are sequentially switched by a decode signal from the address decoding unit. CPU with register selection terminal
The address setting register section for temporarily storing and outputting the register address data from and the plurality of register selecting terminals of the address setting register section are selected, and the register address data from the address setting register section is stored at the initial setting, In the normal operation, a plurality of the address data latch units for comparing the stored address data with the address data from the CPU and outputting a comparison signal, and selected by the comparison signal from the address data latch unit,
An address variable register comprising a plurality of registers accessed by a CPU. 2. An address decoding unit that decodes an address of an address setting register unit from address data from the CPU, and temporarily stores data from the CPU by a decode signal from the address decoding unit, and from the stored data, An address setting register unit having register selection terminals for outputting register address data and write position data, and decoding register number data to select a plurality of address data latch units, and register selection of the address setting register unit The register address data selected by the terminal is stored based on the write position data from the address setting register section at the time of initial setting, and during normal operation, the stored address data is compared with the address data from the CPU for comparison. Multiple registers that output signals An address variable register comprising an address data latch unit and a plurality of registers selected by a comparison signal from the register address data latch unit and accessed by the CPU. 3. The address setting register section counts the number of times the address decoding section decodes the address of the address setting register section, counts up every predetermined number of times, and outputs count data. Sequential selector that selects a plurality of register selection terminals that output a selection signal according to the count data, a first AND circuit that inputs data from the CPU according to the address decode signal, and a setting register that temporarily stores the input data. The address variable register according to claim 1, wherein: 4. The address data latch unit stores a second AND circuit for inputting the register address data according to a selection signal output from a predetermined register selection terminal of the address setting register unit, and the register address data. 2. An address variable register according to claim 1, further comprising: a data latch unit for storing the data, and a comparator unit for comparing the register address data stored in the data latch unit with the address data from the CPU and outputting a comparison signal. . 5. The address setting register section includes a first AND circuit for inputting data from a CPU in response to a decode signal from the address decoding section, a setting register for temporarily storing the input data, and the storing section. A register address data output unit that outputs a bit of register address data from data, a write position data output unit that outputs a bit that specifies a write position, and a selection signal that decodes the register number data and selects a plurality of registers. 3. The address variable register according to claim 2, further comprising a number decoding section having a register selection terminal for outputting. 6. The address data latch unit decodes the write position data and a second AND circuit for inputting the register address data according to a selection signal output from a predetermined register selection terminal of the address setting register unit. And a write position decoding unit that outputs a write position signal, a data latch unit that stores register address data input from the second AND circuit based on the write position signal, and a register address that is stored in the data latch unit 3. An address variable register according to claim 2, wherein the address variable register comprises a comparing section for comparing the data with the address data from the CPU and outputting a comparison signal. 7. The setting register has an n-bit configuration, the upper n / 2 bits are register address data, and the upper m bits in the lower n / 2 bits are write position data.
3. The address variable register according to claim 2, wherein the lower n / 2-m bits are used as register number data. 8. The setting register has an n-bit + n-bit configuration, one n-bit of which is register address data, the other n-bit of which is the most significant m-bit of write position data and the lower n-m-bit of which is a register. 3. The address variable register according to claim 2, which is used as number data.