JPH04253236A - Access control system - Google Patents

Abstract

PURPOSE:To reduce the number of signals to be inputted from the outside to an access switching circuit concerning the access control system to switch plural memory access modes. CONSTITUTION:Prescribed address ranges are respectively allocated to the plural access modes having the various kinds of access velocity. A decoder 31 decodes a read address outputted from a microprocessor or the like and outputs a mode select signal to a decoder 33, 34 or 35 so as to select the access mode such as a normal mode, pair mode and burst mode or the like based on the decoded result. Based on the above-mentioned mode select signal, the decoders 33, 34 and 35 access a memory by outputting one kind of enable signals, two kinds of enable signals or more than three kinds of enable signals within one access cycle.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access control system for switching between a plurality of access modes having different access speeds.

0002

2. Description of the Related Art Generally, it takes a certain amount of time for a memory such as a ROM to actually output data after being accessed by a microprocessor or the like.

Therefore, when accessing multiple ROMs, it is common practice to access other ROMs between accessing one ROM and outputting data from that ROM to increase the overall access speed. ing.

In this access method, the case where two ROMs are accessed in one access cycle is called a pair mode, and the case where three or more ROMs are accessed is called a burst mode. On the other hand, a mode in which one ROM is accessed in one access cycle, that is, a mode in which the next access is made after data is output from the ROM, is called a normal mode.

Conventionally, a circuit for controlling access to a memory such as a ROM has been configured to be able to switch between these three types of access modes using a switch or the like. Figure 7 shows 3
FIG. 2 is a circuit configuration diagram of a conventional access switching circuit that switches between different access modes using a switch.

In the access switching circuit shown in FIG. 7, the other circuits except the switch section 11 are composed of, for example, one LSI, and the operation signals of the switches SW1 and SW2 are connected between the switch section 11 and the LSI. It is connected by two transmitting signal lines.

In FIG. 7, a switch section 11 is a circuit that selects one of three access modes. One ends of the switches SW1 and SW2 are grounded, and the other ends are connected to the resistors R1 and R2, each of which has one end connected to a power supply voltage, and to the inverters 12 and 13. The outputs of these inverters 12 and 13 are output to a decoder 14.

From this decoder 14, switch SW1
, a normal mode signal, a pair mode signal, and a burst mode signal are output to control terminals G of the decoder 15, decoder 16, and decoder 17 according to the setting states of SW2.

For example, when switches SW1 and SW2 are both off, the inputs of inverters 12 and 13 each become high level, a normal mode signal is output from decoder 14, and decoder 15 is enabled.

[0010] Also, switch SW1 is on, switch S
When W2 is off, the input of inverter 12 is at low level, the input of inverter 13 is at high level, and decoder 14 outputs a pair mode signal.
6 is enabled.

Further, when the switch SW1 is off and the switch SW2 is on, the input of the inverter 12 becomes high level, the input of the inverter 13 becomes low level, the burst mode signal is output from the decoder 14, and the decoder 17 is enabled. Become.

In the modal mode, the address data latched in the address latch 18 is decoded by the decoder 15, and based on the decoding result, the decoder 1
Any one of the corresponding outputs a to d of No. 5 becomes "0".

[0013] This allows the enable signal to be output from any of the outputs of the AND gates 20 to 23.

[0014]OE00,

[0015]OE01,

[0016] OE02, or

Normal mode access is performed in which OE03 is output and one enable signal is output in one memory cycle. On the other hand, in pair mode,
For example, when the upper bit of the address data input to the decoder 16 is "0" or "1", when the output of the address counter 19 changes, the outputs a and b of the decoder 16 alternate in synchronization with the clock signal CLK. The outputs c and d become "0" alternately.

As a result, two enable signals are output from the AND gates 20 to 23 in one access cycle.

00
19] OE00,

[0020]OE01 or

[0021]OE02,

[0022] OE03 is output and pair mode access is performed. On the other hand, in the burst mode, the output of the address counter 19 is sequentially counted up in synchronization with the clock signal, and the outputs a to d of the decoder 17 become "0" sequentially.

With this, for example, four enable signals are output from the AND gates 20 to 23 in one access cycle.

[0024]OE00,

[0025]OE01,

[0026]OE02,

OE03 is sequentially output and burst mode access is performed.

[0028]

[Problems to be Solved by the Invention] The above-mentioned access switching circuit generally consists of one or more LSIs, except for the switch section 11 (because the switch section 11 needs to be able to be set externally). Often configured.

In this case, it is necessary to take into the LSI a signal output from the switch section 11 for selecting an access mode such as normal mode, pair mode, or burst mode. Therefore, signal lines for inputting these signals are required, and there is a problem that the number of pins of the LSI increases.

An object of the present invention is to simplify the circuit by eliminating a switch circuit for switching between a plurality of access modes, and to reduce the number of signal lines required to be input from the outside.

[0031]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, when predetermined address ranges are assigned to multiple memory access modes,
The mode selection means 1 determines in which of the address ranges assigned to the respective modes the read address falls, and selects one of the plurality of access modes. This mode selection means 1 is
For example, it can be configured with a decoder, which decodes the read address and selects the access mode corresponding to the address.

The access switching means 2 outputs an enable signal for sequentially accessing one or more memories corresponding to the access mode selected by the mode selection means 1.

[0033]

[Operation] In the present invention, predetermined address ranges are assigned to each of a plurality of memory access modes. Then, the mode selection means 1 determines which address range of the address ranges assigned to each mode the read address output from the microprocessor, etc. corresponds to, and selects the access mode corresponding to that address. I have to.

The access switching means 2 outputs one or more enable signals within one memory cycle based on the selection result of the mode selection means 1. Therefore, there is no need to switch the memory access mode using a switch or the like, and the structure of the access switching circuit can be simplified and the number of signal lines input to the circuit can be reduced.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a ROM access switching circuit according to an embodiment of the present invention.

In this embodiment, as shown in FIG.
00 0000” ~ “1FFF FFFF” (16
(base number, the same applies hereafter) to normal mode, and set the address to "
Set the addresses ``2000 0000'' to ``3FFF FFFF'' to pair mode, and set the addresses ``4000 0000'' to ``3FFF FFFF'' to pair mode.
5FFFFFFFF" address is assigned to burst mode.

Furthermore, FIGS. 5 and 6 show an example of the configuration of a ROM when the above address ranges are assigned to each access mode. In this example, four ROMs (for example, ROM00 to ROM
03) is used to represent 32-bit data of the microprocessor.

For example, in the ROM configuration corresponding to the normal mode shown in FIG.

[0039] 4 ROM00 to ROM by OE00
03 are accessed simultaneously. In addition, in the ROM configuration corresponding to the pair mode shown in Figure 5(B), ROM00 to R
The 8 ROMs of OM07 have the address “2000 00
Data from ``00'' are stored in order, and the enable signal

OE00 causes ROM00 to ROM03 to receive an enable signal.

ROM04 to ROM07 are simultaneously accessed by OE01. Furthermore, in the ROM configuration compatible with the burst mode shown in FIG. 6, ROM00 to ROM15
The 16 ROMs have the address “4000 0000
” is stored in order, and the enable signal

OE00 causes ROM00 to ROM03 to receive an enable signal.

OE01 causes ROM04 to ROM07 to receive an enable signal.

By OE02, ROM08 to ROM11 receive an enable signal.

ROM12 to ROM15 are simultaneously accessed by OE03. In FIG. 2, the address latch 32 is a circuit that latches address data (32-bit address data ADR0 to ADR31) output from the microprocessor, and sends ADR30 and ADR29 of the latched data to the decoder 31.
ADR24 to decoders 33 and 34, ADR23
is output to the decoder 33, and ADR2 and ADR3 are output to the address counter 36.

The decoder 31 has the address latch 32
ADR30 and AD of the address data latched in
This circuit decodes R29 and switches between three access modes: normal mode, pair mode, and burst mode.

For example, ADR30 and ADR29 are “
00", that is, the address is "0000 000
When it is in the range of “0” to “1FFF FFF”,
An enable signal is output to the control terminal G of the decoder 33 to perform normal mode access.

[0048] Also, ADR30 and ADR29 are "0".
1”, that is, the address is “2000 0000
” to “3FFF FFFF”,
An enable signal is output to the control terminal G of the decoder 34 to perform pair mode access.

Furthermore, ADR30 and ADR29 are “
10", that is, the address is "4000 000
” to “5FFF FFFF”,
An enable signal is output to the control terminal G of the decoder 35 to perform burst mode access.

The address counter 36 receives a load signal (L
This circuit counts up the address value fetched in synchronization with the clock signal (CLK) in synchronization with the rising edge of the clock signal (CLK).The lower bit O0 of the count value is sent to the decoder 34, and the lower bit O0 and the upper bit O1 are sent to the decoder 35. Output to. Note that this address counter 3
The count value of 6 is cleared when the next load signal is input.

[0051] In the normal mode in which the control terminal G is enabled, the decoder 33 outputs ADR24, ADR
This circuit outputs a signal to one of the output terminals a to d according to the value of 23. As a result, and gate 37-40
For example, a signal "0" is output from one of them, and one type of enable signal is output in one access cycle.

That is, in the normal mode, the bit data of address data ADR24 and ADR23 is "00", "01", "10", or "11".
4 types of enable signals depending on the

[0053]OE00,

[0054]OE01,

[0055]OE02,

Switching of OE03 is performed. In the pair mode in which the control terminal G is enabled, the decoder 34 outputs the ADR 24 and the output O0 of the address counter 36.
This circuit outputs a signal to one of the output terminals a to d based on the following.

For example, when ADR24 is "0", when output O0 of address counter 36 is "0", output a of decoder 34 becomes "0", and AND gate 37
enable signal from

OE00 is output. Further, when the output O0 of the address counter is "1", the output b of the decoder 34 becomes "0", and the enable signal is sent from the AND gate 38.

OE01 is output. On the other hand, ADR2
4 is "1", the output c of the decoder 34 is "0" when the output O0 of the address counter 36 is "0".
Then, the enable signal is output from the AND gate 39.

OE02 is output. Also, when the output O0 of the address counter 36 is "1", the decoder 34
The output d of becomes "0", and the enable signal is output from the AND gate 40.

OE03 is output. This allows two enable signals in one access cycle.

0062
]OE00,

OE01 or enable signal

[0064]
OE02,

OE03 is output continuously in synchronization with the clock signal, and the two ROMs can be accessed at high speed by these signals. FIG. 5(B) shows an example of the configuration of a ROM in which pair mode access is performed.

In this case, since the whole consists of eight ROMs, ROM00 has the address "2000 00
00", the data of the address advanced by 8 addresses is stored, and ROM01 contains data of "2000 0001".
'', the data of the address advanced by 8 addresses is stored. Thereafter, other ROMs 02 to 07 also store data at addresses advanced by 8 addresses.

When pair mode access is performed to the ROM configured as shown in FIG. 5(B), the first enable signal output from the access switching circuit

[0068] By OE00, ROM00, ROM01
, ROM02, and ROM03 are accessed simultaneously. As a result, for example, addresses "2000 000" to "
2000 0003'' data is output to the data bus. Here, the four ROMs being accessed simultaneously are four ROMs each having a data width of 8 bits.
This is because it represents 32-bit data.

Then, at the next rising edge of the clock signal, the enable signal is

[0070] When OE01 is output, ROM04, R
Four ROMs, OM05, ROM06, and ROM07, are accessed at the same time, and the address is "2000 0004".
~Data of "2000 0007" is output to the data bus. Below is the enable signal

0071 OE00
,

[0072] Every time OE01 is output, ROM00~R
Four ROMs OM03 and four ROMs ROM04 to ROM07 are accessed, and two sets of ROMs are accessed consecutively in one access cycle.

Returning to FIG. 2, the decoder 35 connects the control terminal G
This circuit outputs a signal to one of the output terminals a to d based on the outputs O0 and O1 of the address counter 36 in the burst mode in which the address counter 36 is enabled.

The operation of the access switching circuit in burst mode will now be explained with reference to the operation time chart of FIG. When the load signal is input, the address counter 36 is reset to the initial state. When the signal EN is input in this state (FIG. 4), the outputs O1 and O0 of the address counter 36 become "00". When the output of the counter 36 becomes "00", the output a of the decoder 35 becomes "0".
”, and the enable signal is output from the AND gate 37.

00
75] OE00 is output (Fig. 4 ■). Then, when the address counter 36 counts up at the next rising edge of the clock signal CLK, its outputs O1, O0
becomes "01". The value of address counter 36 is “0”
1”, the output b of the decoder 35 becomes “0”,
Enable signal from AND gate 38

OE01 is output (FIG. 4). Similarly, when the address counter 36 counts up at the next rising edge of the clock signal CLK, its output O1
, O0 becomes "10". When the value of the address counter 36 becomes "10", the output c of the decoder 35 becomes "0", and the enable signal is sent from the AND gate 39.

OE02 is output (FIG. 4). Similarly, the address counter 36 counts up at the next rising edge of the clock signal CLK, and its outputs O1, O
0 becomes "11". In this state, the output d of the decoder 35 becomes "0", and the enable signal is sent from the AND gate 40.

OE03 is output. FIG. 6 is a diagram showing an example of the configuration of a ROM to which burst mode access is performed. In this case, since the entire system is composed of 16 ROMs, each ROM stores data at addresses advanced by 16 addresses. For example, R
Data at address "4000 0010" is stored next to address "4000 0000" of OM00. Similarly, ROM01 address “4000 0
001”, followed by the address “4000 0011”
data is stored.

When burst mode access is performed to the ROM in FIG. 6, the enable signal first output from the access switching circuit

[0080] By OE00, ROM00 to ROM03
4 ROMs are accessed at the same time, for example, addresses "4000 0000" to "4000 0003"
data is output onto the data bus.

Enable signal output at the rising edge of the second clock signal

Four ROMs, ROM04 to ROM07, are accessed simultaneously by OE01, and for example, the address "
Data from 4000 0004 to 4000 0007 are output onto the data bus.

Enable signal output at the rising edge of the third clock signal

Four ROMs, ROM08 to ROM11, are accessed simultaneously by OE02, and for example, the address "
Data from 4000 0008 to 4000 000B are output onto the data bus.

Enable signal output at the rising edge of the fourth clock signal

[0086] ROM12 to ROM15 are accessed simultaneously by OE03, and for example, the address "4000 00
Data from "0C" to "4000 000F" is output to the data bus.

In this way, in burst mode, 1
By continuously outputting four enable signals in one access cycle in synchronization with the clock signal, four (
In this case, four sets of 16 ROMs can be accessed at high speed.

As described above, in the above embodiment, since a plurality of access modes having different access speeds such as normal mode, pair mode, and burst mode are switched by address, the switch section 11 etc. is used to switch between these modes. There is no need to provide an external device, and the circuit configuration becomes simpler. Further, when the access switching circuit is configured with one or more LSIs, there is no need to input a signal for switching the access mode from the outside, so the number of pins of the LSI can be reduced accordingly.

[0089] The access switching circuit of the present invention is
The present invention is not limited to the circuits such as the address latch 32, address counter 36, decoders 31, 33, etc. shown in the embodiment, but can also be realized by circuits having other configurations.

For example, a plurality of address registers may be provided to store addresses to be assigned to normal mode, pair mode, and burst mode, and the address stored in the address register and the address output from the microprocessor may be compared. It is also possible to determine in which address range stored in the address register the address output from the microprocessor falls, and to switch to an access mode corresponding to the address range.

In this case, since the user can arbitrarily rewrite the addresses assigned to each access mode, the configuration of the ROM can be changed more freely.

[0092]

According to the present invention, there is no need for a switch circuit for switching access modes, so the circuit configuration can be simplified and the number of signal lines input from the outside to the access switching circuit can be reduced. Particularly, when the access switching circuit is configured with one or more LSIs, the number of signal lines input to the circuit can be reduced to reduce the number of LSI pins.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit configuration diagram of a ROM access switching circuit according to an embodiment.

FIG. 3 is an explanatory diagram of address ranges assigned to each access mode.

FIG. 4 is an operation time chart in burst mode.

FIG. 5A is a diagram showing an example of a ROM configuration in a normal mode, and FIG. 5B is a diagram showing an example of a ROM configuration in a pair mode.

FIG. 6 is a diagram showing an example of the configuration of a ROM in burst mode.

FIG. 7 is a circuit configuration diagram of a conventional ROM access switching circuit.

[Explanation of symbols]

1 Mode selection means 2 Access switching means

Claims (2)

[Claims] Claims: 1. When predetermined address ranges are assigned to each of a plurality of memory access modes, it is determined in which address range assigned to each of the modes a read address is located, and one of the plurality of access modes is determined. mode selection means (1) for selecting one access mode;
Access switching means (2) for outputting an enable signal for sequentially accessing one or more memories corresponding to the access mode selected by the mode selection means (1)
An access control method comprising: 2. When a predetermined address range is allocated to each of a mode in which one memory is accessed in at least one access cycle and a mode in which two or more memories are accessed, the mode selection means (
1) comprises a first decoder that decodes a read address and outputs a mode selection signal for selecting an access mode corresponding to the read address; a signal enabled by a mode selection signal and incremented in synchronization with at least a clock signal;
2. A second decoder that decodes a read address and outputs an enable signal for sequentially accessing one or more memories corresponding to the access mode selected by the first decoder. Access control method described.