JPH01102661A - Bank control system for memory - Google Patents

Abstract

PURPOSE:To minimize the increase of capacity of a memory part and at the same time to increase the multiplex degree of the bank interleaves by dividing a memory into plural different memory areas for bank interleave numbers for execution of the interleave control. CONSTITUTION:A bank retrieving part 2 can set and retrieve the interleave numbers which are allocated to the memory areas of a memory part 1 for each minimum bank constitution unit (minimum extension unit) of the part 1 and based on the capacity of the part 1. These interleave numbers are retrieved by the access addresses received from a storage control unit SCU for acquisition of the interleave numbers forming the memory areas. Based on the value of said interleave numbers, the address, the timing and the control of a data transfer control part 4 to the part 1. Thus the part 1 is divided into plural address areas of different bank numbers. These address areas can be controlled with different interleave numbers. Thus the transfer is possible successively to the higher ranks from an area having a memory constitution that can move to the higher rank interleaves. In such a constitution, the increase of the capacity and the minimum capacity of the part 1 are minimized and also the multiplex degree of interleaves is increased for improvement of the performance.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a bank control method for a storage device, and is particularly suitable for minimizing the expansion capacity of a storage unit and maximizing the multiplicity of bank interleaving. This invention relates to a bank control method for a storage device.

[Conventional technology]

Conventionally, when determining the number of bank interleave for a storage device,
The number of interleaves is selected depending on the system configuration, and in that system configuration, the number of bank interleaves is constant.

Incidentally, a related bank control method of this type includes, for example, Japanese Patent Laid-Open No. 56-4853.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, when the multiplicity of interleaving is increased to improve performance, the number of banks to be interleaved is large, so there is a problem that the storage section needs to be expanded and the minimum capacity becomes large. In addition, if you increase the number of storage units and reduce the minimum capacity to limit the multiplicity of interleaving, even if the storage configuration allows interleaving at a higher level due to expansion, it may be necessary to change the system configuration in order to limit the capacity for subsequent expansion. There was a problem in that it was not possible to move to upper interleaving.

An object of the present invention is to divide the inside of a storage unit into a plurality of address areas with different numbers of banks, so that each can be controlled with a different number of interleaves, and to sequentially move to an upper level from a part of the memory structure that can move to a higher level interleave. It is an object of the present invention to provide a bank control system for a storage device that can minimize expansion and minimum capacity, and increase the multiplicity of interleaving as much as possible to improve performance.

[Means for solving problems]

The above purpose is for each minimum bank constituent unit (minimum expansion unit) of the storage unit, according to the storage capacity of the storage unit.

A bank search unit is provided that can set and search the number of interleaves to be allocated to the storage area, and this is searched by the access address from the storage control device to find the number of interleaves that the storage area is configured with. This is achieved by switching the address, timing, and control of the data transfer control unit.

[For production]

The bank search section has interleave information in the minimum bank configuration unit, so there is only one minimum bank configuration.

Or you can instruct to interleave multiple.

For example, if the minimum bank configuration is three sets, it can be divided into two storage parts to be interleaved and one set to be interleaved. If the number of interleaves differs, the address, timing, and data transfer control for the storage section will differ, but by switching these control operations depending on the number of interleave banks specified by the bank search section,
The inside of the storage section can be divided into a plurality of storage sections with different numbers of banks, and each section can be controlled with a different number of interleaves.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a storage section, 2 is a bank search section, 3 is an address control section, 4 is a data transfer control section, and 5 is a timing control section.

The storage unit 1 can be equipped with multiple sets of storage units (CDs), which are the minimum bank configuration unit (minimum expansion unit), but in this embodiment, it is assumed that a maximum of 8 sets of CD4 to CD5 can be installed, and one memory Parts (CD) are 8 banks (8 ways)
It is assumed to be 16MB. Furthermore, the number of bank interleaves that can be controlled is 8, 16, and 32 ways, the unit of data transfer with the storage control unit (SICU) is 256 bytes, and the data width of each bank is 8 bytes.

The bank search unit 2 includes search information registers 21-0 to 21-7.
and a selector 22, and search information registers 21-0 to 21-2.
1-7 are storage parts CD0-CD7 in the storage unit 1, respectively.
It corresponds to This search information register 21-0 to 21
-7, the number of interleaves to be used for each of the storage parts CD0 to CD7 in the storage unit 1 is coded and set in advance according to the desired storage capacity. Selector 2 indicates the correspondence between the interleave numbers of the storage locations CDO to CD7 (the interleave numbers set in the search information registers 21-0 to 21-7).
2 selects one of the search information registers 21-0 to 21-7 using the upper three bits of the memory access address (ADR) and outputs the interleaving number data set in the register.

The operation of FIG. 1 will be explained below using an example in which the storage capacity is 112 Mbytes. In this case, CDONCD6 of storage unit 1
becomes effective, and as shown in Figure 2, CD4 to CD5 operate in 32 ways with addresses of 0 to 64 Mbytes, and similarly CD4
~CD5 is 16 ways and operates with addresses of 64 to 96 Mbytes, and CD6 is 8 ways and operates with addresses of 96 to 112 Mbytes. Therefore, the number of interleaves (the number of ways) is stored in the search information registers 21-0 to 21-3 of the bank search unit 2.
Similarly, the number of interleaves is set to 16 in the search information registers 21-4 and 21-5, and the number of interleaves is 8 in the search information register 21-6.
1-7 shall not be used.

The memory access address from the storage control bag [(SCU) is given by 24 bits (ADRO~23), and the upper 3 bits (ADRO~2) are used to search the bank search unit 2 and search information registers 21-0~ 21-7 (although in this example, register 21-7 is not selected), the number of interleaves (number of ways) of the storage area operating at the address is determined. The interleave number found by the bank search section 2 is given to the address control section 3 and timing control section 5.

The address control unit 3 determines the memory access address ADR based on the interleaving number given by the bank search unit 2.
0 to 23 as the storage unit selection address (CD
A) Separate into memory configuration unit address (RAMA) and bank address (BKA). FIG. 3 shows the correspondence between the number of interleaves and the bit configurations of ODA, RAMA, and BKA. The storage unit selection address (ODA) is decoded in the address control unit 3 according to FIG. is sent to the storage unit 1 and used to select storage units to be interleaved in the storage locations CDO to CD7. That is, one storage location in the case of 8-way interleaving, two in the case of 16-way interleaving, and four storage locations in the case of 32-way interleaving are each assigned a storage unit selection address (ODA).
) is selected as shown in FIG. 4 according to the bit configuration. The memory unit address (RAMA) is also sent to the memory unit 1 and used to access the corresponding memory area within the selected memory location. The bank address (BKA) is sent to the data transfer control section 4 together with storage site selection signals 5ELCDO-7 to control the data transfer order.

On the other hand, the timing control unit 5 receives a request (
REQ) and the number of interleaves given from the bank search unit 2, the control timing (RAMT) and selection 'timing (SELT) for the storage unit 1 and data transfer control unit 4 are determined.
) In this embodiment, the unit of data transfer with the SCU is 256 bytes, and the data width of each bank (one way) is 8 bytes. Therefore, in the timing control section 5, in the case of 8-way interleaving, one access is 8 bytes x 8 banks; 64 bytes, so the storage section 2
The control timing (RAMT) to 1 is generated to access 8 banks 4 times, and 8 bytes x 8
Bank x 4 accesses = 256 bytes of data transfer. Similarly, in the case of 16-way interleaving, 8 bytes x 16 banks x 2 accesses, and in the case of 32 ways, 8
Generate control timing (RAMT) for accessing 32 banks x 1 time. The same applies to the selection timing (SELT) to the data transfer control unit 4.

The data transfer control unit 4 receives 5ELC from the address control unit 3.
Controls the data transfer path and transfer order between the accessed storage configuration unit and the SCU using the DO~7 and BKA signals and the selection timing (SELT) from the timing control unit 5.

Although the case where the storage capacity is 112 Mbytes has been described above, the operation is exactly the same in other cases as well, with the only difference being the interleave configuration and addressing.

Furthermore, in this embodiment, the storage capacity and interleave configuration are the same as those of the second I! Although the combination shown in 4 is used, other combinations are also possible without being limited to this.

- As an example, it is also possible to operate all 128 Mbytes in 8 ways.

〔Effect of the invention〕

As is clear from the above description, one aspect of the present invention is as follows.

Since it is possible to divide parts from parts where upper interleave configuration is possible and move to upper interleave sequentially, even if the storage expansion unit is the minimum bank configuration unit, it is possible to increase the multiplicity of interleaving as the storage capacity increases, which is extremely efficient. This has the effect of allowing detailed storage expansion units to be set and providing storage capacity with high throughput.

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a diagram showing an example of correspondence between storage capacity and interleave configuration, and Figure 3 is a diagram showing the number of interleaves and storage unit. FIG. 4 is a diagram showing an example of correspondence between physical addresses, and FIG. 4 is a diagram showing an example of correspondence between the number of interleaves and a storage unit selection address.

1... Storage section, 2... Bank search section, 21-O~
21-7...Search information register, CD0-CD7...
・Storage configuration unit, 3...Address control unit, 4...Data transfer control unit.

5...timing control section.

Figure 1 To 5CIJ From SCU

Claims (1)

[Claims] (1) In a storage device equipped with multiple banks, for each minimum bank configuration unit, set the number of interleave to be allocated to the storage area according to the storage capacity, and calculate the number of bank interleave that constitutes the storage area using the memory access address. and a means for switching bank interleaving control according to the determined bank interleaving number, and interleaving control is performed by dividing the storage device into a plurality of storage parts having different bank interleaving numbers. Bank control method.