JPH07130957A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To accurately perform a self-diagnosis for detecting failure in an integrated circuit forming part under a real using condition without requiring a dedicated test circuit, etc., that itself constitutes an integrated circuit and that is included in the integrated circuit forming part. CONSTITUTION:An integrated circuit forming part 13 is connected to an input buffer part 18, and a voltage level at an input end of the part 13 is kept at a low level, and an output buffer part 19 is under high impedance condition. Further, a MOS.FET 24 controls a condition that a power source voltage supply terminal 20 is connected to a power source line 12 in an integrated circuit forming part 13. This embodiment comprises a control voltage supply terminal 22 to which a control voltage is supplied so that the MOS.FET 24 is kept under a break condition; and a diagnosing circuit part 25 for supplying a power source voltage to a power source line 12 in an integrated circuit forming part 13 under supply of the control voltage and diagnosing failure in the integrated circuit forming part 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention includes an integrated circuit forming portion provided on a substrate such as a semiconductor substrate and is capable of performing self-diagnosis for detecting a failure such as a short circuit or disconnection in the integrated circuit forming portion. The present invention relates to a possible integrated circuit device.

[0002]

2. Description of the Related Art An integrated circuit device having an integrated circuit forming section having a plurality of semiconductor circuit elements on one semiconductor substrate and having a plurality of input / output terminals is not suitable for practical use. It is desired that after being incorporated into a circuit board that constitutes an electronic device to be provided, a self-diagnosis for detecting a failure such as a short circuit or a disconnection in the integrated circuit formation portion can be performed. . Therefore, conventionally, it has been proposed that the integrated circuit device is configured such that the integrated circuit forming portion formed on the semiconductor substrate provided therein has a built-in dedicated test circuit for self-diagnosis.

The dedicated test circuit built in the integrated circuit forming portion of such an integrated circuit device for its self-diagnosis is such that the integrated circuit device is actually in use, and accordingly, another circuit device or circuit is used. It is operated only when verifying the function of the integrated circuit forming part under the condition that the elements, power supply part, grounding part, etc. are connected, and when the integrated circuit forming part performs the original operation, the operation is performed. Be in a non-operational state regardless of

[0004]

In the integrated circuit device provided with the integrated circuit forming section containing the dedicated test circuit for self-diagnosis as described above, the dedicated test circuit is placed in an actual use state. In order to be able to verify the function of the integrated circuit forming unit, it is possible to verify the function of the integrated circuit forming unit in addition to the operation for causing the integrated circuit forming unit to take some preset operating states. However, the operation is performed so as not to be affected by other circuit devices or circuit elements connected to the integrated circuit forming portion. Therefore, the dedicated test circuit itself constitutes an integrated circuit having a relatively large scale, and accordingly, the entire integrated circuit forming section including the dedicated test circuit is extremely complicated because the integrated scale is further increased. As a result, there is a concern that an integrated circuit device including the integrated circuit forming part may reduce the manufacturing yield and the manufacturing cost may increase. is there.

In view of such a point, the present invention comprises an integrated circuit forming portion provided on a substrate such as a semiconductor substrate, and is free from short circuit, disconnection, etc. in the integrated circuit forming portion under actual use conditions. It is possible to accurately perform self-diagnosis for detecting a failure without requiring a dedicated test circuit or the like which constitutes an integrated circuit having a relatively large scale and is included in the integrated circuit forming section. It is an object of the present invention to provide an integrated circuit device having such a structure.

[0006]

In order to achieve the above object, an integrated circuit device according to the present invention has an integrated circuit forming portion provided on a base body, and an input end and an output end of the integrated circuit forming portion. An input buffer section and an output buffer section which are respectively connected to the input connection terminal and the output connection terminal provided above, and a conduction state and a power supply which connect the power supply voltage supply terminal provided on the substrate to the power supply line in the integrated circuit forming section. A switching unit that selectively takes a cutoff state in which the voltage supply terminal is separated from the power supply line in the integrated circuit formation unit, and a diagnostic circuit unit provided between the power supply voltage supply terminal and the power supply line in the integrated circuit formation unit, An input buffer unit, an output buffer unit, and a control voltage supply terminal connected to the switching unit are provided on the base body, and the input voltage buffer terminal is connected to the input buffer unit. The voltage level at the input terminal of the integrated circuit forming part connected to the output part is maintained at a predetermined low level or high level, the output buffer part is set to the high impedance state, and the switching part is set to the cutoff state. When the control voltage is supplied, the power supply voltage is supplied to the power supply line in the integrated circuit forming unit through the diagnostic circuit unit, the integrated circuit forming unit is diagnosed, and the diagnostic result output is obtained from the diagnostic circuit unit. It is supposed to be.

[0007]

In the integrated circuit device according to the present invention configured as described above, the self-diagnosis for detecting a failure such as a short circuit or a disconnection in the integrated circuit forming section is performed in the integrated circuit forming section through the diagnostic circuit section. By supplying the power supply voltage to the power supply line, it is assumed that the diagnostic result output corresponding to the failure in the integrated circuit forming unit is obtained from the diagnostic circuit unit. When a self-diagnosis is performed on the integrated circuit forming unit, a state in which a predetermined control voltage is supplied to the control voltage supply terminal is set, whereby the input buffer unit is connected to the integrated circuit forming unit. The voltage level at the input terminal of the unit is maintained at a predetermined low level or high level, the output buffer unit is set to the high impedance state, and the switching unit is set to the cutoff state. The input terminal and the output terminal of the circuit forming unit are placed in a state in which substantially no input / output of signals is performed, and the power supply line of the integrated circuit forming unit is disconnected from the power supply voltage supply terminal. The self-diagnosis is not affected by other circuit devices or circuit elements connected to the integrated circuit forming unit.

The self-diagnosis of the integrated circuit forming unit under such a condition is such that the input terminal and the output terminal of the integrated circuit forming unit are in a state in which substantially no signal is input and output, and the power line is If a failure occurs after being disconnected from the power supply voltage supply terminal, the effect is that the power supply voltage is supplied to the power supply line of the integrated circuit formation unit. This is done in view of the fact that the current flowing through the line is increased or decreased. That is, in the diagnostic circuit unit, for example, the current flowing through the power supply line of such an integrated circuit forming unit is detected, and the diagnostic result output is formed according to the level of the detected current.

By doing so, the self-diagnosis for detecting the failure of the integrated circuit forming portion under the actual use condition constitutes an integrated circuit having a relatively large scale. Without the need for a dedicated test circuit or the like included in the integrated circuit forming unit,
It is performed accurately while being unaffected by other circuit devices or circuit elements connected to the integrated circuit forming unit. Therefore, the integrated circuit device according to the present invention is a self-detecting device for detecting a failure of the integrated circuit forming part under the actual usage condition, while the complexity of the structure is limited to a small range. Diagnosis will be made appropriately.

[0010]

FIG. 1 shows an example of an integrated circuit device according to the present invention. In the example shown in FIG. 1, an integrated circuit forming portion 13 having a power supply line 12 is provided on a semiconductor substrate 11. This integrated circuit forming unit 13
The power supply line 12 is configured to include a large number of semiconductor circuit elements formed on the semiconductor substrate 11, and the power supply line 12 is used for supplying an operating power supply voltage to the large number of semiconductor circuit elements. The integrated circuit forming unit 13 includes a plurality of signal input terminals 14
a, 14b, 14c and 14d are provided,
A plurality of signal output terminals 15a, 15b, 15c, ..., 1
5d, 15e, 15f, ..., And 15g are provided.

The semiconductor substrate 11 has an integrated circuit forming portion 13
In addition, input connection terminals 16a, 16b, 16c and 16d are formed in an array at the edge portion outside the integrated circuit formation portion 13, and a plurality of output connection terminals 17 are provided.
a, 17b, 17c, ..., 17d, 17e, 17
f, ..., 17g and 17t are arrayed.
Then, the input connection terminal 16 on the semiconductor substrate 11
a and 16b and the plurality of signal input terminals 14a and 14b in the integrated circuit formation part 13 between the input connection terminal 16
An input buffer section 18 is provided for connecting a to the signal input terminal 14a and to the input connection terminal 16b to the signal input terminal 14b, and the input connection terminals 16c and 16d.
And a plurality of signal input terminals 14c in the integrated circuit forming unit 13
And 14d, the input connection terminal 16c is connected to the signal input end 14c, and the input connection terminal 16d is connected to the signal input end 1.
An input buffer unit 18 connected to each of 4d is provided. Further, in the semiconductor substrate 11, the plurality of signal output terminals 15a, 15b, 15 in the integrated circuit forming portion 13 are provided.
and 15d and output connection terminals 17a, 17b,
The signal output terminal 15 is provided between the terminals 17c, ... And 17d.
a to the output connection terminal 17a, the signal output end 15b to the output connection terminal 17b, and the signal output end 15c to the output connection terminal 17
., and an output buffer unit 19 that connects the signal output end 15d to the output connection terminal 17d, respectively, and a plurality of signal output ends 15e, 15f, ... In the integrated circuit forming unit 13. .. and 15g and the output connection terminals 17e, 17f, ..., and 17g between the signal output terminal 15e and the output connection terminal 17e.
To the output connection terminal 17f, ... And the signal output terminal 1
An output buffer unit 19 is provided to connect 5g to the output connection terminals 17g, respectively.

A power supply voltage supply terminal 20, a diagnostic power supply voltage supply terminal 21, and a control voltage supply terminal 22 are also formed on the edge portion of the semiconductor substrate 11. Further, the semiconductor substrate 11 has a conductive state in which the power supply voltage supply terminal 20 is connected to the power supply line 12 in the integrated circuit forming unit 13 and a disconnected state in which the power supply voltage supply terminal 20 is disconnected from the power supply line 12 in the integrated circuit forming unit 13. A MOS field effect transistor (M
OS • FET) 24, the power supply voltage supply terminal 20, the diagnosis power supply voltage supply terminal 21, and the output connection terminal 17t, and the diagnostic circuit section 25 arranged between the power supply line 12 in the integrated circuit forming section 13. Is provided. MOS
The drain and source of the FET 24 are connected to the power supply voltage supply terminal 20 and the power supply line 12 in the integrated circuit formation unit 13, respectively. Further, on the semiconductor substrate 11, the control voltage supply terminal 22 is connected through the connection line 26 to the respective control ends of the plurality of input buffer units 18, the respective control ends of the plurality of output buffer units 19, and the MOS.
-It is connected to the gate of FET24.

Under the above circumstances, when the integrated circuit forming section 13 is to be used for actual use, the input connection terminals 16a to 16d and the output connection terminals 17a to 17g are external circuit devices or circuits, respectively. It is connected to an element or the like. Then, under such a condition, when the integrated circuit forming unit 13 is operated to perform the original function, the power supply voltage VO is supplied to the power supply voltage supply terminal 20, and further, to the control voltage supply terminal 22, for example, , A control voltage VCH having a high level is supplied. As a result, each of the plurality of input buffer units 18 and the plurality of output buffer units 19 is placed in a normal operating state by the high-level control voltage VCH from the control voltage supply terminal 22 supplied to its control terminal. Further, the MOS • FET 24 is rendered conductive by supplying the control voltage VCH having a high level from the control voltage supply terminal 22 to the gate.
Then, the integrated circuit forming unit 13 supplies the power supply line 12 with the power supply voltage VO from the power supply voltage supply terminal 20 through the MOS.F.
When it is supplied through the ET 24, it operates to perform its original function.

On the other hand, when the integrated circuit forming unit 13 is supposed to be used for actual use and self-diagnosis for detecting a failure such as a short circuit in the integrated circuit forming unit 13 is performed, the power supply voltage is supplied. When the power supply voltage VO is supplied to the terminal 20, the control voltage supply terminal 22 is supplied with the control voltage VCL having a low level, and the diagnosis power supply voltage VT is supplied with the diagnosis power supply voltage VT. Supplied. Under such circumstances, each of the plurality of input buffer units 18 has its output end connected by the control voltage VCL having a low level from the control voltage supply terminal 22 supplied to the control end thereof, forming an integrated circuit. Signal input end 14a of the section 13
Corresponding ones of the output buffer units 19 to 14d are maintained at a predetermined low level or high level, and each of the plurality of output buffer units 19 is connected to the control voltage supply terminal 22 supplied to its control end. The control voltage VCL that takes a low level keeps the high impedance state in which the impedance seen from the output end is extremely high. Further, the MOS • FET 24 makes the low level from the control voltage supply terminal 22. Control voltage VCL
Is supplied to the gate so that the gate is cut off.

As described above, when the control voltage VCL having a low level is supplied to the control voltage supply terminal 22, each of the signal input terminals 14a to 14d of the integrated circuit forming section 13 and the output connection terminal 17a. Each of 17 to 17 g is maintained in a state in which substantial signal input / output is not performed, and the power supply line 12 of the integrated circuit forming unit 13 is MO.
It is disconnected from the power supply voltage supply terminal 22 by the S-FET 24. Thereby, the integrated circuit forming unit 1
The self-diagnosis about 3 is the input connection terminals 16a to 16d.
And the output connection terminals 17a to 17g are not affected by an external circuit device or a circuit element to which the output connection terminals 17a to 17g are connected.

The power source voltage supply terminal 20 and the diagnostic power source voltage supply terminal 21 are connected to each other. Therefore, the power source voltage VO from the power source voltage supply terminal 20 and the diagnostic power source voltage VT from the diagnostic power source voltage supply terminal 21 are connected. The supplied diagnostic circuit section 25 is provided with two MOS • FETs 31 and 32 forming the current mirror circuit 30. The MOS-FET 31 is configured such that its drain and gate are commonly connected to the power supply voltage supply terminal 20, and its source is connected to the power supply line 12 of the integrated circuit forming portion 13. Moreover, the MOS • FET 32 is
The drain is connected to the diagnostic power supply voltage supply terminal 2 via the resistor 33.
1 is connected, the source is connected to the power supply line 12 of the integrated circuit forming portion 13, and the gate is a MOS • FET 31.
Is connected to the gate.

As a result, the power supply voltage VO supplied to the power supply voltage supply terminal 20 and the diagnostic power supply voltage VT supplied to the diagnostic power supply voltage supply terminal 21 pass through the current mirror circuit 30 and the power supply line of the integrated circuit forming unit 13. 12, the current IT based on the power supply voltage VO supplied to the power supply voltage supply terminal 20 is supplied to the MOS.FET.
A current IT ′ based on the diagnostic power supply voltage VT supplied to the diagnostic power supply voltage supply terminal 21 flows into the power supply line 12 of the integrated circuit forming portion 13 through the MOS.
It is assumed that the resistor 33 has a level having a fixed ratio relationship with the level of the current IT passing through the FET 31.
And the MOS • FET 32 to flow into the power supply line 12 of the integrated circuit formation portion 13. And in this way,
The voltage VP corresponding to the level of the current IT ′ obtained at the connection point P between the resistor 33 and the MOS • FET 32 by flowing the current IT ′ through the resistance 33 and the MOS • FET 32 is a comparison terminal in the level comparison unit 34. Is supplied to.

The reference terminal of the level comparing section 34 is
A reference voltage VR having a preset reference level is supplied from the reference voltage source 35. And the level comparison unit 3
4, the level comparison between the voltage VP and the reference voltage VR is performed, and when the level of the voltage VP is less than the level of the reference voltage VR, the level comparison unit 34 takes the low level and the level of the voltage VP. Is higher than the level of the reference voltage VR, the comparative output voltage VX having a high level is obtained. In this case, the level of the reference voltage VR corresponds to the minimum value of the level of the voltage VP obtained at the connection point P under the normal condition that the integrated circuit forming unit 13 does not cause a failure such as a short circuit. It is set to be what you do. Therefore, when the integrated circuit forming unit 13 is in a normal state without causing a failure such as a short circuit, the level of the voltage VP is equal to the reference voltage VR.
As described above, the comparative output voltage VX having a high level is obtained from the level comparing section 34, and the integrated circuit forming section 13 is also provided.
However, if a failure such as a short circuit has occurred and it is not in a normal state, and the level of the current IT 'is increased due to this, the level of the voltage VP becomes less than the reference voltage VR, and the level comparison unit 34 The comparative output voltage VX having a low level is obtained, and the comparative output voltage VX is output as a diagnostic result.

Therefore, the diagnostic power supply voltage supply terminal 21 is provided by the portion including the current mirror circuit 30 and the resistor 33.
A current detection unit for detecting a current IT ′ flowing into the power supply line 12 of the integrated circuit formation unit 13 is formed. Further, a portion including the level comparison unit 34 and the reference voltage source 35 detects the current IT ′ by the current detection unit. That is, an output forming section is formed to send out the comparative output voltage VX corresponding to the level of the current IT ′ as the diagnosis result output.

The comparison output voltage VX obtained from the level comparing section 34 is held by the level holding section 36. The output terminal of the level holding section 36 is connected to the output connection terminal 17t via the output buffer section 19. At this time, the output buffer section 19 has its control terminal connected to the control voltage supply terminal 2t.
The control voltage VCL having a low level from 2 is supplied, and the signal is not sent to the output connection terminal 17t. The comparison output voltage VX obtained from the level comparison unit 34 is the level holding unit. In the state held by 36, no output is made to the output connection terminal 17t.

In this way, self-diagnosis is performed to detect a failure such as a short circuit in the integrated circuit forming portion 13 which is supposed to be actually used, and the diagnostic result output (comparative output voltage) obtained thereby is obtained. VX) is held by the level holding unit 36.

After the self-diagnosis of the integrated circuit forming unit 13 is performed, when the integrated circuit forming unit 13 is brought into a state where it is operated to perform its original function, the control voltage supply terminal 22 is set to a low level. The control voltage VCH having a high level is supplied in place of the control voltage VCL having the control voltage VCL, which causes the output buffer unit 19 connected to the output terminal of the level holding unit 36, together with other output buffer units 19, to control the control terminal VCH. The control voltage VCH having a high level is supplied from the control voltage supply terminal 22 to a normal operating state. As a result, the comparison output voltage VX, which is the diagnostic result output held by the level holding unit 36, is led to the output connection terminal 17t through the output buffer unit 19.

As described above, when the self-diagnosis of the integrated circuit forming unit 13 is being performed, the level holding unit 36 is provided.
When the output buffer unit 19 connected to the output terminal of the above is in a state in which the signal is not sent to the output connection terminal 17t, the comparison output voltage VX obtained as the diagnostic result output from the level comparison unit 34 becomes the level holding unit. After the self-diagnosis of the integrated circuit forming unit 13 is performed in the state of being held by the 36, the comparison output voltage VX, which is the diagnostic result output held by the level holding unit 36, is output to the output buffer unit 19. The self-diagnosis of the integrated circuit forming unit 13 is performed through the output connection terminal 17t through the external circuit device to which the input connection terminals 16a to 16d and the output connection terminals 17a to 17g are connected, respectively. The state that is performed without being affected by the circuit element or the like is reliably maintained.

FIG. 2 shows an example of a specific configuration of the input buffer section 18 described above. In the example shown in FIG. 2, one of the input connection terminals 16a to 16d is connected to one input terminal of the AND gate 41 via the inverter 40, and the other input terminal of the AND gate 41 is connected to the control voltage supply terminal. The output end of the AND gate 41 is connected to any one of the signal input ends 14a to 14d in the integrated circuit formation portion 13 while being connected to the signal line 22. Under the circumstances, the control voltage supply terminal 2 is connected to the other input terminal of the AND gate 41.
When the control voltage VCH having a high level from 2 is supplied, the input signal supplied to any of the input connection terminals 16a to 16d is the inverter 40 and the AND gate 4.
1, the signal input terminal 1 in the integrated circuit forming unit 13
It is supplied to any of 4a to 14d. Further, when the control voltage VCL having a low level is supplied from the control voltage supply terminal 22 to the other input terminal of the AND gate 41, the AND gate 41 is maintained in the off state, and the output terminal of the AND gate 41 is The voltage of any of the signal input terminals 14a to 14d in the connected integrated circuit forming unit 13 is
It is maintained at a predetermined low level or high level.

FIG. 3 shows an example of a specific configuration of the output buffer section 19 described above. In the example shown in FIG. 3, a pair of complementary MOS • FETs 42 and 43 are connected between the power supply line to which the power supply voltage VO is supplied and the ground potential point in a state where the drain-source paths of each are connected in series. Connected in between,
The output terminal of the NOR gate 44 is connected to the source of the MOS FET 42, and the output terminal of the NAND gate 45 is connected to the source of the MOS FET 43. Then, one of the signal output terminals 15a to 15g in the integrated circuit forming unit 13 is connected to one input terminal of each of the NOR gate 44 and the NAND gate 45, and the other input terminal of the NOR gate 44 is connected to the inverter 46. And the other input of the NAND gate 45 is directly connected to the control voltage supply terminal 22, respectively, and
A connection point between the MOS • FET 42 and the MOS • FET 43 is connected to any of the output connection terminals 17a to 17g.

Under this condition, the high level from the control voltage supply terminal 22 is applied to the other input terminal of the NOR gate 44 through the inverter 46 and directly to the other input terminal of the NAND gate 45. When the control voltage VCH is supplied, the MOS • FET 42 and the MOS • FET 43 are placed in a conductive state, and one input terminal of each of the NOR gate 44 and the NAND gate 45 is connected to the integrated circuit formation unit 13. The output signal obtained at any of the signal output terminals 15a to 15g is the MOS • FET 42 and the MOS • FE.
Output connection terminal 17a to which the connection point with T43 is connected
~ 17g. Also, via the inverter 46 to the other input terminal of the NOR gate 44,
When the control voltage VCL having a low level is directly supplied from the control voltage supply terminal 22 to the other input terminal of the NAND gate 45, the MOS.FET 42 and the MOS.FE.
T43 is placed in the cutoff state and the high impedance state is taken.

FIG. 4 shows another example of the integrated circuit device according to the present invention. The example shown in FIG. 4 is different from the example shown in FIG. 1 in the specific configuration of the diagnostic circuit section 25 and in that the diagnostic power supply voltage supply terminal 21 is not provided on the semiconductor substrate 11, The structure of the part is common to the example shown in FIG. 4, parts corresponding to the parts shown in FIG. 1 are shown with the same reference numerals as in FIG.

In the example shown in FIG. 4, the diagnostic circuit section 25 is connected in parallel to the drain-source of the MOS.FET 24 instead of the current mirror circuit used in the example shown in FIG. The resistor 37 is used. Further, in connection with the fact that the current mirror circuit is not used, the diagnostic power supply voltage supply terminal 21 used in the example shown in FIG. 1 is not used.
Under such a configuration, when the control voltage VCH having a high level is supplied to the control voltage supply terminal 22, the same operation as in the case of the example shown in FIG. 1 is performed. Further, when the control voltage VCL having a low level is supplied to the control voltage supply terminal 22 and the MOS • FET 24 is turned off, the power supply voltage VO supplied to the power supply voltage supply terminal 20 is supplied through the resistor 37 to the integrated circuit forming unit. 13 power lines 12
Is supplied to the integrated circuit forming section 13 from the power supply voltage supply terminal 20 through the resistor 37 to the power supply line 12 of the integrated circuit forming section 13. Self-diagnosis is performed.

At this time, the resistor 37 forms a current detecting section for detecting a current flowing from the power supply voltage supply terminal 20 to the power supply line 12 of the integrated circuit forming section 13, and also the level comparing section 34 and the reference voltage source 35. By the portion including, the output forming portion for sending out the comparison output voltage VX according to the level of the current detected by the current detecting portion as the diagnostic result output is formed, and the same operation as in the case of FIG. 1 is performed. Will be seen.

[0030]

As is apparent from the above description, in the integrated circuit device according to the present invention, the self-diagnosis for detecting a failure such as a short circuit or a disconnection in the integrated circuit forming portion is predetermined at the control voltage supply terminal. The control voltage of
As a result, the input buffer section maintains the voltage level of the input terminal of the integrated circuit forming section to which it is connected at a predetermined low level or high level, and the output buffer section assumes a high impedance state. Further, the switching section is assumed to be in the cutoff state, and the input terminal and the output terminal of the integrated circuit forming section are placed in a state in which substantially no signal is input / output, and the integrated circuit forming section is formed through the diagnostic circuit section. When the integrated circuit forming unit has a failure due to the supply of the power supply voltage to the power supply line in the integrated circuit forming unit, the influence of the failure is to supply a power supply voltage to the power supply line of the integrated circuit forming unit. Through the current flowing through the power supply line of the integrated circuit forming unit, and as a result, a diagnostic result output corresponding to a failure in the integrated circuit forming unit is obtained from the diagnostic circuit unit Is carried out is the thing. The self-diagnosis of the integrated circuit forming unit is not affected by other circuit devices or circuit elements connected to the integrated circuit forming unit.

Therefore, in the integrated circuit device according to the present invention, the self-diagnosis of the integrated circuit forming portion under actual usage conditions constitutes an integrated circuit having a relatively large scale. In this configuration, a dedicated test circuit included in the integrated circuit forming unit is not required and the complexity is limited to a small range. It is assumed that the operation is not affected by the circuit device, the circuit element, or the like, and is performed accurately.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an example of an integrated circuit device according to the present invention.

FIG. 2 is a schematic configuration diagram showing a specific configuration example of an input buffer unit in the integrated circuit device according to the present invention.

FIG. 3 is a schematic configuration diagram showing a specific configuration example of an output buffer section in the integrated circuit device according to the present invention.

FIG. 4 is a schematic configuration diagram showing another example of a semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

11 semiconductor substrate 12 power supply line 13 integrated circuit forming portion 14a, 14b, 14c, 14d signal input terminal 15a, 15b, 15c, 15d, 15e, 15f, 1
5g signal output terminal 16a, 16b, 16c, 16d input connection terminal 17a, 17b, 17c, 17d, 17e, 17f, 1
7g output connection terminal 18 input buffer section 19 output buffer section 20 power supply voltage supply terminal 21 diagnostic power supply voltage supply terminal 22 control voltage supply terminal 24, 31, 32 MOS • FET 25 diagnostic circuit section 26 connection line 30 current mirror circuit 33 , 37 resistance 34 level comparison unit 35 reference voltage source 36 level holding unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/66 F 7630-4M

Claims (4)

[Claims] 1. An integrated circuit forming part provided on a base, an input buffer part for connecting an input end of the integrated circuit forming part to an input connection terminal provided on the base, and an integrated circuit forming part of the integrated circuit forming part. An output buffer section having an output terminal connected to an output connection terminal provided on the base body, a conduction state connecting the power supply voltage supply terminal provided on the base body to a power supply line in the integrated circuit forming section, and the power supply voltage. A switching unit that selectively switches between a power supply line in the integrated circuit formation unit and a power supply line in the integrated circuit formation unit; and a diagnostic circuit unit provided between the power supply voltage supply terminal and the power supply line in the integrated circuit formation unit. And a control voltage supply terminal provided on the base and connected to the input buffer section, the output buffer section, and the switching section, the control voltage supply terminal In the input buffer unit, the voltage level of the input terminal of the integrated circuit forming unit connected to the input buffer unit is maintained at a predetermined low level or high level, and the output buffer unit is set to a high impedance state, Further, a power supply voltage is supplied to the power supply line in the integrated circuit forming unit through the diagnostic circuit unit while a control voltage for turning off the switching unit is supplied, and the diagnosis of the integrated circuit forming unit is performed. The integrated circuit device according to which the diagnosis result output is obtained from the diagnosis circuit unit. 2. A diagnostic circuit section for holding a diagnostic result output, and a diagnostic result output buffer section for coupling an output end of the output holding section to a diagnostic result output connection terminal provided on a substrate. The diagnostic result output buffer unit is maintained in a high impedance state by the control voltage when the control voltage is supplied to the control voltage supply terminal, and the control voltage is not supplied to the control voltage supply terminal. 2. The integrated circuit device according to claim 1, wherein the diagnostic result output held by the output holding unit is led out to the diagnostic result output connection terminal after the operation. 3. A diagnostic circuit section forms a diagnostic result output according to a current detecting section for detecting a current flowing into a power supply line in the integrated circuit forming section and a level of the current detected by the current detecting section. The integrated circuit device according to claim 1, further comprising an output forming unit. 4. The integrated circuit according to claim 3, wherein the current detection unit is formed to include a current mirror circuit arranged between the power supply voltage supply terminal and the power supply line in the integrated circuit formation unit. apparatus.