JP3036176B2 - Semiconductor integrated circuit with input pull-up circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input pull-up circuit incorporated in an integrated circuit, and more particularly to a semiconductor integrated circuit with an input pull-up circuit which can be used in the field of automobiles requiring a certain amount of source current to the outside. Circuit.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit with an input pull-up circuit, as shown in FIG. 5, a drain electrode (D) is connected between an input terminal (IN) 1 and a high-level reference potential (hereinafter referred to as VCC) line. And a source electrode (S), and a gate electrode (G) connected to a lower reference potential (hereinafter, referred to as VSS), for example, a ground potential. 4), and an internal circuit 5 is provided between the input terminal 1 and the output terminal (OUT) 2.

In the prior art shown in FIG. 7, a resistor 13 is used instead of a P-channel transistor.

Next, the operation will be described. When the external switch (SW) 10 in FIG. 5 is OFF, the integrated circuit (hereinafter referred to as I
C) is set to a high level by a pull-up transistor 4 built in the IC. At this time, a high level (output non-inverted) is output to the output terminal 2 of the IC. Then, when the external switch 10 is ON, the external switch 10, the external connector 9, since the IC input terminal 1 through an external resistor 8 (resistance value Re) is pulled down, the source current from the input terminal (i _s) is Flow out. I at this time
The voltage at the C input terminal 1 is determined by the voltage dividing ratio between the resistance value Re of the external resistor 8 and the resistance value R _ON of the ON resistance of the built-in pull-up transistor 4. In this case, as shown in FIG.
By setting the input voltage (threshold voltage) (V _IHL ) of the C internal circuit 5 to be equal to or higher than the input terminal voltage level (V _IN ) at this time, a low level is output to the output terminal. The relationship between V _IHL and V _IN when the external switch 10 is ON is expressed by the following equation (1).

[0005]

[0006]

In this conventional semiconductor integrated circuit with an input pull-up circuit, there is a problem when used in the field of automobiles or the like, which is grounded somewhere between the input terminal 1 of the IC and the external resistor 9. (GND) short between (most significant failure mode that leads to said system down colloquially dead short) (5 indicated by the dotted line 15) to the case, the source current of the normal time as shown in FIG. 6 (i _s) A very large short-circuit current ( _iss ) flows, and I
C is thermally destroyed and the system goes down. The external switch is ON / O until the system goes down.
There is a problem that malfunction continues regardless of FF.

[0007]

The feature of the present invention is that an external resistor is provided.
Connect a high-level or low-level signal
An input terminal for the power, the VCC line, a VSS line, the input
With an input pull-up circuit having a gate element connected between a terminal and the VCC and inputting a gate signal to a gate
In the semiconductor integrated circuit, the low level and the VSS
A circuit for generating a reference voltage which is a potential between the potentials, a first input terminal connected to the input terminal, a second input terminal for inputting the reference voltage, and an output terminal for outputting the gate signal; And a comparator ,
The comparator input to the first input terminal of the comparator;
Wherein the potential of the input terminal is input to the second end;
Output from the output terminal when it becomes lower than the reference voltage
The gate element is turned off by the gate signal
In the semiconductor integrated circuit with the input pull-up circuit.

The gate element is an insulated gate field effect transistor, for example, a P-channel type transistor,
Preferably, the gate is a gate electrode of the transistor.

Also, a pull-up resistor can be connected between the input terminal and the VCC in parallel with the gate element.

Further, a control signal from a control terminal is input between the gate and the output terminal of the comparator, and the output is transmitted to the comparator and the comparator.
An AND gate serving as a reset signal for an internal circuit which is a circuit other than the gate element can be provided.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is an equivalent circuit diagram of a semiconductor integrated circuit with an input pull-up circuit according to a first embodiment of the present invention. In FIG. 1, portions having the same or similar functions as those in FIG. 5 are denoted by the same reference numerals.

An input terminal 1, a VCC line, and a VSS (GN
D) line, output terminal 2, internal circuit 5 provided between input / output terminals 1 and 2, and resistor 6 between VCC line and VSS line.
A circuit for generating a reference potential (V _ref ) composed of a series body of a reference potential (V _ref ), a first input terminal (-) connected to the input terminal 1, and the reference potential (V
_ref ), and a comparator 3 having a second input terminal (+) for inputting a gate signal and an output terminal 14 for outputting a gate signal. This gate signal is a P-channel transistor 4
, And this gate signal line is also connected to the reset terminal (R) of the internal circuit 5.

Normally, the external switch (SW) 10
The potential (V) of the input terminal (IN) 1 of the IC according to N / OFF
_IN ) is the voltage range shown in FIG.

Here, the internal reference potential of the IC (V
_ref ) is the low level (V _IN ) at the input terminal 1 of the IC.
(L)) (the input terminal voltage when the external switch 10 is ON), the output of the comparator 3, ie, the gate signal is ON / OFF of the external switch.
Output a low level and pull-up P
The channel type transistor 4 is always on and performs a normal operation.

On the other hand, as indicated by a dotted line 15 in FIG. 5, a short circuit has occurred outside the input terminal 1 (for example, between the input terminal 1 and the external resistor 8) and with the ground line (GND). In this case, as shown in FIG.
(V _IN ) becomes equal to or lower than the reference potential (V _ref ), and the P-channel transistor 4 is turned off. Accordingly, the current i _s as shown in FIG. 2 (b) from the immediately zero (0) only the i _ss instantaneously, IC
This IC is an external switch ON / OFF until the system goes down or the system goes down due to thermal destruction.
Inconvenient accidents such as continuing to malfunction irrespective of the situation are eliminated.

Further, the inverted output of the comparator 14 when the short circuit occurs is input to the reset terminal (R), and the internal circuit 5 is also initialized.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 3, portions having the same or similar functions as those in FIG. 1 are denoted by the same reference numerals.

In the second embodiment, the input terminal 1 of the IC and the VC
A high pull-up resistor 11 (about 50 times the _ON resistance R _ON of the P-channel transistor 4, that is, about 100 KΩ) is connected in parallel with the P-channel transistor 4 between C and C.

This is due to the fact that when the normal state is restored after the occurrence of the abnormality, P
The pull-up resistor for returning the channel transistor 4 to normal immediately has a function of returning the output of the comparator 3 to the normal low level.

Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 4, portions having the same or similar functions as those in FIG. 1 are denoted by the same reference numerals.

In the IC according to the third embodiment, a separate control terminal 16 is provided, and is connected to the P-channel type and the gate G of the transistor via the AND gate 12 which receives the signal and the output of the comparator 3 as inputs. . This allows the control terminal to be at a high level during abnormal conditions → normal operation →
The IC can return to a normal state by setting it to the low level. Further, in this embodiment, when the control terminal is set to the low level at the time of selecting and inspecting the IC, leak measurement of the input terminal can be performed.

[0022]

As described above, the present invention has a fail-safe function capable of shutting down the system safely on the occurrence of a short mode failure with respect to GND, which is regarded as the most important in the field of automobiles.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing respective voltage relationships between a normal state and an abnormal state of a system using the present invention.

FIG. 3 is an equivalent circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram showing a third embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing a conventional technique.

FIG. 6 is a diagram showing a relationship between a source current and an input terminal potential when an external switch is turned ON / OFF and when an abnormality occurs.

FIG. 7 is an equivalent circuit diagram showing a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal (IN) 2 Output terminal (OUT) 3 Comparator 4 P-channel transistor 5 Internal circuit 6, 7 Reference resistance 8 External series resistance 9 External connector 10 External switch 11 High resistance for pull-up 12 AND gate 13 Pull-up resistance 14 Output terminal of comparator 15 Undesired short-circuit between input line and GND 16 Control terminal

Claims (5)

(57) [Claims] An external resistor is connected to a high level or
An input terminal for inputting a low-level signal , a higher reference potential line, a lower reference potential line, and a gate element connected between the input terminal and the higher reference potential line for inputting a gate signal to a gate; With input pull-up circuit
In the body an integrated circuit, the potential between the said low low-side reference potential line potential
Comprising a comparator having a circuit for generating a reference voltage is, an output terminal for outputting the gate signal and a second input for the first input terminal for inputting the reference voltage to be connected to said input terminal , Which is input to the first input terminal of the comparator.
Wherein the potential of the input terminal is input to the second end;
Output from the output terminal when it becomes lower than the reference voltage
The gate element is turned off by the gate signal
A semiconductor integrated circuit with an input pull-up circuit. 2. The semiconductor integrated circuit with an input pull-up circuit according to claim 1, wherein said gate element is an insulated gate field effect transistor, and said gate is a gate electrode of said transistor. 3. The semiconductor integrated circuit with an input pull-up circuit according to claim 2, wherein said insulated gate field effect transistor is a P-channel transistor. 4. The device according to claim 1, wherein a pull-up resistor is connected between the input terminal and the higher reference potential line in parallel with the gate element. Semiconductor integrated circuit with input pull-up circuit. 5. A control signal from a control terminal is input between the gate and an output terminal of the comparator, and the output is sent to the comparator and the gate.
4. The semiconductor integrated circuit with an input pull-up circuit according to claim 1, further comprising an AND gate for setting a reset signal for a circuit other than the element .