JP3225887B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device for a power IC in which a control system and a large-current output stage element are integrated.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit using a power semiconductor of this type has a protection function for preventing the power semiconductor from being destroyed due to an overcurrent or a short circuit.

[0003] A conventional first circuit disclosed in Japanese Patent Application Laid-Open No. 1-193909 including a monitor signal generating circuit for this kind of protection function is disclosed.
Referring to FIG. 3 which is a circuit diagram of a semiconductor integrated circuit device of the related art, this first semiconductor integrated circuit device of the related art has an FET1, a voltage-controlled power semiconductor element having a drain connected to a load Z2, and a drain and a gate. FET1 each
And a NPN transistor 3 connected in parallel to the source and gate of
A current mirror circuit 101 comprising PNP
A current mirror circuit 102 composed of transistors 35 and 36 of the same type, a current source 37 for supplying a reference current I0 to the transistor 36, a power supply 8 for supplying power to the current mirror circuit 102, and a power supply 9 for the FETs 1 and 2. .

Next, the operation of the first conventional semiconductor integrated circuit device will be described with reference to FIG. 3. The current mirror circuit 101 receives the drain current of the FET 2 and the current mirror circuit 102 corresponding to the reference current I0. Compared with the output, a voltage signal S1 corresponding to the difference current is output to the output terminal TO.

In this circuit, since the power FET1 and the FET2 having a small current capacity are connected in parallel, the current IL flowing through the load Z2 is such that the currents I1 and I2 are equal to the area ratio of the FET1 and the FET2. And each of these currents I1 and I2 flows separately to FET1 and FET2. When the current I2 flows to the FET2, the current I2 flows to the transistor 33 of the current mirror circuit 101, so that a current I3 determined by the area ratio of the transistors 33 and 34 flows through the transistor 34. The current flowing through the transistor 36 of the current mirror circuit 102 has a constant value by the constant current source 37, and the current I4 determined by the area ratio of the transistors 35 and 36 flows through the transistor 35. Therefore, the current I3 that changes in proportion to the state of the current I1 flowing to the load R2 flows through the transistor 34, whereas the transistor 35 has the ability to flow only a certain current I4. Therefore, compared to the current I4, the current I
3 is small, the transistor 34 is the transistor 3
5 cannot continue to flow, and a current surplus occurs. To eliminate this surplus current, the operating point of the transistor 35 shifts from the non-saturation region to the saturation region. Level S1 rises. On the other hand, if the current I3 is larger than the current I4, the transistor 34 cannot supply the set current I4 or more, so that a shortage of current occurs. Since the operating point shifts to the saturation region, the voltage level S1 of the output terminal TO decreases.

As described above, the voltage level S1 of the output terminal TO is equal to the current value I flowing through the transistors 34 and 35.
It changes depending on the magnitude relation of 3, I4. By setting the reference current value I0 and the area ratio of the transistors 33, 34 and 34, 36 of each of the current mirror circuits 101, 102, the output terminal when the current I1 flowing through the FET 1 becomes equal to or more than the set current value The detection of the overload state of the FET 1 is realized by using the change of the voltage level S1 of TO.

FIG. 4 is a circuit diagram of a second conventional semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 6-244693, in which the same components as those of FIG. Referring to FIG. 1, this second conventional semiconductor integrated circuit device has the same structure as that of the first conventional technology, except that the sources and gates of FETs 1 and 2 are connected in parallel, and the load between the drain of the FET 1 and the power supply 9. In addition to Z2 and power supply 9,
A reference resistor R201, which is connected between the drain of the FET2 and the power supply 9 to generate a reference voltage V0 corresponding to the drain current of the FET2, compares the load voltage V1 generated in the load Z2 with the reference voltage V2, and compares the comparison signal VS Output from the comparator 201
And a bias control circuit 202 for controlling the bias voltage of the gates of the FETs 1 and 2.

Next, the operation of the second conventional semiconductor integrated circuit device will be described with reference to FIG. 4. FET1 and FET2 are reciprocals K1, K2 (K1 <
K2). Further, the resistance r2 of the load Z2 of the FET1 is
The resistance value r1 of the load resistor R201 is expressed as ｛(K2-1) × R
By setting 2｝, FET2 is always
The source-drain voltage, ie, the reference voltage V0 is F
The state is higher than the source-drain voltage of ET1, that is, the load voltage V1. These voltages V1 and V0 are compared with the comparator 2
The comparison signal S1 is supplied to the positive and inverted inputs of 01, and outputs an L level. The bias control circuit 202 turns off the transistor 21 in response to the L level of the comparison signal S1,
The bias voltages B of 1 and 2 are held at the normal level. When the resistance value of the load Z2 decreases for some reason with respect to the normal load state, the load voltage V1 becomes higher than the reference voltage V0. Comparator 201 inverts comparison signal S1 to an H level in response to the rise of load voltage V1. The bias control circuit 2 responds to the H level of the comparison signal S1.
02 transistor 22 is turned on, causing the bias voltage B to drop. As described above, the voltages V1 and V0 are output from the comparator 201.
Thus, detection of the normal load state and the abnormal load state is realized.

FIG. 5 is a block diagram showing a third conventional semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 3-195212 using common characters / numerals for constituent elements common to FIG.
In this third conventional semiconductor integrated circuit device, a voltage detection circuit that is connected between the gate and the source of the FET 1 and outputs a detection voltage VG corresponding to a gate-source voltage is provided in the third conventional semiconductor integrated circuit device. 301 and the comparison signal S2
Drive circuit 302 which amplifies the input signal D and supplies the drive signal G for the gate of FET1 by the control of
And a comparator 303 that compares the reference voltage V0 with the voltage VG and outputs a comparison signal S2, and a reference voltage generator 304 that generates the reference voltage V0.

Next, the operation of the third conventional semiconductor integrated circuit device will be described with reference to FIG. 5. This circuit changes the level of the output G of the gate drive circuit 302 so that the gate-source The desired current limitation is performed by utilizing the saturation region characteristics between the voltage and the drain current. First, the comparator 303 compares the gate detection voltage VG with the reference voltage V0, and controls the drive signal G so that the gate-source voltage does not become higher than the reference voltage V0. By setting the gate-drain voltage in this manner, the drain current of the FET 1 cannot flow more than the current value determined by the static characteristics.
It is possible to limit the drain current of ET1.

[0011]

In the above-mentioned first conventional semiconductor integrated circuit device, the current error generated in each of the two-stage current mirror circuits is caused by the difference between the reference current value and the small current capacity semiconductor for detecting overcurrent. There is a drawback that the current values flowing through the elements are affected, respectively, causing errors.

Further, in the ordinary bipolar transistor constituting the current mirror circuit, the impedance between the emitter and the collector in the active region is on the order of several MΩ, so that the impedance at the output terminal is several MΩ, and switching noise and the like generated at the time of switching. However, there is a drawback in that an output signal line is affected by capacitive coupling and a malfunction occurs.

Further, in the second conventional semiconductor integrated circuit device, when the load includes an inductance component, a voltage higher than the power supply voltage is applied to the input terminal of the comparator due to the back electromotive force generated at the time of turn-off. There is a drawback that the device is destroyed due to the occurrence of cracks.

Furthermore, the third conventional semiconductor integrated circuit device utilizes the saturation characteristics of a voltage-driven semiconductor element. However, since the third semiconductor integrated circuit device operates in a saturation region, the power consumption of the power semiconductor increases significantly, and the overcurrent increases. However, there was a drawback that thermal destruction was attained even if destruction due to heat was prevented.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, to provide high accuracy in detecting abnormalities such as overload, to be resistant to noise interference, to eliminate a factor of thermal destruction, and to reduce power even in a load including an inductance component. An object of the present invention is to provide a semiconductor circuit device capable of detecting a state of a semiconductor element.

[0016]

According to the present invention, there is provided a semiconductor integrated circuit device connected to a load, an output semiconductor element for controlling a load current of the load, and a load current change extraction for extracting a change in the load current. Means, current-voltage conversion means for converting the extracted change in the load current into a current change voltage signal, and a current-to-voltage conversion signal for a predetermined reference voltage of the current change voltage signal.
That exceeded in response a voltage comparing means for outputting a predetermined level comparison signal of the load current variation extracting means
Has a drain and a gate each of which is the semiconductor element.
Connected in parallel to the drain and gate of one FET
Area is smaller than the first FET at a predetermined ratio.
A second FET and an input connected to the source of the second FET
A current mirror circuit connected to the
Conversion means, one end of which is connected to the output end of the current mirror circuit.
The end is provided with a resistor connected to a power supply .

[0017]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention using common characters / numerals for components common to those in FIG. 9, and FIG. The semiconductor integrated circuit device according to the present embodiment shown in FIG. 1 has an FET 1 as a power element common to the first conventional technology in which drains and gates are connected in parallel, and an FE as a small current element for detection.
T2, a power supply 8 for supplying a voltage V3, a power supply 9 for supplying a load current IL, and a current mirror circuit 5 including FETs 3 and 4, which are N-channel MOS transistors, in addition to a load resistor R2. , A resistor R1 connected between the power supply 8 and the drain of the FET 4 to generate the detection voltage V1
A reference voltage source 6 for supplying a reference voltage V0, a comparator 7 for inputting a reference voltage V0 to a positive input and a detection voltage V1 to an inverted input, comparing these voltages V0 and V1, and outputting a comparison signal S1. Is provided.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, the currents I1 and I2 of the FET1 and the FET2 are set to the load Z2 as described in the first prior art. Load current IL flowing through
2 are distributed so as to have a ratio of each of the element areas A1 and A2, and are represented by the following equations.

I1 = IL × A1 / (A1 + A2) (1) I2 = IL × A2 / (A1 + A2) ... (2) The current I2 flows through the FET3 of the current mirror circuit 5,
FET4 has element areas A3, A4 of FET3, 4 respectively.
The current I4 of the following equation determined by the ratio of?

I4 = I2 × A4 / (A3 + A4) (3) This current I4 flows through the resistor R1 between the FET 4 and the power supply 8, and the resistance of this resistor If the value is R1, the resistance R1 and FE
A detection voltage V expressed by the following equation is applied to a node N1 which is a connection point with T4.
1 occurs.

V1 = V3-R1 × I4 (4) = V3- [R × IL × A2 × A4 / ｛(A1 + A2) × A3}] (5) That is, the detection voltage V1 changes according to the state of the load current IL.

The comparator 7 has a detection voltage V1 and a reference voltage V0.
And outputs a comparison signal S1 corresponding to the magnitude relationship between these voltages V0 and V1 to the output terminal TO.

Here, the upper limit of the load current IL is equal to the load Z2.
, The shape and circuit constant of each element are set such that the detection voltage V1 and the reference voltage V0 become equal. As a result, the magnitude relationship between the detection voltage V1 and the reference voltage V2 is reversed between the case where the load current IL is smaller than the set upper limit, that is, the normal state, and the case where the load current IL flows beyond the set upper limit, that is, the overload state. As a result, the comparison signal S1
The state of the FET 1 is detected when the output level of the FET 1 greatly changes.

That is, in the normal state, since the detection voltage V1 is lower than the reference voltage V0, the comparison signal S1 is at the L level. In the overload state, on the contrary, since the detection voltage V1 becomes higher than the reference voltage V0, the comparison signal S1 is inverted to the H level.

As a specific numerical example, the area ratio A1: A2 of the FETs 1 and 2 is set to FE of the 999: 1 current mirror circuit 5.
The area ratio A3: A4 of T3,4 is 10: 1, the resistance value of the resistor R1 is 2.5 kΩ, the reference voltage V0 is 2.5V, and the voltage V3 of the power supply 8 is 5V. In addition, it is assumed that a sufficiently low inductance having a DC equivalent resistance is connected as the load Z2.

In this state, when the drive signal ID is supplied to the FETs 1 and 2 and the FETs 1 and 2 change from the cut-off state to the conductive state, the load current IL that increases with time starts to flow from the load Z2, and the load current IL Is assumed to have reached 9A. At this time, currents I1 and I2 corresponding to the area ratio flow through the FETs 1 and 2, and the current I1 is 8991 mA and the current I2 is 9 mA according to the equations (1) and (2). Current I
2 flows through the current mirror circuit 5 as it is,
From the equations (3) and (4), the current I3 of the FET3 is 9 mA,
The current I4 of ET4 is 0.9 mA. This current I4 is converted into a detection voltage V1 by the resistor R1, and this voltage V1
1 becomes 2.75 V from the equation (4) and is supplied to the inverting input of the comparator 7. On the other hand, since the positive input voltage of the comparator 7 is 2.5 V of the reference voltage V0, the comparator outputs L level.

Next, after a lapse of time from the above-described circuit state, the load current IL slightly exceeds 10 A.
+ Α is assumed. At this time, the current I1 is 9990 m
A + α1, current I2 is 10 mA + α2, current I3 is 10
mA + α2, and the current I4 is 1 mA + α3. This current I4 is converted into the detection voltage V1 by the resistor R1, and this voltage V1, that is, the inverted input voltage of the comparator 7 becomes 2.5V-
It becomes α4. On the other hand, the positive input voltage of the comparator 7 remains at the reference voltage of 2.5 V, and the voltage of the positive input is slightly higher than the voltage of the inverted input. Becomes By monitoring the level of the comparison signal S1, it is possible to detect whether the FET 1 is in an overcurrent state or not.

Also, in contrast to the conventional first technology in which the current mirror circuit is composed of two stages, in the present embodiment, the current mirror circuit is composed of one stage. Can be reduced. Further, in the circuit of the present embodiment, there is no place having a high impedance of the order of several MΩ, and a margin for malfunction due to switching noise or the like can be expanded.

Further, the load is not limited to the resistance as in the second conventional technique, and an inductance load can be handled.

Further, in this embodiment, an N-channel MOS transistor is used as a transistor constituting a current mirror circuit.
Instead of using an S-type FET, an NPN bipolar transistor may be used.

Next, a second embodiment of the present invention will be described with reference to FIG. 2, which is also shown in a circuit diagram by using common characters / numerals for constituent elements common to FIG. The difference of the embodiment from the first embodiment is that the comparison signal S1 has H level.
Drive signal ID of FETs 1 and 2 in response to inversion to level
That is, a shutoff circuit 10 for shutting off is further added.

The cutoff circuit 10 calculates the logical product of the latch signal F1 such as an RS flip-flop that latches the comparison signal S1 and outputs the latch signal L, and the drive signal D supplied from the drive circuit 11 and the latch signal L. A two-input AND circuit A1 for generating a drive signal ID.

The operation will be described. At the time of startup, the latch circuit F1 sets the initial state, that is, the signal Q bar to the H level by the reset signal R. The latch circuit F1 responds to the comparison signal S1 supplied to the input S, and this signal S1
And supplies the inverted output signal Q-bar to one input of the AND circuit A1. The AND circuit A1 takes the logical product of this signal Q bar and the drive signal D supplied to the other input, and outputs a drive signal ID. In the normal operation state, as described above, since the comparison signal S1 is at the L level, the signal Q goes to the H level, and the AND circuit A1 passes the drive signal D and outputs it as the drive signal ID. Therefore, FETs 1 and 2 operate according to the level of drive signal ID.

Next, in an overload state, the comparison signal S1 becomes H
Level, and the signal Q bar becomes L level, so AND
The circuit A1 cuts off the drive signal D and therefore the drive signal ID. As a result, the FETs 1 and 2 are turned off,
The protection operation is realized.

Since the FETs 1 and 2 are cut off, current cannot be supplied to the load Z2 and the FETs 3 and 4. However, almost simultaneously with the interruption of these FETs 1 and 2,
As the comparison signal S1 changes from H level to L level again, the input S of the latch circuit F1 changes from H level to L level.
Change to level. However, the signal Q bar keeps the L level until the reset signal R is input, and the FETs 1 and 2 keep the cut-off state irrespective of the drive signal D to protect the FETs 1 and 2.

The circuit according to the present embodiment does not utilize the saturation characteristics of the power FET, as in the third conventional technique, but operates to shut off the power FET itself.
The element does not break down due to heat generation due to a rapid increase in power consumption.

[0037]

As described above, the semiconductor integrated circuit device of the present invention includes the load current change extracting means, the current / voltage converting means, and the voltage comparing means, so that the current mirror circuit is provided in one stage. Because of the reduction, there is an effect that the state of the semiconductor element can be detected with higher accuracy.

Further, since there is no high impedance portion in the circuit, there is an effect that a malfunction margin due to disturbance noise such as switching noise can be increased.

Further, since the change in the potential of the load is not directly detected but extracted as a change in current and then converted into a voltage and detected, the influence of the load impedance state can be avoided.
There is an effect that not only a resistance but also an inductance can be connected as a load.

Furthermore, the voltage control type semiconductor device is not controlled in the saturation region, but is completely shut off, so that there is an effect that thermal destruction due to an increase in loss in the semiconductor device can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 3 is a circuit diagram showing an example of a first conventional semiconductor integrated circuit device.

FIG. 4 is a circuit diagram showing an example of a second conventional semiconductor integrated circuit device.

FIG. 5 is a block diagram showing an example of a third conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1-4 FET 21, 33-36 Transistor 5, 101, 102 Current mirror circuit 6 Reference voltage source 7, 201, 303 Comparator 8, 9 Power supply 10 Cutoff circuit 11 Drive circuit A1 AND circuit F1 Latch circuit R1 Resistance Z2 Load

Claims (2)

(57) [Claims] An output semiconductor element connected to a load for controlling a load current of the load; a load current change extracting unit for extracting a change in the load current; Current-voltage conversion means for converting the current-change voltage signal to a predetermined reference voltage ;
And a voltage comparison means for outputting a level comparison signal of a predetermined response to the excessive, said load current change detection means, each of the drain and gate
Is connected to the drain of the first FET which is the semiconductor element.
Connected in parallel to each of the
A second FET smaller than the first FET, and a current having an input connected to the source of the second FET.
A mirror circuit, wherein the current-voltage conversion means has one end connected to the current mirror circuit.
The semiconductor integrated circuit device according to claim Rukoto with the other end connected to the source resistance at the output end of the road. 2. The semiconductor integrated circuit device according to claim 1, further comprising a drive signal cutoff unit that cuts off a drive signal of the semiconductor element in response to the supply of the comparison signal.