JPH07130938A - Lead frame for semiconductor integrated circuit - Google Patents
Lead frame for semiconductor integrated circuitInfo
- Publication number
- JPH07130938A JPH07130938A JP5271099A JP27109993A JPH07130938A JP H07130938 A JPH07130938 A JP H07130938A JP 5271099 A JP5271099 A JP 5271099A JP 27109993 A JP27109993 A JP 27109993A JP H07130938 A JPH07130938 A JP H07130938A
- Authority
- JP
- Japan
- Prior art keywords
- island
- pellet
- lead frame
- lead
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路用リード
フレームに関し、特に樹脂封止半導体集積回路に用いら
れる半導体集積回路用リードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for semiconductor integrated circuits, and more particularly to a lead frame for semiconductor integrated circuits used in resin-sealed semiconductor integrated circuits.
【０００２】[0002]
【従来の技術】図３は従来の半導体集積回路用リードフ
レーム（以下、リードフレームと記す）の一例の平面
図、図４（ａ），（ｂ）は図３のリードフレームにペレ
ットを搭載した平面図およびそのＢ−Ｂ’線断面図であ
る。従来の樹脂封止半導体集積回路に用いられるリード
フレームは、図３に示すように、小さなアイランド４０
を有し、アイランド４０はアイランド吊り用リード４
１，４２によって支持されている。また、リード４３は
搭載するペレットの内側まで存在する。2. Description of the Related Art FIG. 3 is a plan view of an example of a conventional lead frame for a semiconductor integrated circuit (hereinafter, referred to as a lead frame), and FIGS. 4 (a) and 4 (b) show a lead frame of FIG. It is a top view and its BB 'sectional view taken on the line. As shown in FIG. 3, a lead frame used in a conventional resin-sealed semiconductor integrated circuit has a small island 40.
And the island 40 has leads 4 for island suspension.
It is supported by 1, 42. Further, the lead 43 exists up to the inside of the pellet to be mounted.
【０００３】図４（ａ），（ｂ）に示すように、ペレッ
ト２０を搭載する場合には、ペレット２０のサイズより
少し大きいサイズの絶縁フィルム５０をペレット２０の
底部に敷いてワイヤ５１でペレット２０とリード４３と
を接続している（実開昭６３−１６５８４６号公報参
照）。このような構成にすることにより、搭載するペレ
ット２０のサイズに合わせて絶縁フィルム５０のサイズ
を変えることでサイズの異なるペレット２０を同一リー
ドフレームに搭載することができる。As shown in FIGS. 4 (a) and 4 (b), when the pellet 20 is mounted, an insulating film 50 having a size slightly larger than the size of the pellet 20 is laid on the bottom of the pellet 20 and is pelletized with a wire 51. 20 and the lead 43 are connected (see Japanese Utility Model Laid-Open No. 63-165846). With such a configuration, it is possible to mount pellets 20 having different sizes on the same lead frame by changing the size of the insulating film 50 according to the size of the pellets 20 to be mounted.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来のリード
フレームでは、リードフレームとペレットとの間に必ず
絶縁フィルムを必要とし、そのため工数がかかり、アイ
ランドとペレットの底部が絶縁されているのでペレット
の基板電位を安定させることができず、また、絶縁フィ
ルムをアイランド上に敷くことによってペレットの位置
がリードよりも高くなり、そのため、ペレットとリード
を接続するワイヤが長く角度がきつくなり接続信頼性上
の問題点もあった。In the above-mentioned conventional lead frame, an insulating film is always required between the lead frame and the pellet, which requires man-hours and the bottom of the island is insulated from the pellet. The substrate potential cannot be stabilized, and the insulating film is laid on the island so that the pellet position is higher than the leads. Therefore, the wire connecting the pellet and the lead is long and the angle is tight, which increases connection reliability. There was also a problem.
【０００５】本発明の目的は、絶縁フィルムを用いずに
同一のリードフレームで異なるサイズのペレットを搭載
できる接続信頼性が高く基板電位の安定した汎用性のあ
るリードフレームを提供することにある。An object of the present invention is to provide a versatile lead frame in which pellets of different sizes can be mounted on the same lead frame without using an insulating film, the connection reliability is high, and the substrate potential is stable.
【０００６】[0006]
【課題を解決するための手段】本発明は、ペレットを搭
載するアイランドと、前記ペレットのパッドとボンディ
ングワイヤを介して接続するリードと、前記アイランド
に接続しこのアイランドを支持するアイランド吊り用リ
ードとを有する半導体集積回路用リードフレームにおい
て、前記アイランドのサイズが搭載を対象とする前記ペ
レットのいずれのサイズよりも小さく、前記リードが前
記アイランドに接続している。According to the present invention, there are provided an island on which a pellet is mounted, a lead connected to a pad of the pellet via a bonding wire, and an island suspension lead connected to the island and supporting the island. In the lead frame for a semiconductor integrated circuit having, the size of the island is smaller than any size of the pellet to be mounted, and the lead is connected to the island.
【０００７】[0007]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００８】図１は本発明の一実施例の平面図、図２
（ａ），（ｂ）は図１のリードフレームにペレットを搭
載した平面図およびそのＡ−Ａ’線断面図である。ま
ず、図１に示すように、対象とする搭載ペレットよりも
小さいアイランド１０と、このアイランド１０を支持す
るアイランド吊り用リード１１，１２とアイランド１０
に接続するリード１３とを有するリードフレームを形成
する。FIG. 1 is a plan view of an embodiment of the present invention, FIG.
(A), (b) is the top view which mounted the pellet on the lead frame of FIG. 1, and its AA 'sectional view taken on the line. First, as shown in FIG. 1, an island 10 that is smaller than the target mounting pellet, the island suspension leads 11 and 12 that support the island 10, and the island 10.
Forming a lead frame having a lead 13 connected to.
【０００９】次に、図２（ａ），（ｂ）に示すように、
アイランド１０とリード１３との間を切断した後、アイ
ランド１０とこのアイランド１０に接続して残されたり
リード残り２２上にペレット２０を搭載し、ワイヤ２１
でペレット２０と切断されたリード１３を接続する。こ
のとき、アイランド１０はアイランド吊り用リードに支
持されている。Next, as shown in FIGS. 2 (a) and 2 (b),
After cutting between the island 10 and the lead 13, the pellet 20 is mounted on the island 10 and the lead remaining 22 which is left connected to the island 10 and the wire 21.
Then, the pellet 20 and the cut lead 13 are connected. At this time, the island 10 is supported by the island suspension leads.
【００１０】このように、リードフレームにペレット２
０を搭載するときに搭載するペレット２０のサイズに合
わせてリード１３を切断すれば、サイズの異なるペレッ
ト２０を搭載できる。リード１３切断後ペレット２０の
底部に残ったリード残り２２は、ペレット２０を支える
アイランド１０の補強の役割も果し、一方、ペレット２
０の底面とアイランド１０は絶縁物を介することなく接
続されているので、ペレット２０の基板電位を安定させ
ることができる。In this way, the pellet 2 is attached to the lead frame.
If the leads 13 are cut in accordance with the size of the pellets 20 to be mounted when 0 is mounted, pellets 20 of different sizes can be mounted. The lead residue 22 remaining at the bottom of the pellet 20 after cutting the leads 13 also serves to reinforce the island 10 that supports the pellet 20, while the pellet 2
Since the bottom surface of 0 and the island 10 are connected without an insulator, the substrate potential of the pellet 20 can be stabilized.
【００１１】[0011]
【発明の効果】以上説明したように本発明は、アイラン
ドのサイズの搭載を対象とするペレットのいずれのサイ
ズよりも小さくし、リードをアイランドに接続させるこ
とにより、ペレット搭載時にサイズに合った大きさにア
イランドとリードの間を切断することで対象とするサイ
ズの異なるペレットの全てを搭載でき汎用性を持たせる
ことができる効果がある。As described above, according to the present invention, the size of the island is smaller than any of the pellets intended to be mounted, and the leads are connected to the island, so that the size suitable for the pellet mounting can be achieved. By cutting between the island and the lead, it is possible to mount all the pellets of different target sizes and to have versatility.
【００１２】また、アイランドとペレット間に絶縁物を
使用することがないので接続するワイヤを短くできるの
で接続信頼性を高め基板電位を安定させる効果もある。Further, since an insulator is not used between the island and the pellet, the wire to be connected can be shortened, so that the connection reliability is improved and the substrate potential is stabilized.
【図１】本発明の一実施例の平面図である。FIG. 1 is a plan view of an embodiment of the present invention.
【図２】（ａ），（ｂ）は図１のリードフレームにペレ
ットを搭載した平面図およびそのＡ−Ａ’線断面図であ
る。2A and 2B are a plan view of a pellet mounted on the lead frame of FIG. 1 and a sectional view taken along the line AA ′.
【図３】従来のリードフレームの一例の平面図である。FIG. 3 is a plan view of an example of a conventional lead frame.
【図４】（ａ），（ｂ）は図３のリードフレームにペレ
ットを搭載した平面図およびそのＢ−Ｂ’線断面図であ
る。4 (a) and 4 (b) are a plan view and a cross-sectional view taken along line BB 'of FIG. 3 in which pellets are mounted on the lead frame.
１０，４０ アイランド １１，１２，４１，４２ 吊り用リード １３，４３ リード ２０ ペレット ２１，５１ ワイヤ ２２ リード残り ５０ 絶縁フィルム 10,40 Island 11,12,41,42 Hanging lead 13,43 Lead 20 Pellet 21,51 Wire 22 Lead remaining 50 Insulating film
Claims (1)
ペレットのパッドとボンディングワイヤを介して接続す
るリードと、前記アイランドに接続し、このアイランド
を支持するアイランド吊り用リードとを有する半導体集
積回路用リードフレームにおいて、前記アイランドのサ
イズが搭載を対称とする前記ペレットのいずれのサイズ
よりも小さく、前記リードが前記アイランドに接続して
いることを特徴とする半導体集積回路用リードフレー
ム。1. A semiconductor integrated circuit lead having an island on which a pellet is mounted, a lead connected to a pad of the pellet via a bonding wire, and an island suspension lead connected to the island and supporting the island. In the frame, the lead frame for a semiconductor integrated circuit is characterized in that the size of the island is smaller than any size of the pellets which are symmetrically mounted, and the leads are connected to the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5271099A JPH07130938A (en) | 1993-10-29 | 1993-10-29 | Lead frame for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5271099A JPH07130938A (en) | 1993-10-29 | 1993-10-29 | Lead frame for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07130938A true JPH07130938A (en) | 1995-05-19 |
Family
ID=17495340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5271099A Pending JPH07130938A (en) | 1993-10-29 | 1993-10-29 | Lead frame for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07130938A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09107062A (en) * | 1995-10-11 | 1997-04-22 | Nec Corp | Semiconductor device and manufacture thereof |
| WO2000051179A1 (en) * | 1999-02-23 | 2000-08-31 | Koninklijke Philips Electronics N.V. | Method of manufacturing a leadframe assembly |
-
1993
- 1993-10-29 JP JP5271099A patent/JPH07130938A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09107062A (en) * | 1995-10-11 | 1997-04-22 | Nec Corp | Semiconductor device and manufacture thereof |
| WO2000051179A1 (en) * | 1999-02-23 | 2000-08-31 | Koninklijke Philips Electronics N.V. | Method of manufacturing a leadframe assembly |
| US6340634B1 (en) | 1999-02-23 | 2002-01-22 | U.S. Philips Corporation | Method of manufacturing an assembly of conductors and a semiconductor device manufactured by means of such an assembly |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19961210 |