JPH07128411A - Delay testing method - Google Patents

Abstract

PURPOSE:To execute the delay testing of a scan circuit by observing an output signal of a second FF circuit section at the timing set by considering delay of a signal in a scan-out path. CONSTITUTION:When a clock signal set by considering a quantity of delay of a signal in a functional logic circuit G is inputted from a clock-inputting terminal 4, an output signal of the circuit G is fetched into an ending point FF circuit 63A in synchronism with the timing to be outputted from an output terminal 12. The output signal is outputted to the outside of an LSI via a path P2 from the terminal 12 of the circuit 63A to a scan-out terminal 13 so that the signal outputted from the terminal 13 is observed. After finishing the observation, delay test information in relation to a normal logic circuit path P1 including the circuit G, i.e., a logical value of the circuit 63A is outputted to the outside from the terminal 13 under the controlling of a scan-out control unit to be observed. By utilizing each information obtained by the above manner, the analysis of a failure is carried out by an equipment-diagnosis device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay test (delay fault detection test) technique for a signal propagation path, and more particularly to a technique effective when applied to a logic LSI applied to a large-scale computer or the like.

[0002]

2. Description of the Related Art A large-scale computer system is provided with an automatic diagnosis function for realizing system maintenance, diagnosis, etc., so that reliability is improved. In the logic LSI applied to such a large-sized computer, the delay test of the internal signal propagation path can be performed using the test pattern generated in advance in order to enable the above-mentioned automatic diagnosis.

This delay test can be performed by propagating a change signal (rising, falling) on a single path and observing an output point after a designed propagation time. In this technique, a test circuit (called a scan circuit) that can freely read and write the logical value of a flip-flop (hereinafter abbreviated as FF) in the circuit independently of normal logic is incorporated, and clock terminals of each FF are incorporated. On the other hand, it is premised that the pulse signal can be applied from the LSI external terminal at any timing. As input and output points of change signals, not only LSI external terminals but also LSI
The internal FF is also made available. By applying such a technology, the algorithm for creating the pattern for the delay test can be applied only to the combination circuit separated by the FF or the LSI external terminal, and the automatic generation of the test pattern by the device or software can be performed. Made possible.

As an example of a document describing the delay test technique, there is JP-A-52-28613.

[0005]

In the above prior art, what is tested is a normal logic circuit that realizes the function originally possessed by the LSI, that is, a circuit that realizes a predetermined function in the normal operation of the LSI. Therefore, the scan circuit for performing the delay test of such a circuit is excluded from the test target.

However, in a large-scale electronic computer or the like, a scan circuit is used for the purpose of monitoring the logical value of each FF in the logic LSI in real time during automatic device diagnosis in the field, and the machine cycle speed is increased. As a result, an undesired increase in the delay of the scan circuit may hinder automatic device diagnosis.
Found by the inventor. In addition, it is necessary to use an algorithm for generating a test pattern for enabling the delay test of the scan circuit separately from the test pattern for the normal logic circuit, assuming a delay defect of the scan circuit. Becomes

A first object of the present invention is to provide a technique for performing a delay test of a scan circuit.

A second object of the present invention is to provide a technique for performing a delay test of a scan circuit without using a test pattern dedicated to the test of the scan circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

The output signal of the second flip-flop circuit section arranged at the end point of the test target path is observed at a timing set in consideration of the signal delay in the scan-out path after the second flip-flop circuit section. The delay defect analysis is performed based on this observation result and the delay test result of the test target path. At this time, address information for selecting the second flip-flop circuit section, normal output expected value from the second flip-flop circuit section, and normal output expectation are included in the information for the delay test of the test target path. The delay test can be performed based on the test pattern to which the timing information for observing the value is added.

[0012]

According to the above means, the output signal of the flip-flop circuit section arranged at the end point of the test target path is observed at the timing set in consideration of the signal delay in the scan-out path after this circuit section. Doing so enables a scan-out delay test.

The information for the delay test of the path to be tested includes address information for selecting the second flip-flop circuit section, a normal output expectation value from the second flip-flop circuit section, and this normal value. Performing the delay test based on the test pattern to which the timing information for observing the expected output value is added does not require generation of a dedicated test pattern for the scan-out delay test.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows a large-scale computer to which the method according to one embodiment of the present invention is applied.

The large-scale electronic computer 41 shown in FIG. 4 has an input unit 41 for fetching data, and an arithmetic unit 44 for processing the data input via the input unit 41 according to a predetermined program. A memory unit 45 for storing the processing result of the arithmetic unit 44, an output unit 42 for outputting the storage information of the memory unit 45 and the arithmetic result of the arithmetic unit 44, and operation control of each unit. It includes a control unit 43. A device diagnostic device (also referred to as a service processor) for maintenance and diagnosis of the large electronic computer is coupled to the computer. This device diagnostic device gives a trace instruction of the internal state to the large-scale electronic computer 41 shown in FIG. 4 and analyzes various information obtained from the large-scale computer 41 in accordance with the instruction to thereby analyze the large-scale computer. 41 diagnosis is performed. In order to enable such a diagnosis, the large-scale electronic computer 41 is provided with a diagnosis function for enabling a diagnosis by the above-mentioned device diagnosis device in addition to the original processing function (basic function).

FIG. 5 shows the diagnostic function of the large-scale electronic computer 41 in relation to the device diagnostic device 100.

A device diagnostic unit 47 is provided to realize the diagnostic function of the large-sized electronic computer 41. When the device diagnostic device 100 gives a trace instruction of the internal state to the large-sized electronic computer 41, the input unit 42 and the control unit are controlled. The internal diagnostic function of each of the unit 43, the arithmetic unit 44, the memory unit 45, and the output unit 46 is activated by the device diagnostic unit 47, and the diagnostic information of each unit is sent to the device diagnostic device 100 via the device diagnostic unit 47. Transmitted.

FIG. 6 shows an example of the internal structure of the output unit 46.

The arithmetic unit 4 is not particularly limited.
6 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

In-unit individual functions 51 and 52 such as an input buffer circuit are provided, and an in-unit individual function 53 such as a driver for outputting a signal to the outside of the LSI is provided in the subsequent stage. An FF circuit unit group 61 including FF (flip-flop) circuit units 61A, 61B, 61C is arranged between the external input terminals T1 to T3 and the in-unit individual function 51. Between the external input terminals T4 to T6 and the individual unit function 52, the FF circuit sections 62A and 62 are provided.
An FF circuit unit group 61 composed of B and 62C is arranged. The FF circuit sections 63A, 63B, and
FF circuit unit group 63 composed of 63C, and FF circuit unit 64
An FF circuit unit group 64 composed of A, 64B and 64C is arranged. Furthermore, the individual function 53 in the unit and the external output terminal T
Between 7 and T9, FF circuit parts 65A, 65B, 65
An FF circuit unit group 65 composed of C is arranged.

The FF circuit section groups 61, 62, 63, 6
4 and 65 are basically provided for adjusting the timing of the input signal by the signal holding function.
As will be described later, the scan-in and scan-out functions function as a scan circuit for realizing the delay test of the circuit for realizing the individual function in each unit. That is, when the basic function is signal timing adjustment, it also has a delay test function.

FIG. 7 shows the configuration of the output unit 46 when focusing on the diagnostic function for the delay test.

As shown in FIG. 7, a scan-in control unit 67 and a scan-out control unit 68 are provided, and the FF circuit section groups 61 and 6 are provided.
The operations of 2, 63, 64 and 65 are controlled. For example, the scan-in control unit 67 responds to the control signal input from the external input terminal of the LSI by the FF circuit section groups 61, 62, 63, 64, 65.
Of these, select the FF circuit section to scan in,
The scan-in value (1 or 0) is set and the scan-in timing is controlled. Further, the scan-out control unit 68 selects an FF circuit section to be scanned out or selects a value scanned out from the selected FF circuit section according to a control signal input from an external input terminal of the LSI. It has a function to output externally.

FIG. 1 shows a structural example of a main part of the output unit 46 when focusing on the delay test function.

According to the prior art, when the FF circuit section 61A and the FF circuit section 63A are selected, the delay test is performed only on the normal logic circuit path P1 from the FF circuit section 61A to the FF circuit section 63A. However, in the present embodiment, in addition to the delay test of the normal logic circuit path P1, the delay test of the scan circuit path P2 from the FF circuit portion 63A to the scan out terminal 13 is performed.
In order to enable such a delay test, in the present embodiment, as the FF circuit units 61A and 63A, those which can monitor the output logic by selection by addressing without requiring a trigger signal are used. I am using.
Although not particularly limited, such an FF circuit unit is realized by a combination of a set / reset type FF and a logic gate.

FIG. 8 shows a configuration example of the scan circuit section 61A.

As shown in FIG. 8, the scan circuit section 61A includes a set / reset type FF (flip-flop) 71, an inverter 72, and a 3-input AND gate 7.
3, 74 and 2 input AND gate 75 are included. The signal scanned into the FF 71 is input to the input AND gate 37 via the terminal 79 and to the 3-input AND gate 74 via the inverter 72. Also, the scan-in timing clock is the terminal 8
It is adapted to be inputted to the 3-input AND gates 73 and 74 via 0. The selector circuit 76 decodes the address signal for FF selection to
The F selection signal 81 is obtained and is a part of the function of the scan-in controller 67 or the scan-out controller 68. When the FF selection signal 81 is asserted to the high level, the FF circuit portion 63A (FF71) is brought into the selected state. In this state, when the output logic of the AND gate 73 becomes high level, the output terminal (Q) 12 of the FF 71 becomes high level, and the AND circuit 74
When the output logic of is at low level, the output terminal 12 of the FF 71 is at low level. Depending on the logic level of the signal input from the terminal 79, the AND gate 73,
By selectively activating any of 74,
The set / reset state of the FF 71 can be selected. The terminal D of the FF 71 is a data input terminal, and the logic state of the data input terminal D is held in synchronization with the clock. Further, the 2-input AND gate 75 is activated by the FF selection signal 81 from the selector circuit 76, and when the FF selection signal 81 is at a high level, the output of the output terminal (Q) 12 of the FF 71 is output. Logic is
External output is possible via the AND gate 75 and an OR gate 77 arranged in the subsequent stage. That is, in the selected state by addressing, the signal scanned into the FF 71 can be output to the outside via the AND gate 75 immediately after the scan in by the activation of the AND gate 75.

The FF circuit section 63B and other FF circuit sections having the same structure as the FF circuit section 63A can be applied.

Further, the following information is added to the delay test pattern (the test pattern for the delay test of the scan circuit path P2) generated by using the conventional technique. It should be noted that this additional information is unnecessary in the delay test of the scan circuit path P2.

That is, it is an addressing pattern of the FF circuit portion which is the end point of the test target path in the normal logic circuit test, a normal output expected value from the scan-out terminal, and timing information for observing such an expected value. The addressing pattern is decoded by the selector circuit 76 shown in FIG. Here, the addressing pattern is information obtained at the time of LSI logic design, and the normal output expected value is information already obtained at the time of generating the test pattern of the normal logic circuit. Therefore, in this embodiment, it is not necessary to generate a dedicated test pattern for testing the scan circuit.

FIG. 2 shows the test procedure of the circuit of FIG. 1, and FIG. 3 shows the operation timing of the main part of FIG.

First, the activation condition of the normal logic circuit path to be tested is set (step 21). The activation condition set in this step is a condition necessary for testing the normal logic circuit path P1, and the initialization setting of the FF circuit unit (step 22) and the initialization setting of the input terminal (step 23) are performed using the scan circuit. ), And setting of the end point FF circuit section scan address (step 24).

The initialization setting in step 22 is not particularly limited, but the reset terminal of the FF circuit portions 61A and 63A is set to the high level, so that the output terminal 12
Is in the low level state.

In the initial setting of the input terminal in step 23, the input terminal 1 is set to the low level and the clock input terminal 2 is set to the high level in order to activate the functional logic circuit G represented by the gate.

Further, in the scan address setting in step 24, the scan circuit path P2 from the end point FF circuit section 63A to the scan-out terminal 13 is activated, and in this state, the data is input to the data input terminal 10 of the FF circuit section 63A. The output data can be output from the output terminal 12 of the FF circuit unit 63A in synchronization with the clock input from the clock input terminal 11.

Next, as shown in FIG. 3, by applying a clock signal to the clock input terminal 3, the starting point F
A high level signal is output from the data output terminal 8 of the F circuit unit 61A. This signal is delayed by the functional logic circuit G represented by the gate and transmitted to the data input terminal 10 of the end point FF circuit unit 63A. When the clock signal set in consideration of the signal delay amount in the functional logic circuit G is input from the clock input terminal 4, the output signal of the functional logic circuit G is synchronized with it and is output to the end point FF circuit section 63A. It is taken in and is output from the output terminal 12 of the FF circuit unit 63A (step 26). Since this output signal is output to the outside of the LSI through the path from the output terminal 12 of the FF circuit unit 63A to the scan out terminal 13, the signal output from the scan out terminal 13 is observed (step). 27). This observation is
This is performed via the device diagnostic unit 47 (see FIG. 5).
Immediately after the signal is captured by the FF 71 of the FF circuit unit 63A in synchronization with the assert timing of the scan timing signal 80, the value is output to the output terminal 12 of the FF 71.
Appear in. The scan circuit path P2 delay test information from the output terminal 12 to the scan out terminal 13 is observed by observing the logic state of the scan out terminal 13 at the measurement timing set in consideration of the delay time in the scan circuit path P2. Can be obtained.

After such observation is completed, the delay test information about the normal logic circuit path P1 including the functional logic circuit G, that is, the logic value of the end point FF circuit section 63A is controlled by the scan-out control unit 68. It is observed by being externally output from the scan-out terminal 13 (step 28).

Using the information obtained as described above,
Failure analysis is performed in the device diagnostic device 100. In this analysis, if the observation result of step 27 and its expected value match, and if the observation result of step 28 and its expected value match, the functional logic circuit G represented by the gate. , And the scan circuit are both judged to be operating normally.

On the other hand, if the observation result of step 27 and the expected value thereof do not match, and the observation result of step 28 and the expected value thereof match, the gate is represented. Although the functional logic circuit G is operating normally, it is determined that the scan circuit path P2 has a delay defect.

Furthermore, the observation result of step 27 and the expected value thereof do not match, and the result of step 28
When the observation result by the above does not match the expected value thereof, there is a delay defect in the functional logic circuit G represented by the gate, and in the FF circuit section 63A that handles a signal input through such a functional logic circuit G. , The delay test of the scan circuit becomes impossible due to the improper scan-in signal. However, the observation result in step 27 and the expected value thereof match, and the observation result in step 28 and its If the expected values do not match, it is determined that the functional logic circuit G represented by the gate has a delay defect.

Thus, by comparing the observation result of step 27 with the observation result of step 28, not only the delay test of the functional logic circuit G represented by the gate but also the delay test of the scan circuit can be performed. Become.

According to the above embodiment, the following operational effects can be obtained.

(1) Observe the output signal of the FF circuit section 63A arranged at the end point of the test target path at a timing set in consideration of the signal delay in the scan circuit path P2 after this circuit section 63A. This enables a scan-out delay test. By performing such a delay test, it is possible to improve the reliability of the scan circuit in the LSI, and at the time of automatic device diagnosis in the field of a large-scale computer to which such an LSI is applied, especially the logical value of FF. It is effective when monitoring in real time.

(2) Address information for selecting the flip-flop circuit section, a normal output expectation value from the flip-flop circuit section, and this normal output expectation value are included in the information for the delay test of the test target path. By performing the delay test based on the test pattern to which the timing information to be observed is added, it is unnecessary to generate a dedicated test pattern for the scan-out delay test.

(3) In the conventional delay test procedure for the normal logic circuit path P1, a fixed procedure (see FIG. 2) required in advance.
By adding steps 24, 27) in
Since the delay test of the scan circuit path P2 can be performed in addition to the delay test of the normal logic circuit path P1,
Although the scan-out delay test is performed in addition to the test target path, the increase in test execution time can be suppressed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the output unit 4
Although 6 is configured by one chip, the present invention can be applied even when the unit to be diagnosed is configured by a plurality of chips. Further, not only the output unit 46 but also the other units such as the input unit 42 and the control unit 43, the paths P1 and P can be obtained in the same manner as the above embodiment.
Two delay tests are possible.

In the above description, the case where the invention made by the present inventor is mainly applied to an LSI used in a large-scale electronic computer which is a field of application which is the background of the invention has been described. It can be widely applied to semiconductor integrated circuits having a delay test function of a signal propagation path by in-scan out.

The present invention can be applied under the condition that at least scan-in and scan-out are performed.

[0050]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by observing the output signal of the flip-flop circuit section arranged at the end point of the test target path at a timing set in consideration of the signal delay in the scan-out path after this circuit section, the scan signal is scanned. Out delay test is possible.

The information for the delay test of the test target path includes the address information for selecting the flip-flop circuit section, the expected normal output value from the flip-flop circuit section, and the expected normal output value. By performing the delay test based on the test pattern to which the timing information to be observed is added, it is unnecessary to generate a dedicated test pattern for the scan-out delay test. The delay test data collection is continuously performed by adding a fixed procedure required in advance to the conventional delay test procedure. Therefore, it is possible to perform a scan-out delay test in addition to the test target path. Nevertheless, the increase in test execution time can be suppressed.

[Brief description of drawings]

FIG. 1 is a main part circuit diagram of an LSI to which a method according to an embodiment of the present invention is applied.

FIG. 2 is a flow chart of a delay test according to an embodiment method of the present invention.

FIG. 3 is an operation timing chart of a main part of the LSI.

FIG. 4 is a basic configuration block diagram of a large-scale computer.

FIG. 5 is a block diagram of a device diagnosis function in the large-sized computer.

FIG. 6 is a basic configuration block diagram of an output unit included in the large-sized electronic computer.

FIG. 7 is a diagnostic function block diagram of an output unit included in the large-sized electronic computer.

FIG. 8 is a circuit diagram of a configuration example of an FF circuit unit included in the output unit.

[Explanation of symbols]

 13 scan out terminal 41 electronic computer 42 input unit 43 control unit 44 arithmetic unit 45 memory unit 46 output unit 47 device diagnostic unit 61-65 FF circuit section group 61A-61C FF circuit section 62A-62C FF circuit section 63A-63C FF circuit Part 64A-64C FF circuit part 65A-65C FF circuit part 67 Scan-in control unit 68 Scan-out control unit 71 FF 76 Selector circuit 100 Device diagnostic device G Functional logic circuit P1 Normal logic circuit path P2 Scan circuit path

Claims (2)

[Claims] 1. A first device arranged at a starting point of a test target path.
The test pattern scanned in from the flip-flop circuit unit is scanned in to the second flip-flop circuit unit arranged at the end point of the test target path, and the second
In a delay test method that enables a delay test of the test target path by scanning out and observing a holding state of the flip flop circuit section, a second flip flop circuit section arranged at an end point of the test target path The step of observing the output signal at a timing set in consideration of the signal delay in the scan-out path after the second flip-flop circuit section is included, and the observation result and the delay test result of the test target path are included in the result. A delay test method characterized by performing delay defect analysis based on the above. 2. The information for the delay test of the test target path includes address information for selecting the second flip-flop circuit section, a normal output expected value from the second flip-flop circuit section, and the normal value. The delay test method according to claim 1, wherein the delay test is performed based on a test pattern to which timing information for observing an expected output value is added.