JP2001201543A - Recording medium with scan pass constructing program recorded thereon, constructing method of scan pass, and arithmetic processing system with this scan pass integrated therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the construction of a scan pass to a resistor or memory on an integrated circuit such as FPGA or the like on a user side in a recording medium with scan pass constructing program recorded therein so as to enhance the testing efficiency of a user logic circuit constituted on the integrated circuit and shorten the development period thereof. SOLUTION: A computer reads the definition information of scan pass according to a program (#1-#12), and a scan pass logic of hardware description language level forming the basis of the scan pass to be constructed on the integrated circuit is generated on the basis of scan pass definition information (#13). According to this, a user can easily construct the scan pass to the on-circuit resistor or memory on the integrated circuit such as FPGA or the like on the basis of the scan pass logic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FPGA (Field
Programmable Gate Array) and PLD (Programmable Log
ic Device), a recording medium storing a scan path construction program that is a path for inputting and outputting data to registers and memories on an integrated circuit such as an integrated circuit, a method of constructing a scan path, and an operation incorporating the scan path Related to processing systems, especially CPU and IP (Intellectual Pro
The present invention relates to a technology for improving the efficiency and facilitation of a board test (actual device test) of an integrated circuit composed of (perty) and the like.

[0002]

2. Description of the Related Art Conventionally, an ASIC (Application Specific Application) which is a logic circuit for a specific application including an FPGA and a PLD is known.
In the field of integrated circuits such as (Integrated Circuit), circuits have become larger and more complex with the advancement of circuit functions.
The tests themselves tend to be more complex. Logic circuits constituting these integrated circuits can be classified into a combinational circuit whose output is uniquely determined with respect to an input and a sequential circuit whose output is determined by a function of a past state and an input. Of these circuits, for combinational circuits, a test pattern was automatically created using the D algorithm and random numbers, and this test pattern was used as an input signal to be applied to external terminals of the circuit, and appeared at other external terminals. Test methods for checking output signals have been generalized, but for sequential circuits represented by flip-flop circuits, it is not easy to set or read out the value of the flip-flop arbitrarily, so the D algorithm It is difficult to automatically create a test pattern using a test pattern. Therefore, for the sequential circuit,
The flip-flops in the circuit are designed to operate as a shift register by connecting them in a chain, and the scan function is used to control and observe the value of each flip-flop externally using this shift function during testing. There is one that adopts a pass method (for example, see Japanese Patent Application Laid-Open No. H10-143390).

[0003]

However, the test of the conventional scan path method as disclosed in Japanese Patent Application Laid-Open No. H10-143390 described above requires a semiconductor maker to scan flip-flops in a circuit at the design stage. Since it can be realized by creating a configuration, an integrated circuit of a method in which a user can create a desired user logic circuit at hand by writing arbitrary logic at a development site, such as an FPGA or a PLD Therefore, such a circuit cannot be verified by a PC (Personal Computer) or EWS (Engineerin
g Work Station), mainly for logic simulation and timing simulation. For this reason, the test of the user logic circuit incorporated in the FPGA or PLD cannot be efficiently performed, and there is a problem that it takes a long time to develop the user logic circuit on the FPGA or PLD.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a user can easily construct a scan path for registers and memories on an integrated circuit such as an FPGA on a user side. In this way, the recording of the scan path construction program which can efficiently perform the test of the user logic circuit formed on the integrated circuit and can shorten the development period of the user logic circuit It is an object to provide a method for constructing a medium and a scan path. Also, without increasing the scale of a logic circuit on an integrated circuit such as an FPGA,
An object of the present invention is to provide an arithmetic processing system capable of obtaining a core function. Still another object of the present invention is to provide an arithmetic processing system capable of controlling a plurality of CPU cores having different language specifications.

[0005]

In order to achieve the above object, according to the first aspect of the present invention, a scan path which is a data input / output path to a register or a memory on an integrated circuit such as an FPGA is integrated by a computer. A recording medium recording a program for constructing on a circuit, the program causing a computer to read definition information of a scan path, and a hardware description as a basis of the scan path to be constructed on an integrated circuit. The scan path logic at the language level is generated based on the scan path definition information.

In the above configuration, the program causes the computer to read the definition information of the scan path,
The logic of the scan path at the hardware description language level, which is the basis of the scan path built on the integrated circuit,
Generated based on scan path definition information. Thus, the user can easily construct a scan path for a register or a memory on the circuit on an integrated circuit such as an FPGA based on the logic of the scan path.

Further, the program further causes the computer to read descriptive information in Bacchus notation regarding the connection relationship between the logic of the generated scan path and the logic such as a controller for controlling the scan path. It is desirable to generate a hardware description language level connection file for the connection relationship based on the information. Thereby, the circuit of the scan path and the circuit such as the controller can be easily connected based on the connection file.

According to a third aspect of the present invention, there is provided a method for constructing a scan path, which is a path for inputting and outputting data to a register and a memory on an integrated circuit such as an FPGA, on the integrated circuit by a programmed computer. So,
Inputting scan path definition information, and generating, based on the scan path definition information, logic of a hardware description language level scan path based on the scan path to be built on the integrated circuit. It consists of According to this method, the same operation as the first aspect of the invention can be obtained.

A step of inputting descriptive information in Bacchus notation for a connection relationship between the generated scan path logic and logic such as a controller for controlling the scan path, and based on the descriptive information, Generating a hardware description language level connection file for the connection relationship of In this way,
The same operation as described above can be obtained.

According to a fifth aspect of the present invention, there is provided an arithmetic processing system comprising an integrated circuit such as an FPGA, a computer, and an interface device for mediating data transmission therebetween. A data path for performing arithmetic processing with a predetermined data width and a scan path for this data path are provided, and the computer is provided with a function of controlling this data path. And data transmission between the data path.

In this configuration, the computer transmits a control code to the data path provided on the integrated circuit through the scan path and the interface device, thereby performing arithmetic processing on the data path on the integrated circuit. Can be executed. That is, the same processing as that of the conventional CPU core can be performed by using the data path arithmetic function on the integrated circuit side and the data path control function on the computer side.

According to a sixth aspect of the present invention, there is provided an arithmetic processing system comprising a plurality of integrated circuits having a CPU core, a computer, and an interface device for mediating data transmission therebetween. The computer transmits a control code for each CPU core on a plurality of integrated circuits via the scan path and the interface device by constructing a scan path for each CPU core on the integrated circuit on the integrated circuit. Is what you do.

In this configuration, since the computer transmits the control code to each of the CPU cores on the plurality of integrated circuits through the scan path and the interface device, for example, each of the CPU cores can be recognized from the computer side. By transmitting such a control code, a single computer can control a plurality of CPU cores having different language specifications.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a scan path constructed using a program recorded on a recording medium according to an embodiment of the present invention and an interface system created using the scan path will be described with reference to the drawings. I will explain. FIG. 1 shows an outline of an interface system including a scan path constructed using a program recorded on a recording medium according to the present embodiment. This interface system 1 is a type of integrated circuit such as an FPGA (Fi
This is for performing an actual test of the user logic circuit on the eld programmable gate array (2). The interface system 1 is a debug module A for a user logic circuit arranged in a part of the FPGA 2.
SH (Adaptive Scan Handler) 3.
PC (Personal Computer) for issuing control commands to ASH3 and displaying command execution results
5 and an interface device (Adaptive Scan Agent Pod: hereinafter referred to as A) for transmitting and receiving data between the ASH 3 and the PC 5 in accordance with the contents of the command sent from the PC 5.
4). Also, in PC5,
Generation of logic for a test path (hereinafter, referred to as a scan path) for the user logic circuit on the FPGA 2 and the logic of the scan path and ASH
A program (scan path construction program in the claims) for creating a connection file regarding the connection relationship with the logic of the various controllers in 3 is stored. This program is CD-RO
This is installed from M7 (recording medium).
The user activates this program to execute a hardware description language level source connection between the logic of the scan path for the user logic circuit and the connection file.
Output file 6. In this embodiment, VHDL (VHSIC Hardware Description) is used as a hardware description language.
Language), the source of the scan path logic output to the source file 6 and the source of the connection file are VHDL sources.

Based on the logic of the source-level scan path output to the source file 6, the FP
The construction and installation of the scan path circuit on the GA 2 are performed. In the following description, the configuration of the interface system 1 and the flow of data after the construction and installation of the scan path circuit on the FPGA 2 are completed, and then the construction of the scan path circuit on the FPGA 2 And the incorporation will be described. FIG. 2 shows a detailed configuration of the interface system 1 after the scan path circuit is constructed and installed. PC5 is the CD-RO of FIG.
Basic logic circuit generation unit 51 storing scan path construction program installed from M7, FPGA
An actual unit control unit 52 for issuing a control command to the ASH 3 at the time of the actual unit test 2; an input unit 53 for inputting data to the basic logic circuit generation unit 51 and giving an instruction to the actual unit control unit 52; A display unit 54 displays the execution result of the control command issued to the ASH 3 by the real machine control unit 52, and a communication driver 55 for communicating with the ASAP 4. The ASAP 4 includes a communication driver 41 for communicating with the PC 5, a controller 42 that analyzes a rough command sent from the PC 5 and issues a detailed command to the ASH 3, and a command received from the controller 42. The TAP controller 43 transmits and receives data to and from the ASH 3 accordingly. The TAP controller unit 43 has a dedicated terminal (not shown) for a boundary scan test called a TAP (Test Access Port), and transmits and receives signals to and from the ASH 3 using this dedicated terminal. The TAP includes TDI (Test Data Input) for inputting data from ASH3, TDO (Test Data Output) for outputting data to ASH3, TMS (Test Mode Select) for setting a test control state,
(Test Clock) for inputting a test clock
And four dedicated terminals.

The FPGA 2 is comprised of the above-described debug module ASH3 and a logic circuit 2 created by a user.
4a, 24b, and 24c. ASH3 is A
The TAP controller 21 for transmitting and receiving signals to and from the TAP controller 43 on the SAP 4 side, and the TAP according to a command issued from the actual device controller 52 of the PC 5
A path controller 22 for switching a path to be connected to the controller 21; and each of the user logic circuits 24a and 24 according to a command issued from the actual device controller 52.
b, fetching data of memory and register in 24c
It is composed of scan paths 23a, 23b and 23c which are test paths for updating. PC5 and A
The data transmission between SAP4 is performed by the RS-232C interface, but the data transmission between ASAP4 and ASH3 is JT for the boundary scan test.
This is performed by the AG interface.

FIG. 3 shows a data flow between each module in the FPGA 2. The TAP controller unit 21
The status is changed based on a TMS signal (not shown) transmitted from the AP 4 (signal output from the TMS terminal described above). And this TAP controller unit 2
In accordance with the status 1, access is made to an instruction register scan path 27 which is a scan path for an IR (Instraction Register) in the main controller 26 or each user logic circuit 2
It is determined whether to access the scan paths 23a, 23b, and 23c for the registers and the memories in 4a, 24b, and 24c. The TAP controller 21 includes a main
When sending a command to the IR in the controller 26,
The TDO signal transmitted from the ASAP 4 (the signal output from the TDO terminal) is output to the instruction register scan path 27 as an IR-TDO signal,
When reading the contents of the IR in the main controller 26, the IR-TDI signal output from the instruction register scan path 27 is read by the TDI.
The signal is transmitted to the ASAP 4 as a signal (input signal to the TDI terminal). When sending serial data to registers and memories in each of the user logic circuits 24a, 24b and 24c, the TAP controller 21 converts the TDO signal transmitted from the ASAP 4 into a DR (Data Register) -TD.
An O signal is output to the scan paths 23a, 23b, and 23c.
When reading the contents of the registers and memories in b and 24c, the DR-TDI signal output from the scan paths 23a, 23b and 23c is transmitted to the ASAP 4 as a TDI signal (input signal to the TDI terminal).

Scans accessible from ASAP4
When switching the paths 23a, 23b, and 23c, the SELECT-SCAN-PATH command issued from the PC 5
Sent to the instruction register scan path 27 via the SAP 4 and the TAP controller 21;
This command is executed by the main controller 26. As a result, a scan path switching signal is transmitted from the main controller 26 to the select scan module 25, and the scan paths 23a, 23b, and 23c accessible from the ASAP 4 (hereinafter collectively referred to as scan paths 23 and 23). ) Is switched. Further, each user logic circuit 24a, 24b, 24c
(Hereinafter, collectively referred to as a user logic circuit 24) and the main controller 26, data is sent to a register or a memory in the user logic circuit 24 through the scan path 23, or the user logic circuit 2
4 is provided with a signal line for a HALT signal for giving an instruction as to whether data in a register or a memory in the memory 4 is to be read.

Next, scan path 2 on FPGA 2
The construction of the third circuit will be described. Scan path 23
Is constructed based on the VHDL level logic of the scan path 23 automatically generated by the basic logic circuit generation unit 51 in the PC 5. This scan path 2
3 will be described with reference to FIG. The user inputs various definition information about the scan path 23 using the input unit 53 of the PC 5 before generating the logic of the scan path 23. That is, the user first sets the number N of scan passes to be created.
Is set (# 1), and thereafter, definition information on N scan paths is input (# 2 to # 12). Specifically, first, the data bit length of each scan path 23 is input (# 4). When the data transmitted from the ASAP 4 can be written to the register or the memory in the user logic circuit 24 via the scan path 23, that is, when the write control is performed (YES in # 5) ), The user may select scan path 23
If the access target is a register (YES in # 6),
As input parameters for generating the VHDL source code of the scan path 23, the definition information of the register scan path with the write control flag (see FIG. 6) is input (# 7). Further, when the access target of the scan path 23 is a memory (NO in # 6), the user specifies a memory scan parameter with a write control flag as a parameter.
The path definition information is input (# 8).

On the other hand, the data transmitted from the ASAP 4 is not written to the register or the memory in the user logic circuit 24 via the scan path 23,
If it is desired that data in a register or a memory in the logic circuit 24 can only be read via the scan path 23, that is, if there is no write control (NO in # 5), the user needs to access When the target is a register (YES in # 9), definition information of a register scan path without a write control flag is input as an input parameter for generating a VHDL source code of the scan path 23 (# 10). When the access target is a memory (NO in # 9), the definition information of the memory scan path without the write control flag is input (#
11). When the user finishes inputting the definition information for all the scan paths 23 (NO in # 3),
Based on the input definition information of each scan path 23, the basic logic circuit generation unit 51 in the PC 5 generates N scan paths 23 and select scan paths corresponding thereto.
A VHDL source code for the module 25 and the main controller 26 is generated (# 13).

Next, the definition processing of each scan path 23 performed in steps # 4 to # 11 will be described in detail with reference to FIGS. As shown in FIG.
The items for defining the path 23 include the following six items. Number of input buses 33 (corresponding to the number of registers or memories readable by each scan path 23) Number of output buses 34 (corresponding to the number of registers or memories rewritable from each scan path 23) Each register (or (Whether write control is used or not) Specifying whether to read data from each register (or memory) Bus width of each input / output bus 33, 34 Scan path The logic of the data unit 31 and the control unit 32 constituting the scan path 23 is generated based on the above-mentioned definition items 1 to specify whether to access a register or a memory. In addition, the number of lines of the we signal output from the control unit 32 is equal to the number of registers or memories that can be written from each scan path 23.

Next, the data format of the scan path 23 automatically generated by the basic logic circuit generator 51 based on the above-mentioned definition items will be described with reference to FIG. As shown in (Example 1) of FIG. 6, when the access target by one scan path 23 is three registers A, B, and C, the scan path 23
It comprises three sets of data areas 11 and write control bits 12 corresponding to the number of bits of each of the registers A, B and C to be accessed. The three write control bits 12 are bits for storing information on whether or not the registers A, B, and C can be rewritten in order from the left, and “c” in each of the write control bits 12 shown in FIG. This indicates that the register corresponding to the write control bit 12 is rewritable. In the case of (Example 1), since the leftmost and rightmost write control bits 12 are “c”, the registers A and C corresponding to the respective write control bits 12 can be rewritten. Each write control bit 1
The value of 2 is actually “1” when writing to the registers A and C is performed, and becomes “0” when only reading data of the registers A and C is performed. Also,
As shown in (Example 2), when only one register D is accessed, the scan path 23 includes one set of the data area 11 and the write control bit 12.

Next, the scan path 23 of the above (Example 2)
Will be described with reference to FIG. 7 and FIG. 8. The values of the definition items to which are input when creating the data, and the logic of the scan path 23 generated based on these definition contents will be described. As shown in these figures, the scan (Example 2)
When the path 23 is created, the number of input buses: 1 The number of output buses: 1 Write: Yes Read: Yes Bus width: 16 bits Scan path access target: Register value is input to each definition item. By defining the scan path 23 as above, as shown in these figures, one input bus DIN and one output bus DOUT having a bus width of 16 bits are generated. In addition, by setting "write-on" in the above and setting 1 as the number of output buses, one terminal for a we signal is generated in the control unit. Furthermore, as shown in these figures, the data section 31 is provided with terminals for inputting UPDATE, CAPTURE, SHIFT, and TCK signals, which are control signals from the TAP controller section 21. FIG.
As shown in the figure, a shift register 35, a temporary storage register 37, and a bus 36 for transmitting data between them are generated in the scan path 23. A terminal for inputting DR-TDO, which is data transmitted from ASAP4 to shift register 35, and an output terminal for DR-TDI, which is data transmitted from shift register 35 to ASAP4, are generated.

Next, a method of incorporating the logic of the scan path 23 created as described above into the user logic circuit 24 will be described. The scan path 23 is incorporated by a method of connecting a register or a memory in the user logic circuit 24 to the scan path 23 via a multiplexer. FIG. 9 shows a method of connecting the scan path 23 and the register 38 in the user logic circuit 24. Din in the figure indicates a bus for inputting data from another register or memory in the user logic circuit 24, and Dout indicates a bus for outputting data to another register or memory in the user logic circuit 24. Is shown. The register 38 has four terminals, of which the D terminal is a terminal for data input from the Din bus,
The terminal is a terminal for data output to the Dout bus, ena
The terminal is a terminal for inputting an enable signal, and the clk terminal is a terminal for inputting a clock signal.

The connection between the register scan path 23 automatically generated by the basic logic circuit generator 51 and the register 38 in accordance with the above-mentioned definition items is connected to the register 38 as shown in the lower part of FIG. The data part 31 of the scan path 23 is set to “1” of the multiplexer 39a.
And the data input bus Din from another register or memory in the user logic circuit 24 is connected to the D terminal of the multiplexer 39a.
Connect to the D terminal of the register 38 via the channel of 0 '. Further, the control unit 32 of the scan path 23 is connected to the ena terminal of the register 38 via the channel “1” of the multiplexer 39b, and a signal line of an enable signal for the register 38 in a mode other than the debug mode (normal mode). Is connected to the ena terminal of the register 38 via the channel “0” of the multiplexer 39b. Furthermore, the output Dout bus from the Q terminal is branched, and the Q terminal and the data section 31 of the scan path 23 are connected. Further, the multiplexers 39a and 39b are provided with HA.
When the LT signal is transmitted, that is, in the debug mode, the channels of the multiplexers 39a and 39b are both set to '
1 ', and conversely, multiplexers 39a, 39
When the HALT signal is not sent to b, that is, in the normal mode, both the channels of the multiplexers 39a and 39b are set to be switched to "0".

By connecting the scan path 23 and the register 38 as described above, in the debug mode, the we signal is sent from the control unit 32 of the scan path 23 to the ena terminal of the register 38, 23 is a multiplexer 39
a, and the contents of the register 38 are supplied from the Dout terminal to the scan path 2.
3 and other memories and registers in the user logic circuit 24. On the other hand, in the normal mode, a load signal is sent to the ena terminal of the register 38, and input data from another register or memory in the user logic circuit 24 is transferred to the register 38 via the Din bus and the multiplexer 39a. And the contents of this register 38 are supplied from the Dout terminal to the user logic circuit 2.
4 to other memories and registers.

Next, referring to FIG.
A method of connecting the memory 3 to a memory in the user logic circuit 24 will be described. The memory 40 has five terminals,
Among them, the Adr terminal is a terminal for inputting addresses of other memories and registers in the user logic circuit 24, the Din terminal is a terminal for inputting data from other memories and registers in the user logic circuit 24, and the we terminal is A terminal for inputting a write enable signal, a clk terminal is a terminal for inputting a clock signal, and a Dout terminal is a user logic circuit 24
This is a terminal for outputting data to other memories and registers. To connect the scan path 23 automatically generated by the basic logic circuit generation unit 51 to the memory 40, FIG.
As shown in the “After installation” below,
The bit of the address area 31a in the data section 31 of the path 23 is connected to the Adr terminal of the memory 40 via the channel "1" of the multiplexer 39c, and the address bus for other memories and registers in the user logic circuit 24 is connected. Is connected to the Adr terminal of the memory 40 via the '0' channel of the multiplexer 39c. Also, the bit of the data area 31b in the data section 31 of the scan path 23 is connected to the Din terminal of the memory 40 via the channel “1” of the multiplexer 39d, and the user logic circuit 2
4 is connected to the Din terminal of the memory 40 via the channel "0" of the multiplexer 39d. Furthermore, the control unit 32 of the scan path 23 is connected to the multiplexer 3
9e is connected to the WE terminal of the memory 40 through the channel of “1”, and the write / write operation to the memory 40 in the normal mode is performed.
The signal line of the enable signal is connected to the multiplexer 39e.
It is connected to the we terminal of the memory 40 via the channel 0 '. Also, multiplexers 39c, 39d, and 39e receive H
When the ALT signal is sent, that is, in the debug mode, all the channels of the multiplexers 39c, 39d, and 39e are switched to "1".
When the HALT signal is not sent to 9c, 39d, and 39e, that is, in the normal mode, the multiplexer 39
The setting is made so that the channels c, 39d and 39e are all switched to '0'.

Since the scan path 23 and the memory 40 are connected as described above, the control unit 32 of the scan path 23 transmits the memory 40 during the debug mode.
Signal is sent to the we terminal of the scan path 23.
Of the data area 31b of the multiplexer 39
d, the same data is written to the area on the memory 40 corresponding to the address of the address area 31a, and the same data is transferred from the Dout terminal of the memory 40 to another register or memory in the user logic circuit and the scan path 2
3 and sent to. On the other hand, in the normal mode, a we signal is sent to the we terminal of the memory 40, and the data sent from the data bus is transferred via the multiplexer 39d to the memory 40 corresponding to the address sent from the address bus. And the same data is sent from the Dout terminal of the memory 40 to another register or memory in the user logic circuit and the scan path 23.

Next, referring to the flowchart of FIG. 11, the scan path 23 incorporated in the user logic circuit 24 by the above-described method and the VHDL format select scan module generated in # 13 of FIG. 2
5 and a method of connecting the main controller 26 will be described. When the user completes the incorporation of each scan path 23 into the user logic circuit 24 (# 2)
1), the scan path 23 and the select scan
The connection relationship between the module 25 and the main controller 26 is defined by using the Backus-Cath notation (# 22).

That is, as a result of the VHDL code generation processing of # 13 in FIG. 4, as shown in FIG. 12, input / output terminals 71 to 76 corresponding to the scan paths 23a, 23b and 23c, Logic circuits 24a, 24
b, 24c, corresponding to the control signal (HALT signal) input terminals 77 to 79, select scan
Each scan path 23a, 23b,
The input / output terminals 61 to 66 for the scan path 23a, 2c and the scan path 23a, 2
Since VHDL format codes corresponding to the control signal output terminals 67 to 3b and 23c are generated, the user uses the codes of these terminals to create a source describing the connection relationship between the terminals. The basic logic circuit generation unit 51 of the PC 5 has a source compiler described in the Bacchus notation, and when a user inputs a source created in the Bacchus notation, the source of the connection relation described above is used by using the compiler. Of the scan path 23, the select scan module 25, and the main controller 26 in the VH
A top-level connection file in the DL format is generated (# 23).

Next, the user operates the scan path 23 incorporated in the user logic circuit 24 by the method shown in FIGS. 9 and 10, and the VHD generated in # 13 of FIG.
L-format select scan module 25 and main controller 26, and VHD created in # 23 above
Based on the L-level top-level connection file,
After performing logic synthesis, logic simulation, placement and wiring design, etc. of the ASH3 including the scan path 23 together with the user logic circuit 24, the user
The logic circuit 24 and the ASH 3 are mounted on the FPGA 2. This mounted FPGA2 is connected to PC5 and ASAP4.
To the input unit 53 of the PC 5 (# 24).
Then, a control command is issued from the actual device control unit 52 to the ASH 3 in the FPGA 2 using the command, and online debugging (actual device test) of the user logic circuit 24 can be performed (# 25).

Next, details of the above-mentioned online debugging will be described. The actual machine control unit 52 includes a debugger. When this debugger is started, the display unit 54 of the PC 5
The debugger screen is displayed above. From this debugger screen, the user can set a break point for the user logic circuit 24 such as a CPU core, refer to data in the register 38 or the memory 40 on the user logic circuit 24, and perform a test operation for the register 38 or the memory 40. Data input settings can be made. That is, the user can use the debugger to execute ASA from the PC 5 side.
FPGA2 via P4 and the circuit of scan path 23
The values of the register 38 and the memory 40 of the user logic circuit 24 on the side can be arbitrarily controlled and observed.

As described above, according to the interface system 1 constructed using the program recorded on the recording medium according to the present embodiment, the basic logic circuit generation unit 51 of the PC 5 executes the scan path definition defined by the user. Scan path 23 in VHDL format according to information, select
Scan module 25 and main controller 2
6 and VHDL about these connection relations
Since the top-level connection file is generated in the format, the user can set the scan path 23 to the register 38 and the memory 40 in the user logic circuit 24 on the FPGA 2 based on the logic of the VHDL level.
Can be easily constructed, and the circuit of the scan path 23 can be easily incorporated in the data transmission path from the PC 5 to the register 38 and the memory 40 on the FPGA 2.
As a result, P
Since the values of the register 38 and the memory 40 on the FPGA 2 can be arbitrarily controlled and observed from the C5 side, the FPGA
2, the actual test of the user logic circuit 24 configured above can be efficiently performed, and the development period of the user logic circuit 24 can be shortened.

Next, an arithmetic processing system created using the scan path 23 according to the present embodiment will be described with reference to FIGS. As shown in FIG. 13, the interface system 1 including the scan path 23 according to the present embodiment generates a control command according to an algorithm created by a user, and transmits the control command to a register group in the FPGA 2 via ASAP4 and ASH3. Since the data can be transmitted to the R and the memory group M, by utilizing the interface system 1, the CPU core and the IP (Intellec
Tual Property) can be remotely controlled from the PC 5. By applying this function, as shown in FIG.
A control function (a function of the conventional microcontroller 82) for a data path (general term of circuits for performing arithmetic processing with a predetermined data width such as an ALU or an adder) 83 or the like which is necessary when An arithmetic processing system 80 ported to software (CPU core control unit 87) on the PC 5 can be realized. The arithmetic processing system 80 receives a signal from the CPU core control unit 87 on the PC 5 via the ASAP4 and the ASH3.
By transmitting and receiving the microcode as a packet with respect to the data path 83 on the PGA 2, arithmetic processing by the data path 83 is enabled. In the conventional CPU core 81, when the algorithm is complicated, the logic scale of the microcontroller 82 is the largest. However, this arithmetic processing system 80 provides the PC 5 with a control function such as the data path 83 by the microcontroller 82. FPGA due to the complexity of the algorithm because it was ported
2 can suppress an increase in the logic scale of the CPU core 81.

Next, another arithmetic processing system created by using the interface system 1 according to the present embodiment will be described with reference to FIGS. The arithmetic processing system 80 includes a plurality of CPU cores 81a to 81d having different language specifications arranged on the plurality of FPGAs 2a to 2d.
Is provided for each of the CPU cores 81a to 81d from the PC 5 through the scan path, thereby transmitting a plurality of CPU cores 8 via the scan path.
1a to 81d are controlled. FIG.
Arranges ASH3 on one FPGA 2a,
FIG. 16 shows a connection method in a case where a plurality of CPU cores 81a to 81d on separate FPGAs 2a to 2d are controlled from a PC 5 via an SH3. FIG. ASH3a
To 3d connected in a chain, and each FPGA 2a to 2d
CPU cores 81a to 81d in the same FPGA
The connection method when controlling from the PC 5 via the SHs 3a to 3d is shown. The PC 5 sends a control command in the form of a meta-language (interpreted language) to each of the CPU cores 81a-81d.
a to 81d can be controlled. Also, PC5 is
IPs 85a to 85d (hereinafter referred to as I
Since it is possible to directly access the internal memory and the register alone (referred to as P85), it is also possible to control the IP85 having a built-in register interface and to control the IP85 via the memory.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, the present invention is applied to an FPGA,
The present invention may be applied to another integrated circuit such as a PLD (Programmable Logic Device). In the above embodiment,
The user has created the definition information about the connection relation between these parts by a method of describing the connection relation of each terminal of the scan path, the select scan module, and the main controller using the Backus-Cass method. The terminal of the scan path, the select scan module, and the main controller are displayed on the screen by the basic logic circuit generation unit of the PC, and the user connects these terminals using a drawing tool or the like. Depending on the method, the definition information of the connection relation between these components may be created. In the above embodiment, a general user
Establish a scan path in the logic circuit and allow the user logic circuit to go online through this scan path.
Although the debugger has been described, the target of online debugging may be a CPU core.

[0037]

As described above, according to the first aspect of the present invention,
A program causes a computer to read the definition information of the scan path, and perform a scan at a hardware description language level on which the scan path to be built on the integrated circuit is based.
The path logic is generated based on the scan path definition information.
Based on the logic of the path, a scan path for a register or a memory on the circuit can be easily constructed on an integrated circuit such as an FPGA. This allows the computer to arbitrarily control and observe the values of the registers and memories on the integrated circuit from the computer through this scan path, so that the actual test of the user logic circuit on the integrated circuit can be efficiently performed. In addition, the development period of the user logic circuit can be shortened.

According to the second aspect of the present invention, the program causes the computer to read descriptive information on the connection relationship between the logic of the scan path and the logic of the controller or the like that controls the scan path by the Bacchus symbolic method. Then, based on this description information, a connection file at the hardware description language level for these connection relationships is generated, so that the user can scan the circuit and controller of the scan path based on this connection file. And other circuits can be easily connected. This makes it possible to easily incorporate a scan path circuit into a data transmission path from a computer to a register or a memory on an integrated circuit.

According to the third aspect of the present invention, the step of inputting the definition information of the scan path and the logic of the scan path at the hardware description language level which is the basis of the scan path built on the integrated circuit And a step of generating the same based on the scan path definition information, so that the same effect as the first aspect of the invention can be obtained.

According to the fourth aspect of the present invention, a step of inputting descriptive information by the Bacchus symbolic method regarding the connection relationship between the generated logic of the scan path and the logic such as a controller for controlling the scan path. And a step of generating a hardware description language level connection file for these connection relationships based on the description information, thereby obtaining an effect equivalent to that of the invention described in claim 2 above. Can be.

According to the fifth aspect of the present invention, a data path for performing arithmetic processing with a predetermined data width and a scan path for the data path are provided on the integrated circuit side, and the data path is provided on the computer side. With the ability to control
Since the data is transmitted between the computer and the data path via the scan path and the interface device, the data path arithmetic function of the integrated circuit and the data path control function of the computer are used. Conventional CP
The same processing as that of the U core can be performed. This allows
The function of the CPU core can be obtained without increasing the scale of the logic circuit on the integrated circuit.

According to the invention of claim 6, the computer transmits the control code for each CPU core on the plurality of integrated circuits via the scan path and the interface device. By transmitting a control code recognizable by each CPU core from the computer, a single computer can control a plurality of CPU cores having different language specifications. Also, an interpreted language may be used for the control code transmitted from the computer to each CPU core. Thus, a plurality of CPU cores having different language specifications can be controlled by a common control code.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating an interface system including a scan path constructed using a program recorded on a recording medium according to an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of the interface system.

FIG. 3 is a diagram showing a data flow between modules in an FPGA of the interface system.

FIG. 4 is a flowchart showing input processing of scan path definition information and generation processing of each module in the ASH based on the input definition information.

FIG. 5 is a diagram showing a scan path definition process.

FIG. 6 is a diagram showing a data format of a scan path automatically generated based on definition information.

FIG. 7 is a diagram showing the logic of the scan path.

FIG. 8 is a diagram showing the logic of the scan path in functional block units.

FIG. 9 is a diagram showing a connection method between the scan path and a register in a user logic circuit.

FIG. 10 is a diagram showing a connection method between the scan path and a memory in a user logic circuit.

FIG. 11 is a flowchart showing a method for connecting the scan path, select scan module, and main controller to enable online debugging.

FIG. 12 is a diagram showing connection terminals of the scan path, the select scan module, and the main controller.

FIG. 13 is a diagram showing a basic connection method of the interface system including the scan path.

FIG. 14 is a diagram showing an arithmetic processing system created by using the scan path.

FIG. 15 is a diagram showing another arithmetic processing system created using the scan path.

FIG. 16 is a diagram showing a modified example of another arithmetic processing system created using the scan path.

[Explanation of symbols]

2 FPGA (Integrated Circuit) 4 ASAP (Interface Device) 5 PC (Computer) 7 CD-ROM (Recording Medium Recording Scan Path Construction Program) 23 Scan Path 25 Select Scan Module (Controller) 26 Main Controller (controller) 38 Register 40 Memory 51 Basic logic circuit generator (scan path construction program) 80 Arithmetic processing system 81, 81a, 81b, 81c, 81d CPU core 83 Data path

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kenji Mogi 1-4-16 Higashitenma, Kita-ku, Osaka-shi Inside Roland Co., Ltd. (72) Inventor Toshimitsu Nakao 1-4-16 Higashitenma, Kita-ku, Osaka-shi No. F-term in Laurent Co., Ltd. (reference) 2G032 AA02 AA07 AB20 AC10 AE12 AG02 AK16 5B048 AA20 AA21 CC18

Claims (6)

[Claims] 1. A recording medium recording a program for constructing, on an integrated circuit, a scan path, which is a path for inputting and outputting data to and from a register and a memory on an integrated circuit such as an FPGA by a computer. The program causes the computer to read the scan path definition information, and converts the logic of the hardware description language level scan path based on the scan path to be built on the integrated circuit into the scan path definition information. A recording medium storing a scan path construction program, wherein the program is generated on the basis of the scan path construction program. 2. The program further reads, into the computer, descriptive information in Bacchus notation about a connection relationship between the logic of the generated scan path and a logic such as a controller that controls the scan path. And generating a connection file at a hardware description language level for the connection relationship based on the description information.
A recording medium on which a path construction program is recorded. 3. A method for constructing, on an integrated circuit, a scan path, which is a path for inputting / outputting data to / from a register or a memory on an integrated circuit such as an FPGA, by using a programmed computer. Inputting the definition information of the scan path, and generating the scan path logic of a hardware description language level based on the scan path to be built on the integrated circuit based on the scan path definition information. A method for constructing a scan path. 4. A step of inputting descriptive information in Bacchus notation for a connection relation between the logic of the generated scan path and a logic such as a controller that controls the scan path, based on the descriptive information. 4. The method according to claim 3, further comprising: generating a connection file at a hardware description language level for the connection relationship. 5. An arithmetic processing system comprising an integrated circuit such as an FPGA, a computer, and an interface device for mediating data transmission therebetween, wherein an arithmetic operation is performed on the integrated circuit with a predetermined data width. A data path for processing and a scan path for this data path are provided, and the computer is provided with a function of controlling this data path, and the computer and the computer are connected to each other via the scan path and the interface device. An arithmetic processing system for transmitting data to and from a data path. 6. A plurality of integrated circuits having a CPU core,
An arithmetic processing system comprising a computer and an interface device for mediating data transmission therebetween, wherein a scan path for each CPU core on the plurality of integrated circuits is constructed on each integrated circuit. An arithmetic processing system, wherein the computer transmits control code to each of the CPU cores on the plurality of integrated circuits via the scan path and the interface device.