JPH07120945B2 - Automatic mode switching PLL circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic mode switching PLL (phase locked loop) circuit used in a frequency synthesizer or the like.

2. Description of the Related Art FIG. 2 shows the configuration of a conventional 2-mode PLL circuit.
In FIG. 2, reference numeral 1 is a reference oscillator, the output of which is input to the frequency divider 2 and the output of the frequency divider 2 is added as the reference input of the digital phase comparator 3. The two outputs, phase lag and lead, of the phase comparator 3 are input to the charge pump 4, and the phase lock signal from the phase comparator is also output.
10 is a control signal for the switch 5. The output of the charge pump 4 is input to the low-pass filter 7, and the characteristics of the low-pass filter 7 can be changed by the switch 5. The output of the low-pass filter 7 is input to the voltage controlled oscillator 6, and the output of the voltage controlled oscillator 6 is used as the output 9 and at the same time input to the frequency divider 8.
The output of the frequency divider 8 is input to the comparison input of the phase comparator 3.

Next, the operation of the above conventional example will be described. In FIG. 1, a phase-locked loop circuit that is normally used except for the switch 5 is used, in which the oscillation frequency of the reference oscillator 1 is f _R ,
If the frequency division ratio of the frequency divider 2 is M and the frequency division ratio of the frequency divider 8 is N, the frequency f _O of the output 9 is It is represented by.

Further, here, the frequency dividers 2 and 8 are variable frequency dividers, and the output frequency f _O can be changed by changing the values of N and M. The characteristic of this loop can be represented by the loop gain and the transfer characteristic of the low-pass filter 7. When the RC filter as shown in FIG. 1 is used as the low-pass filter 7, the loop becomes a secondary loop.

At this time, if the power supply voltage of the charge pump is Vp and the modulation sensitivity of the VCO is Kv, the PLL response is determined by ωn (natural frequency)
And ζ (damping coefficient) are expressed by the following equations.

From this, if R ₂ is shorted by the switch 5, ωn becomes large, and the natural frequency of the PLL rises, so that the response of the system becomes faster. Therefore, if the switch 5 is turned on by the phase lock signal 10 when the PLL is not locked, the synchronous pull-in of the PLL is realized more quickly. Further, when locked, the switch 5 is open and ωn becomes small, which is advantageous in terms of noise suppression and stability. By switching the filter characteristics in this way, it is possible to achieve both high-speed rising and high noise suppression characteristics.

Problems to be Solved by the Invention However, in the above-described conventional two-mode PLL circuit, since the transfer function of the filter 7 is changed by the switch 5 depending on the mode, it is necessary to externally attach the switch 5 when making the circuit into an IC. However, there is a drawback that it is difficult to miniaturize the circuit.
In addition, the switch 5 has a drawback that the voltage-controlled oscillator 6 is easily disturbed.

Further, since the switch 5 is necessary, the configuration including the control circuit becomes complicated.

The present invention solves such a conventional drawback.
Excellent automatic mode switching PL that is suitable for systemization and does not give disturbance
The purpose is to provide an L circuit.

Means for Solving the Problems In order to solve the above problems, the present invention is provided with two switching transistors and a time constant circuit which respectively operate depending on whether the polarity of the phase difference pulse is positive or negative. When the pulse width of is large, the drive current of the charge pump is switched to a large current.

Operation According to the present invention, therefore, there is no need for a switch for switching the drive current of the charge pump in accordance with the mode switching of the PLL circuit, and there is an effect that the mode switching is automatically performed.

Practical Example FIG. 1 is a diagram showing the configuration of a charge pump according to an embodiment of the present invention. In the figure, 14 is a charge pump, T ₁ , T ₂
Is a PNP switching transistor, T ₃ and T ₄ are NPN switching transistors, R _{1 to} R ₄ are resistors, C ₁ and C ₂ are capacitors, and (a) and (b) are phase difference pulses from the phase comparator 3. Input terminals (a) and (b) receive negative and positive pulses, respectively. (C) is a terminal for output pulse to VCO6, and V _CC and V _E are power supplies. For the negative pulse from the terminal (a), the switching transistor T ₁ ,
T _2, resistances R _1, R _2, a capacitor C ₁ is concerned, to the base of the switching transistor T ₁ is an input terminal (a), also between the emitter and the power supply V _CC of the switching transistors T ₁ resistors R _1, R ₂ is connected, and the connection point between the resistors R ₁ and R ₂ is connected to the base of the switching transistor T ₂ and, in parallel with the resistor R _1, both the capacitor C ₁ and the base and emitter of the switching transistor T ₂ are connected. . Switching transistor for positive polarity pulse from terminal (b)
T _3, T ₄ and the resistance R _3, R ₄ and the capacitor C ₂ is similar connected with the collector comrades of the switching transistor T ₁ through T ₄ are commonly connected extracting an output from the output terminal (c), resistance
Low-pass filter consisting of R ₀ and capacitor C ₀ connected in series
17 is designed to be inserted between the ground. The same reference numerals as those in FIG. 2 represent the same names.

Next, the operation of the above embodiment will be described. 2 is the same as the conventional example except that the charge pump 4 in FIG. 2 is replaced by 14 and the low-pass filter 7 is replaced by 17, and the phase lock signal 10 is omitted. Therefore, the operation will be described with reference to FIG. The phase comparator 3 compares the frequencies of the reference oscillator 1 and the VCO 6 with the outputs of the fixed frequency divider 2 and the variable frequency divider 8. If the phases are delayed, pulses (a) to (-) are generated.
When the phase of the variable frequency divider 8 is ahead of the fixed frequency divider 2, pulses (b) to (+) are generated. In either case, the larger the phase difference, the wider the pulse width. When there is no input from the phase comparator 3 to the input terminals (a) and (b), no current flows through the transistors T _{1 to} T ₄ and the output terminal (c)
Is held at a potential determined by the charge of the capacitor C ₀ . Next, when a phase delay occurs and, for example, a negative polarity pulse is input to the input terminal (a), the switching transistor T ₁ is turned on during the pulse application period, and the output terminal (c) outputs the low-pass filter 17 The capacitor C ₀ is charged with a positive potential. Switching transistor at the same time
The emitter current i of T ₁ causes a voltage drop due to the resistor R ₁ , and this potential difference charges the capacitor C ₁ . The base voltage of the switching transistor T ₂ decreases as the width of the negative polarity pulse applied to the input terminal (a) becomes wider, and the switching transistor T ₂ is turned on when it becomes a predetermined value or less. The operating current when the switching transistor T ₂ is ON is added to the output current of the output terminal (c). The operating current can be sufficiently large, so that the larger the phase delay, the larger the rate of increase in the potential of the output terminal (c). The same operation is performed when a positive pulse is input to the input terminal (b).

According to the above embodiment, the drive current of the charge pump 14 can be automatically controlled according to the magnitude of the phase difference pulse.

Effects of the Invention According to the present invention as described in the above embodiments, the PLL
Since the drive current of the charge pump of the circuit is automatically controlled by using the charge pumps having the first and second switching transistors and the time constant circuit, the automatic mode switching is performed without using the changeover switch. PL
An L circuit can be configured, and as a result, it has an advantage that the response of the PLL loop system can be made variable by a relatively simple configuration suitable for an IC.

[Brief description of drawings]

FIG. 1 shows an automatic mode switching PLL according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the main configuration of the circuit, and FIG.
FIG. 3 is a block diagram of an entire PLL circuit. T ₁ ~T ₄ ...... switching transistors, R ₁ ~R ₄ ...... resistors, C _1, C ₂ ...... capacitor, a, b ...... input terminal, c ...... output terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03L 7/18 H03L 7/10 E 7/18 Z

Claims (1)

[Claims] 1. A digital phase comparator, a charge pump driven by a pair of positive and negative phase difference pulse outputs of the phase comparator, and an output of the charge pump through a low-pass filter. A first NPN switching transistor used in a phase-locked loop circuit having a controlled voltage controlled oscillator, the charge pump driving the base by the positive polarity phase difference pulse, and the base by the negative polarity phase difference pulse. When a first PNP switching transistor to be driven is provided, the collectors of the switching transistors are connected in series at a common connection point, and a resistor and a capacitor are connected in parallel between the emitter of the first PNP switching transistor and a power supply. Connect a constant circuit via a resistor to connect the first NPN switching transistor. A time constant circuit in which a resistor and a capacitor are connected in parallel is connected between the emitter of the star and ground, and the connection point between the resistor on the emitter side of the 1 NPN switching transistor and the time constant circuit is the base, and the emitter is A second NPN switching transistor whose collector is connected to the common connection point and a connection point between the resistor on the emitter side of the first PNP switching transistor and the time constant circuit are bases, and the collector is a power supply. And a second PNP switching transistor whose collectors are connected to the common connection point respectively so that the charge pump output is taken out from the common connection point, and the second PNP switching transistor is provided only when the phase difference pulse width is wide.
Automatic mode switching PLL circuit that turns on the switching transistor of.