JPS6155825B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal synchronization circuit for synchronizing the horizontal deflection operation of a television receiver with a horizontal synchronization signal.

Such a horizontal synchronization circuit is generally configured to perform PLL (phase locked loop) control of a horizontal oscillation circuit using a horizontal synchronization signal as a reference signal.
In such a circuit, in order to achieve synchronization in a short time and to avoid malfunctions due to noise etc. in the synchronized state, the sensitivity of the phase detection stage that detects the phase error of the oscillation circuit should be adjusted to an asynchronous state. It is necessary to switch in a synchronous state.

Therefore, a circuit to detect the synchronization state of the horizontal synchronization circuit is required, but conventional detection circuits of this type directly guide the received horizontal synchronization signal to the detection circuit, and detect the phase difference between the horizontal synchronization signal and the horizontal flyback pulse. I'm trying to find a match.

However, since there is a high probability that noise will appear in the back porch of the horizontal synchronization signal, the above-described configuration has the disadvantage that the detection circuit malfunctions due to this noise, making it impossible to accurately detect the synchronization state of the horizontal synchronization circuit. It was hot.

Therefore, the present invention has been made to eliminate such drawbacks, and details thereof will be explained below with reference to the drawings.

FIG. 1 shows a schematic configuration of a horizontal synchronization circuit to which the present invention is applied. In the same figure, 1 is AFC
(automatic frequency control) circuit, 2 is an APC (automatic phase control) circuit, and 3 is a horizontal deflection section.

The AFC circuit 1 basically includes a gate circuit 4 that allows the output of a synchronization separation circuit (not shown) to pass through only a minute period including a horizontal synchronization signal period, and a horizontal synchronization pulse (HP) derived from this gate circuit.
A first phase detection circuit 5 detects a phase difference between the output pulse of a frequency dividing circuit to be described later, a first low-pass filter 6 smoothes the detected output, and a ceramic resonator. a VCO (voltage controlled oscillator) 7 whose oscillation frequency is determined by the output voltage of the filter 6;
It is composed of a frequency dividing circuit 8 that divides the frequency of the oscillation output. Here, the oscillation frequency of the VCO 7 is selected to be approximately n (integer) times the horizontal frequency (H) of the television, and the pulse obtained by dividing this oscillation output by 1/n in the frequency dividing circuit 8 is the first pulse. It should be noted that the signal is guided to the phase detection circuit 5.

On the other hand, the APC circuit 2 includes a second APC circuit that detects the phase difference between the 1/n frequency divided pulse from the frequency dividing circuit 8 and the flyback pulse (FP) taken out from the horizontal output circuit in the horizontal deflection section 3. A phase detection circuit 9 and a second low-pass filter 10 that smoothes the detection output thereof.
and a variable phase shift circuit 11 that changes the phase of the 1/n frequency divided pulse according to the DC voltage obtained from this filter and guides it to the horizontal trigger circuit 12 in the deflection section 3 . It should be noted here that the time constant of the second low-pass filter 10 is selected to be sufficiently smaller than that of the first low-pass filter 6 described above.

Further, 14 obtains the horizontal synchronizing pulse (HP) and the horizontal flyback pulse (FP) to determine whether the receiver is in a synchronized state or not, and thereby switches the gate circuit 4 between operation and non-operation. , the detection sensitivity of the first phase detection circuit 5, and the time constant of the first low-pass filter 6. In the present invention, this circuit is particularly referred to as an H killer circuit.

The H killer circuit 14 performs each of the above-mentioned switches, but first, the switching of the gate circuit 4 will be explained. That is, in the case of so-called video-in-sync, in which the video signal part of the received television signal is transferred to the synchronization signal side due to transmission distortion, etc., this video signal is derived from the synchronization separation circuit.
AFC circuit 1 malfunctions. Therefore, in order to eliminate this malfunction, it is sufficient to gate the output of the synchronization separation circuit so that it passes only during the horizontal synchronization signal period. For this reason, the gate circuit 4 is operated only in a synchronized state in which such a gate pulse (actually, with some margin, corresponds to the horizontal synchronizing signal period and a minute period including the period before and after the horizontal synchronizing signal period). I'm trying to make it work. At this time, the gate pulse is generated by the frequency dividing circuit 8.

Next, the detection sensitivity of the first phase detection circuit 5 and the first
Switching of the time constant of the low-pass filter 6 will be explained. That is, if the sensitivity of the first phase detection circuit 5 is made high and the time constant of the first low-pass filter 6 is selected to be small, the AFC circuit 1 may malfunction due to noise near the horizontal synchronization signal (especially in a weak electric field). Become. Therefore, in order to avoid this malfunction, the detection sensitivity cannot be set too high, and the time constant must be selected relatively large. However, if this is done, it will take a long time to achieve synchronization in an asynchronous state such as when the power is turned on or when switching channels. Therefore, the detection sensitivity is low only in the synchronous state, and
The time constant is switched so that it becomes larger.

In addition, the time constant of the second low-pass filter 10 was selected to be sufficiently small because it is thought that the APC circuit 2 is hardly affected by the above-mentioned noise. This is to enable sufficient tracking of the changing phase of the flyback pulse.

Note that the horizontal trigger circuit 12 is a variable phase shift circuit 11.
The output pulse of the horizontal output circuit 13 is converted into a pulse width suitable for driving the horizontal output circuit 13.

2 and 3 show an embodiment of such a horizontal synchronization circuit, and parts corresponding to those in FIG. 1 are given the same figure numbers. First, in Figure 2,
The oscillation frequency of VCO7 is approximately 32H (center frequency:
504, 11KHz), and therefore, the frequency divider circuit 8 basically consists of five T flip-flops _F1 to _F5 that sequentially divide the frequency of the above oscillation output. It is configured as a circuit.

The 1/32 frequency divided output (frequency: approximately H) from the frequency dividing circuit 8, that is, the output of F ₅ is I ² L (eye square
Semiconductor elements Q ₇ to _{Q 32} are inverted by Q ₂₅ or Q ₂₅ and Q ₂₆ .
It is guided by the bases of Q ₂₇ and Q ₂₈ respectively.

On the other hand, the horizontal synchronization pulse (HP) derived from the synchronization separation circuit (not shown) is transmitted to terminal 1 on the left end of the diagram.
5, is inverted by transistor T ₁₄₅ and element Q ₂₂ , and guided to the bases of Q ₂₇ and Q ₂₈ described above.

Therefore, as can be seen from the time chart in Fig. 4, each base of Q ₂₇ and Q ₂₈ has an AND of the Q output of F ₅ and the horizontal synchronization pulse (HP), or an output of F ₅ and the horizontal synchronization pulse. Pulse corresponding to AND with pulse
P ₁ and P ₂ appear, and each pulse is Q ₂₇ , T ₁₄₉ or
It will be extracted through Q ₂₈ and T ₁₅₀ . These pulses P ₁ and P ₂ are then guided to the first phase detection circuit 5 shown in FIG.

Note that the gate circuit 4 for the horizontal synchronizing pulse (HP) explained in FIG. 1 is composed of _Q11 to _Q21 , which will be described later.

Next, the output of F ₂ of the frequency dividing circuit 8 is Q ₇ , Q ₈
The Q output of F ₃ is inverted at Q ₁₁ and the output of F ₄ is inverted at Q ₉ and Q ₁₀ and guided to point A. Therefore, at point A
A pulse (PA) corresponding to the logical product of the respective outputs of F ₂ , F ₃ , and F ₄ (hereinafter, such a logical product will be expressed as ₂ , _3, and ₄ ) will appear. On the other hand, the output of F ₅ is inverted by Q ₂₅ and Q ₂₆ and guided to point B, where it is ANDed with the previous pulse at point A inverted by Q ₁₅ . Therefore, a pulse (PB) corresponding to ₂ , ₃ , ₄ , and ₅ appears at point B, and this pulse passes through Q ₂₉ or Q ₂₉ and Q ₃₀ .
It is guided by the base of Q ₃₁ and Q ₃₂ .

On the other hand, the horizontal flyback pulse (FP) taken out from the horizontal output circuit 13 in FIG.
After being shaped by a Zener diode (Z ₂ ) and a diode D ₁₃ , it is led to the bases of Q ₃₁ and Q ₃₂ mentioned above through T ₁₄₂ and Q ₂ .

Therefore, the base of Q ₃₁ is the AND of the inverted output of the pulse at point B and the flyback pulse (FP), or the pulse at point B and the flyback pulse (FP).
Pulses P ₃ and P ₄ corresponding to the logical product of will appear, and each pulse will be extracted through Q ₃₁ , T ₁₅₁ or Q ₃₂ , T ₁₅₂ . And these two pulses P ₃ ,
_P4 is led to the second phase detection circuit 9 of FIG.

Further, the output of F ₄ of the frequency dividing circuit 8 is inverted at Q ₉ and guided to point C, and the Q output of F ₃ is inverted at Q ₁₁
and _Q12 , and the output of _F5 is inverted at _Q24 and guided to point C. Therefore, at point C
A pulse _P5 corresponding to _F4 , _F3, and ₅ appears, and this pulse _P5 is led to the variable phase shift circuit 11 of FIG. 3 through _Q13 and _Q14 .

Next, in FIG. 3, the first phase detection circuit 5
are transistors T ₂₁₉ and T ₂₂₀ to which the aforementioned pulses P ₁ and P ₂ taken out from T ₁₄₉ and T ₁₅₀ in FIG. _T216〜
The main elements include a transistor T ₂₁₈ and a transistor T ₂₂₂ for switching detection sensitivity. This first phase detection circuit 5 is equipped with capacitors C ₂ and C ₃ and a resistor R ₃ .
A first low-pass filter 6 consisting of
The voltage smoothed by this filter 6 is shown in Figure 2.
It is applied as a control voltage to VCO7.

Similarly, the second phase detection circuit 9 is configured as shown in FIG.
Transistors T ₂₃₅ , to _which the pulses P ₃ and P ₄ taken out from T 151 and T ₁₅₂ are respectively applied to their bases;
T ₂₃₄ and transistors T ₂₃₀ to _{T 232} constituting a current mirror circuit as main elements, and this second
A second low-pass filter 10 consisting of a capacitor C ₅ and resistors R ₅ and R ₆ is connected to the phase detection circuit 9. The voltage smoothed by this filter 10 is applied to the base of the rightmost transistor _T227 of the variable multiphase circuit 11, which will be described later.

Note that T ₁₆₆ and T ₁₆₈ at the right end of FIG. 3 operate as limiters that limit the potential change at point J in the second phase detection circuit 9 within a predetermined range.

On the other hand, the variable phase shift circuit 11 includes a transistor T ₂₂₁ to which the above-mentioned pulse _{P 5} extracted from Q ₁₄ in FIG _. A transistor T ₂₂₃ that switches charging and discharging of the capacitor C ₄ that creates a sawtooth voltage, and a sawtooth voltage appearing at the emitter of this T ₂₂₃ and the second low-pass filter 10
The main elements are transistors T ₂₂₄ to _{T 227} , which constitute a comparison circuit with the DC voltage obtained from the DC voltage, and transistors T ₂₂₈ and T ₂₂₉ which take out the output pulse of the comparison circuit and guide it to the horizontal trigger circuit 12 .

In addition, the H killer circuit 14 is connected to the terminal 15 in FIG.
positive horizontal sync pulse (HP) from
The AND output (point H) of the burst gate pulse (GP) created at Q ₃ to Q ₆ and T ₁₃₇ (see Figure 4) inverted at T ₁₄₆ is applied to the base of the transistor T. ₁₈₄ , T ₁₈₅ , a transistor T ₁₈₆ which is cascade-connected to this T ₁₈₅ and to which the horizontal flyback pulse (FP) from the terminal ₁₆ in FIG. Transistors T ₁₈₉ to _{T 194} constitute a comparison circuit between the voltage obtained by smoothing with the resistor R ₁ of C ₁ and a constant DC voltage, and switching transistors T ₁₉₅ to _{T 197} respond to the output voltage of this comparison circuit.
It is composed of the main elements. The switching transistor T ₁₉₅ is connected to the base common connection point of Q ₂₁ and Q ₂₂ in FIG. 2 for switching between operation and non-operation of the gate circuit. Further, T ₁₉₆ is connected to the base of T ₂₂₂ for switching the sensitivity of the first phase detection circuit 5. Furthermore, T ₁₉₇ is designed to connect a resistor R ₃ ' for switching the time constant of the first low-pass filter 6 between the midpoint of connection between the capacitor C ₂ and the resistor R ₃ and the ground point.

As mentioned above, the reason why the horizontal synchronizing pulse (HP) is gated with the inverted output of the burst gate pulse (GP) and guided to the H killer circuit is because the noise appearing in the back porch of the horizontal synchronizing signal causes the H killer circuit to This is to prevent malfunction.

One embodiment of the present invention is constructed as described above, and its operation will be explained next.

() AFC operation T ₂₁₉ and T ₂₂₀ of the first phase detection circuit 5 are as shown in Fig. 2.
When the pulses P ₁ and P ₂ from T ₁₄₉ and T ₁₅₀ are not applied, they are off, and only when they are applied, they are turned on and collector currents flow respectively.
At this time, since T ₂₁₆ to _{T 218} constitute a current mirror circuit, if the magnitude of the collector current of T ₂₁₉ is i, a current i of the same magnitude flows through T ₂₁₆ as well.

Here, each pulse width γ ₁ of the above-mentioned pulses P ₁ and P ₂ ,
As can be seen from Figure 4, γ ₂ is a state in which the fall of the 1/32 frequency-divided output of frequency divider circuit 8 (Q output of _F5 ) corresponds to the exact center of the horizontal synchronizing pulse (HP). That is, in the synchronous state, γ ₁ = γ ₂ , and if the phase of the frequency-divided output shifts from this state, γ ₁ < γ ₂ (in the left direction) depending on whether it shifts to the left or right in FIG. ) or γ ₁ > γ ₂ (in the case of right direction)
become.

Therefore, the capacitors C ₂ and C ₃ of the first phase detection circuit 5 have a current amount (i×γ
₁ ) and the amount of current flowing out from this point I (i×γ ₂ )
Since the battery is charged or discharged by the amount corresponding to the difference between
VCO7 is controlled. In the synchronous state, γ ₁ =γ ₂ , that is, the two current amounts are equal, so the potential at point I is held at a constant value and the AFC system becomes stable.

() APC operation The operation of the second phase detection circuit 9 is substantially the same as that of the first phase detection circuit 5 described above. Therefore, the potential at point J of this second phase detection circuit 9 is T ₁₅₁ , T ₁₅₂ in FIG.
The pulse width γ ₃ , γ ₄ of the pulses P ₃ , P ₄ (see Fig. 4) extracted from the horizontal flyback pulse (FP) and the pulse PB generated at point B in the frequency dividing circuit 8
The potential of the variable phase shift circuit 11 increases or decreases depending on the phase difference between the J point and the J point.
The base potential of T ₂₂₇ will change.

On the other hand, T ₂₂₁ of the variable phase shift circuit 11 is Q ₁₄ in Fig. 2.
The pulse appearing at the collector of the horizontal scanning period
Pulse P ₅ located in the center of Ts (see Figure 4)
It turns on only when T 221 arrives, and when T ₂₂₁ turns on, T ₂₂₃ also turns on. Therefore, the capacitor C ₄ for creating the sawtooth voltage is charged with the power supply voltage (+Vcc) via the resistor R ₄ when T ₂₂₃ is off, and discharged when T ₂₂₃ is on. This generates a sawtooth voltage like VC in FIG. 4 at the emitter of T ₂₂₃ , which is applied to the base of T ₂₂₄ .

Therefore, T ₂₂₄ and T ₂₂₅ of the phase shift circuit 11
is turned on only during the period when the sawtooth wave voltage VC exceeds the voltage at point J of the second phase detection circuit 9 applied to the base of T ₂₂₇ , and when T ₂₂₅ is turned on, T ₂₂₈ is turned on. As a result, T ₂₂₉ is also turned on and current flows through the horizontal trigger circuit 12, causing the horizontal trigger circuit 12 to be activated. That is, the variable phase shift circuit 11 determines the activation timing of the horizontal trigger circuit 12 by turning on _T229 . For this reason, the horizontal flyback pulse
When the phase of FP and the output pulse PB of the frequency divider circuit 8 are out of phase, the base potential of _T227 changes, thereby changing the activation timing. In the synchronous state, the base potential of T ₂₂₇ is held at a level approximately 1/2 of the sawtooth voltage VC, and the APC operation becomes stable.

() H killer operation As mentioned above, the horizontal flyback pulse FP of positive polarity is applied from Q ₂ to the base of T ₁₈₆ of the H killer circuit 14, so this T ₁₈₆ is turned off only during the flyback pulse period. This turns T ₁₈₅ off and T ₁₈₇ on. On the other hand, a horizontal synchronizing pulse HP gated with an inverted version of the burst gate pulse GP is applied to the bases of T ₁₈₄ and T ₁₈₅ from point T ₁₄₆ H. For this reason, both the pulses HP and FP
T ₁₈₄ and T ₁₈₇ are turned on at the same time only during the period when the two coincide with each other in time. Therefore, T ₁₈₈ is turned on only during this period, and a charging current flows to the capacitor C ₁ . This capacitor _C1 is discharged through the resistor _R1 , but in the synchronized state, the coincidence of both pulses HP and FP is repeated, so the base potential of _T189 rises, and _T190 , which is held at a constant value, increases. This will exceed the base potential of . Then, T ₁₈₉ turns on and T ₁₉₄ also turns on, thereby turning on each of the switching transistors T ₁₉₅ to _{T 197} .

When T ₁₉₅ of the switching transistor is turned on, the bases of Q ₂₀ and Q ₂₁ in the gate circuit 4 of FIG. 2 are grounded, so that the collector points D and E of Q ₂₀ and Q ₂₁ are respectively Become a high level.
Therefore, the Q output led from F ₃ of the frequency dividing circuit 8 to point D through Q ₁₁ and Q ₁₂ is applied to the base of Q ₁₆ , and the Q output led from F ₄ to point E is applied to Q ₁₈ is applied to the base of Therefore, _a pulse P ₆ corresponding to F ₃ and F ₄ appears at point F, and _a pulse P ₇ corresponding to ₃ and ₄ appears at point G. 4) and the horizontal synchronizing pulse HP passed through Q ₂₂ will be ANDed at the collector of Q ₂₂ . This means that the aforementioned pulses P ₁ and P ₂ guided to the first phase detection circuit 5 are gated, and therefore, the malfunction of the AFC circuit due to video-in-sync explained in Fig. 1 is eliminated. This means that it will be done.

Note that T ₁₈₆ is turned on during periods other than the horizontal flyback period, so if noise is applied to T ₁₈₄ and T ₁₈₅ at this time, T ₁₈₅ is turned on by the noise. Therefore, capacitor C ₁ will be discharged through T ₁₈₅ and T ₁₈₆ . Therefore, the horizontal sync pulse
Even if there is noise in the HP, the H killer will not malfunction due to that noise.

Further, when the switching transistor T ₁₉₆ is turned on, T ₂₂₂ in the first phase detection circuit 5 is turned off, so that R ₂₅₀ connected in parallel with R ₂₅₁ is electrically disconnected. Therefore, T ₂₁₉ ,
The emitter load resistance of T ₂₂₀ is increased and therefore
In the synchronous state, the current flowing through T ₂₁₆ and T ₂₁₉ is smaller than in the asynchronous state. This means that the detection sensitivity in the synchronized state is lower, which eliminates malfunctions of the AFC circuit due to noise and the like.

Further, when the switching transistor T ₁₉₇ is turned on, R ₃ ' is connected in parallel to R ₃ of the first low-pass filter 6. Therefore, the capacitance of capacitor _C2 is apparently larger than in the asynchronous state, and therefore, the potential fluctuation at point I becomes smaller. In other words, this means that the time constant of the first low-pass filter 6 becomes larger in the synchronized state, which makes it more effective against noise, etc. in a weak electric field.
This eliminates the AFC circuit's response.

In addition, up until now, there have been two types of AFC circuits that make an oscillator oscillate at a frequency sufficiently higher than the horizontal frequency and control the frequency of the oscillator according to the phase difference between the frequency-divided output of this oscillator and the horizontal synchronization signal, and Although the explanation has been given by taking as an example a horizontal synchronizing circuit equipped with an APC circuit that shifts the phase of the output according to the phase difference with the horizontal flyback pulse, the present invention is applicable not only to such a special horizontal synchronizing circuit, but also to, for example, It can also be applied to a horizontal synchronization circuit configured as a single AFC or APC circuit that directly controls an oscillator that oscillates at a horizontal frequency using a horizontal synchronization signal as a reference signal.

As explained above, the present invention includes a circuit for controlling AFC or APC of a horizontal oscillator using a horizontal synchronization signal as a reference signal, and a circuit for detecting phase coincidence between the horizontal synchronization signal and a horizontal flyback pulse, and the detection circuit If a phase match is detected in
In a horizontal synchronization circuit that switches the operating state of the AFC or APC circuit, input of the horizontal synchronization signal to the detection circuit is prohibited only during the burst gate pulse period, so that noise appearing in the back porch of the horizontal synchronization signal can be prevented. Therefore, the above-mentioned detection circuit will not malfunction, and therefore the above-mentioned AFC or
The APC circuit operates optimally in both asynchronous and synchronous states.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a horizontal synchronization circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing details of one embodiment thereof, and FIG. 4 is a diagram for explaining the operation of FIG. It is a time chart. 1 ...Horizontal AFC circuit, 2 ...Horizontal APC circuit,
3 ...Horizontal deflection section, 14...H killer circuit.

Claims (1)

[Scope of Claims] 1. A frequency control circuit that controls the frequency of a horizontal oscillator using a horizontal synchronization signal as a reference signal, and a detection circuit that detects a state in which the phases of the horizontal synchronization signal and the horizontal flyback pulse match; In the horizontal synchronization circuit which switches the operating state of the frequency control circuit when the phase coincidence state is detected in the circuit, a gate circuit is provided that prohibits passage of the horizontal synchronization signal only during a burst gate pulse period, A horizontal synchronization circuit characterized in that a horizontal synchronization signal is inputted to the detection circuit through this gate circuit. 2. Claims in which the frequency control circuit is configured to control the frequency of the oscillator according to the phase difference between the divided output of the oscillator that oscillates at a frequency sufficiently higher than the horizontal frequency and the horizontal synchronization signal. The horizontal synchronization circuit described in item 1.