JPS6141193B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal synchronization circuit for synchronizing the horizontal deflection operation of a television receiver with a horizontal synchronization signal.

Such a horizontal synchronization circuit is generally configured to control a horizontal oscillation circuit using a horizontal synchronization signal as a reference signal using PLL (phase locked loop) control, but if the video signal portion of the received television signal is affected by, for example, transmission distortion, etc. Therefore, in the case of so-called video-in-sync, where the video signal is transferred to the synchronization signal side, this video signal is derived from the synchronization separation circuit, which may cause the horizontal synchronization circuit to malfunction and cause screen image shaking. become.

Therefore, the present invention has been made to eliminate such drawbacks, and details thereof will be explained below with reference to the drawings.

FIG. 1 shows a schematic configuration of a horizontal synchronization circuit to which the present invention is applied. In the same figure, 1 is AFC
(automatic frequency control) circuit, 2 is an APC (automatic phase control) circuit, and 3 is a horizontal deflection section.

The AFC circuit 1 basically consists of a gate circuit 4 that allows the output of a synchronization separation circuit (not shown) to pass through only a minute period including a horizontal synchronization signal period, a horizontal synchronization pulse HP derived from this gate circuit, and components described later. A first phase detection circuit 5 that detects the phase difference with the output pulse of the circuit, a first low-pass filter 6 that smoothes the detected output, and a ceramic resonator, the oscillation frequency being determined by the filter characteristics of this resonator. The VCO (voltage controlled oscillator) 7 is controlled by the output voltage of the filter 6, and a frequency dividing circuit 8 divides the frequency of the oscillation output. Here, the oscillation frequency of the VCO 7 is set to approximately n (integer) times the horizontal frequency H of the television, and the pulse obtained by dividing this oscillation output by 1/n in the frequency dividing circuit 8 is the first phase detected. It should be noted that circuit 5 is introduced.

On the other hand, the APC circuit 2 has a second phase detection circuit that detects the phase difference between the 1/n frequency divided pulse from the frequency dividing circuit 8 and the flyback pulse FP taken out from the horizontal output circuit in the horizontal deflection section 3. A circuit 9, a second low-pass filter 10 for smoothing the detection output thereof, and a phase of the 1/n frequency-divided pulse is changed according to the DC voltage obtained from this filter and guided to the horizontal trigger circuit 12 in the deflection section 3 . It is composed of a variable phase shift circuit 11. Here, the time constant of the second low-pass filter 10 is the same as that of the first low-pass filter 6 described above.
It should be noted that this is selected to be sufficiently smaller than that of .

Further, 14 obtains the horizontal synchronizing pulse HP and the horizontal flyback pulse FP to determine whether the receiver is in a synchronized state or not, and thereby switches the gate circuit 4 between operation and non-operation. Detection circuit 5
Detection sensitivity switching and first low-pass filter 6
In the present invention, this circuit is particularly referred to as an H killer circuit.

The H killer circuit 14 performs each of the switching operations described above, but first, switching of the gate circuit 4 will be explained. That is, as mentioned above, the malfunction of AFC circuit 1 in the case of video in sync is caused by the video signal being affected by this AFC circuit.
This occurs by entering the first phase detection circuit 5 in the circuit. Therefore, when the gate circuit 4 is in the synchronized state, it obtains a gate pulse having a pulse width including the horizontal synchronization signal period and the period before and after it from the frequency divider circuit 8 in the AFC circuit, and uses this pulse to control the horizontal synchronization from the synchronization separation circuit. After the pulse HP is gated, it is led to the first phase detection circuit 5.

Next, the detection sensitivity of the first phase detection circuit 5 and the first
Switching of the time constant of the low-pass filter 6 will be explained. That is, if the sensitivity of the first phase detection circuit 5 is made high and the time constant of the first low-pass filter 6 is selected to be small, the AFC circuit 1 may malfunction due to noise near the horizontal synchronization signal (especially in a weak electric field). Become. Therefore, in order to avoid this malfunction, the detection sensitivity cannot be set too high, and the time constant must be selected relatively large. However, if this is done, it will take a long time to achieve synchronization in an asynchronous state such as when the power is turned on or when switching channels. Therefore, the detection sensitivity is low only in the synchronous state, and
The time constant is switched so that it becomes larger.

In addition, the time constant of the second low-pass filter 10 was selected to be sufficiently small because it is thought that the APC circuit 2 is hardly affected by the above-mentioned noise. This is to enable sufficient tracking of the changing phase of the flyback pulse.

Note that the horizontal trigger circuit 12 is a variable phase shift circuit 11.
The output pulse of the horizontal output circuit 13 is converted into a pulse width suitable for driving the horizontal output circuit 13.

2 and 3 show an embodiment of such a horizontal synchronization circuit, and parts corresponding to those in FIG. 1 are given the same figure numbers. First, in Figure 2,
The oscillation frequency of VCO7 is approximately 32H (center frequency:
504, 11KHz), and therefore, the frequency divider circuit 8 basically consists of five T flip-flops _F1 to _F5 that sequentially divide the frequency of the above oscillation output. It is configured as a circuit.

The 1/32 frequency divided output (frequency: approximately H) from the frequency dividing circuit 8, that is, the output of F ₅ is I ² L (eye square
It is inverted by Q ₂₅ or Q ₂₅ and Q ₂₆ in the semiconductor elements Q ₇ to _{Q 32} which operate as inverters called L, and is guided to the bases of Q ₂₇ and Q ₂₈ , respectively.

On the other hand, the horizontal synchronization pulse HP derived from the synchronization separation circuit (not shown) is inverted by the transistor _T145 and the element _Q22 from the terminal 15 at the left end of the figure, and is led to the bases of the aforementioned _Q27 and _Q28 . It will be destroyed.

Therefore, as can be seen from the time chart in Fig. 4, each base of Q ₂₇ and Q ₂₈ has the AND of the Q output of F ₅ and the horizontal synchronizing pulse HP, or the output of F ₅ and the horizontal synchronizing pulse. The pulse P ₁ corresponding to the logical product of
P ₂ appears, and each pulse of this appears Q ₂₇ , T ₁₄₉ or Q ₂₈ ,
It will be taken out through T ₁₅₀ . and,
These pulses P ₁ and P ₂ are used in the first phase detection circuit 5 of FIG.
It is guided by.

Note that the gate circuit 4 for the horizontal synchronizing pulse HP explained in FIG. 1 is composed of _Q11 to _Q21 , which will be described later.

Next, the output of F ₂ of the frequency dividing circuit 8 is Q ₇ , Q ₈
The Q output of F ₃ is inverted at Q ₁₁ and the output of F ₄ is inverted at Q ₉ and Q ₁₀ and guided to point A. Therefore, a pulse PA corresponding to the logical product of the outputs of F ₂ , F ₃ , and F ₄ (hereinafter, such a logical product will be expressed as ₂ , ₃ , and ₄ ) will appear at point A. . On the other hand, the output of F ₅ is inverted by Q ₂₅ and Q ₂₆ and guided to point B, where it is ANDed with the previous pulse at point A inverted by Q ₁₅ . Therefore, at point B, a pulse PB corresponding to ₂ , ₃ , ₄ , and ₅ appears, and this pulse passes through Q ₂₉ or Q ₂₉ and Q _30.
It is guided by the base of Q ₃₁ and Q ₃₂ .

On the other hand, _the horizontal flyback pulse FP taken out from the horizontal output circuit ₁₃ in FIG.
After being shaped by T ₁₄₂ and Q ₂ , the above
It is guided by the bases of Q ₃₁ and Q ₃₂ .

Therefore, at the base of Q ₃₁ , pulses P ₃ and P ₄ corresponding to the logical product of the inverted output of the pulse at point B and the flyback pulse FP or the logical product of the pulse at point B and the flyback pulse FP appear, Each of these pulses is extracted through Q ₃₁ , T ₁₅₁ or Q ₃₂ , T ₁₅₂ . Then, both pulses P ₃ and P ₄ are the third pulse.
The signal is guided to the second phase detection circuit 9 shown in the figure.

Further, the output of F ₄ of the frequency dividing circuit 8 is inverted at Q ₉ and guided to point C, and the Q output of F ₃ is inverted at Q ₁₁
and _Q12 , and the Q output of _F5 is inverted at _Q24 and guided to point C. Therefore, at point C,
A pulse _P5 corresponding to _F4 , _F3, and ₅ appears, and this pulse _P5 is led to the variable phase shift circuit 11 of FIG. 3 through _Q13 and _Q14 .

Next, in FIG. 3, the first phase detection circuit 5
are transistors T ₂₁₉ and T ₂₂₀ to which the aforementioned pulses P ₁ and P ₂ taken out from T ₁₄₉ and T ₁₅₀ in FIG. _T216 ～
The main elements include a transistor T ₂₁₈ and a transistor T ₂₂₂ for switching detection sensitivity. This first phase detection circuit 5 is equipped with capacitors C ₂ and C ₃ and a resistor R ₃ .
A first low-pass filter 6 consisting of
It is designed to be applied as a control voltage.

Similarly, the second phase detection circuit 9 is configured as shown in FIG.
Transistors T ₂₃₅ , to _which the pulses P ₃ and P ₄ taken out from T 151 and T ₁₅₂ are respectively applied to their bases;
T ₂₃₄ and transistors T ₂₃₀ to _{T 232} constituting a current mirror circuit as main elements, and this second
A second low-pass filter 10 consisting of a capacitor C ₅ and resistors R ₅ and R ₆ is connected to the phase detection circuit 9. The voltage smoothed by this filter 10 is applied to the base of the rightmost transistor _T227 of the variable multiphase circuit 11, which will be described later.

Note that T ₁₆₆ and T ₁₆₈ at the right end of FIG. 3 operate as limiters that limit the potential change at point J in the second phase detection circuit 9 within a predetermined range.

On the other hand, the variable phase shift circuit 11 includes a transistor T ₂₂₁ to which the above-mentioned pulse _{P 5} extracted from Q ₁₄ in FIG _. A transistor T ₂₂₃ that switches charging and discharging of the capacitor C ₄ that creates a sawtooth voltage, and a sawtooth voltage appearing at the emitter of this T ₂₂₃ and the second low-pass filter 10
The main elements are transistors T ₂₂₄ to _{T 227} , which constitute a comparison circuit with the DC voltage obtained from the DC voltage, and transistors T ₂₂₈ and T ₂₂₉ which take out the output pulse of the comparison circuit and guide it to the horizontal trigger circuit 12 .

In addition, the H killer circuit 14 is connected to the terminal 15 in FIG.
The horizontal synchronizing pulse HP of positive polarity from
Transistors T 184 , T ₁₈₅ to which the AND output (H point) of the burst gate pulse GP (see Figure 4) created at Q ₃ to Q ₆ and T ₁₃₇ inverted at T ₁₄₆ is applied to the _base . and a transistor cascade-connected to this T ₁₈₅ to which the horizontal flyback pulse FP from terminal 16 in Figure 2 is applied to the base.
T ₁₈₆ and a transistor that forms a comparison circuit between the voltage obtained by smoothing the pulse obtained at the collector of T ₁₈₅ mentioned above with capacitor C ₁ and resistor R ₁ and a constant DC voltage.
The main elements are transistors T ₁₈₉ to T ₁₉₄ and switching transistors T ₁₉₅ to _{T 197} that respond to the output voltage of the comparison circuit. The switching transistor T ₁₉₅ is connected to the base common connection point of Q ₂₁ and Q ₂₂ in FIG. 2 for switching between operation and non-operation of the gate circuit. Further, T ₁₉₆ is connected to the base of T ₂₂₂ for switching the sensitivity of the first phase detection circuit 5. Furthermore, T ₁₉₇ connects the resistor R ₃ ' to a capacitor for switching the time constant of the first low-pass filter 6.
It is designed to be connected between the connection point between C ₂ and resistor R ₃ and the ground point.

As mentioned above, the reason why the horizontal synchronization pulse HP is gated with the inverted output of the burst gate pulse GP and guided to the H killer circuit is to prevent the H killer circuit from malfunctioning due to noise appearing in the back porch of the horizontal synchronization signal. This is to prevent

One embodiment of the present invention is constructed as described above, and its operation will be explained next.

() AFC operation T ₂₁₉ and T ₂₂₀ of the first phase detection circuit 5 are as shown in Fig. 2.
When the pulses P ₁ and P ₂ from T ₁₄₉ and T ₁₅₀ are not applied, they are off, and only when they are applied, they are turned on and collector currents flow respectively. At this time, since T ₂₁₆ to _{T 218} constitute a current mirror circuit, if the magnitude of the collector current of T ₂₁₉ is i, then the same magnitude of current i also exists in T ₂₁₆ .
flows.

Here, each pulse width τ of the above pulses P ₁ and P _2
1 , τ ₂ is a state in which the fall of the 1/32 frequency-divided output of the frequency divider circuit 8 (Q output of _F5 ) corresponds to the exact center of the horizontal synchronizing pulse HP, as shown in Figure 4. That is, in the synchronous state, τ ₁ = τ ₂ , and when the phase of the frequency-divided output shifts from this state, τ ₁ <τ ₂ depending on whether it shifts to the left or right in FIG.
(in case of left direction) or τ ₁ >τ ₂ (in case of right direction).

Therefore, the capacitors C ₂ and C ₃ of the first phase detection circuit 5 have a current amount (i×τ
₁ ) and the amount of current flowing out from this point I (i×τ ₂ )
Since the battery is charged or discharged by the amount corresponding to the difference between
VCO7 is controlled. In the synchronous state, τ ₁ =τ ₂ , that is, the above-mentioned two current amounts are equal, so the potential at point I is held at a constant value, and the AFC system is in a stable state.

() APC operation The operation of the second phase detection circuit 9 is substantially the same as that of the first phase detection circuit 5 described above. Therefore, this second
The potential at point J of the phase detection circuit 9 is as shown in FIG.
The pulse width τ ₃ , τ _{4 of the pulses P 3 , P 4 ( see} FIG. 4) extracted from T ₁₅₁ , T ₁₅₂ (see FIG. 4) is the difference between the horizontal flyback pulse FP and the pulse PB generated at point B in the frequency dividing circuit 8. It will rise or fall depending on the phase difference, and the base potential of T ₂₂₇ of the variable phase shift circuit 11 will change depending on the potential at the J point.

On the other hand, T ₂₂₁ of the variable phase shift circuit 11 is shown in Fig. 2.
It turns on only when the pulse appearing at the collector of Q ₁₄ , that is, the pulse Ps located in the center of the horizontal scanning period Ts (see Figure 4) arrives, and this T ₂₂₁
T ₂₂₃ also turns on when it turns on. Therefore, the capacitor C ₄ for creating the sawtooth voltage is charged with the power supply voltage (+Vcc) via the resistor R ₄ when T ₂₂₃ is off, and discharged when T ₂₂₃ is on. This generates a sawtooth voltage like VC in FIG. 4 at the emitter of T ₂₂₃ , which is applied to the base of T ₂₂₄ .

Therefore, T ₂₂₄ and T ₂₂₅ of the phase shift circuit 11
is on only during the period when the sawtooth wave voltage VC exceeds the voltage at point J of the second phase detection circuit 9 applied to the base of T ₂₂₇ , and when T ₂₂₅ is turned on,
T ₂₂₈ turns on. As a result, T ₂₂₉ is also turned on and current flows through the horizontal trigger circuit 12, causing the horizontal trigger circuit 12 to be activated. That is, the variable phase shift circuit 11 determines the activation timing of the horizontal trigger circuit 12 by turning on _T229 . Therefore, if the phase of the horizontal flyback pulse FP and the output pulse PB of the frequency divider circuit 8 deviate from each other, the base potential of _T227 changes, thereby changing the startup timing mentioned above. . In the synchronous state, the base potential of _T227 is maintained at a level approximately 1/2 of the sawtooth wave voltage VC, and the APC operation becomes stable.

() H killer operation The base of T ₁₈₆ of the H killer circuit 14 receives a positive horizontal flyback pulse from Q ₂ as described above.
Since FP is applied, this T ₁₈₆ is turned off only during that flybutter pulse, thereby turning off T ₁₈₅ and turning on T ₁₈₇ . on the other hand,
Burst gate pulse at the base of T ₁₈₄ and T ₁₈₅
A horizontal synchronization pulse HP gated with the inverse of GP is applied from T ₁₄₆ (point H). Therefore, T ₁₈₄ and T 187 are simultaneously turned on only during the period _{when both the pulses HP and FP coincide in time, and therefore, T 188 is} turned on only during this period, and a charging current flows to the capacitor C ₁ . this capacitor
C ₁ is discharged through resistor R ₁ , but in the synchronized state, the coincidence of both pulses HP and FP is repeated, so the base potential of T ₁₈₉ rises, and the base potential of T ₁₉₀ , which is held at a constant value, increases. The potential will be exceeded. Then, T ₁₈₉ turns on and T ₁₉₄ also turns on, thereby turning on each of the switching transistors T ₁₉₅ to _{T 197} .

When T ₁₉₅ of the switching transistor is turned on, Q ₂₀ in the gate circuit 4 in FIG.
Since the base of Q ₂₁ is grounded, this Q ₂₀ , Q ₂₁
The respective collectors (point D) (point E) become high level. Therefore, the Q output led from F ₃ of frequency divider circuit 8 to point D through Q ₁₁ and Q ₁₂ is
The Q output applied to the base of Q ₁₆ and led from F ₄ to point E is applied to the base of Q ₁₈ . Therefore, _a pulse P ₆ corresponding to F ₃ and F ₄ appears at point F, and _a pulse P ₇ corresponding to ₃ and ₄ appears at point G. 4) and the horizontal synchronizing pulse HP passed through Q ₂₂ will be ANDed at the collector of Q ₂₂ . This means that the aforementioned pulses P ₁ and P ₂ guided to the first phase detection circuit 5 are gated, and therefore, the video input signal explained in FIG. 1 is gated.
This eliminates the malfunction of the AFC circuit caused by the sink.

Note that T ₁₈₆ is turned on during periods other than the horizontal flyback period, so if noise is applied to T ₁₈₄ and T ₁₈₅ at this time, T ₁₈₅ is turned on by the noise. Therefore, capacitor C ₁ has T ₁₈₅ ,
It will discharge through T ₁₈₆ . Therefore, even if noise is mixed into the horizontal synchronization pulse HP,
This noise prevents the H killer from malfunctioning.

Further, when the switching transistor T ₁₉₆ is turned on, T ₂₂₂ in the first phase detection circuit 5 is turned off, so that R ₂₅₀ connected in parallel with R ₂₅₁ is electrically disconnected. For this reason,
The emitter load resistance of T ₂₁₉ and T ₂₂₀ increases,
Therefore, in the synchronous state, the current flowing through T ₂₁₆ and T ₂₁₉ is smaller than in the asynchronous state. This means that the detection sensitivity in the synchronized state is lower, which eliminates malfunctions of the AFC circuit due to noise and the like.

Further, when the switching transistor T ₁₉₇ is turned on, R ₃ ' is connected in parallel to R ₃ of the first low-pass filter 6. Therefore, the capacitance of capacitor C ₂ is apparently larger than in the asynchronous state, and therefore I
Potential fluctuations at points become smaller. That is, this is the first
This means that the time constant of the low-pass filter 6 becomes larger in the synchronized state, and this eliminates the AFC circuit's response to noise and the like in the case of a weak electric field.

As explained above, the present invention controls the frequency of the horizontal oscillator using the horizontal synchronization signal as the reference signal.
In a horizontal synchronization circuit equipped with an AFC (or APC) circuit, a circuit is provided to detect the phase coincidence between the horizontal synchronization signal and the horizontal flyback pulse, and when this detection circuit detects phase coincidence, the horizontal synchronization Create a gate pulse with a pulse width that includes the signal period,
The horizontal synchronization signal gated with this pulse is
Since the signal is supplied to the AFC (APC) circuit, it is possible to eliminate malfunctions of the horizontal synchronization circuit when video-in-sync occurs due to transmission distortion of the received television signal.

Furthermore, when the present invention is applied to a horizontal synchronization circuit in which the oscillation frequency of the oscillator is selected to be sufficiently higher than the horizontal frequency, and the oscillation output is stepped down to the horizontal frequency by a frequency dividing circuit, the above-mentioned gate pulse is It can be easily created using the frequency divider circuit described above, and is suitable for converting a horizontal synchronization circuit into an IC.

Note that although the above description has been made regarding the case of a horizontal synchronous circuit provided by connecting two AFC circuits and APC circuits, the present invention can also be applied to the case of a horizontal synchronous circuit composed of a single AFC or APC circuit. will be easily understood from the explanation so far.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a horizontal synchronization circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing details of one embodiment thereof, and FIG. 4 is a diagram for explaining the operation of FIG. It is a time chart. 1 ...Horizontal AFC circuit, 2 ...Horizontal APC circuit, 3 ...
Horizontal deflection section, 14...H killer circuit.

Claims (1)

[Claims] 1. In a horizontal synchronization circuit including a frequency control circuit that controls the frequency of a horizontal oscillator using a horizontal synchronization signal as a reference signal, a circuit for detecting phase coincidence between a horizontal synchronization signal and a horizontal flyback pulse. established,
When phase matching is detected by this detection circuit,
A horizontal synchronization circuit characterized in that a gate pulse having a pulse width including a horizontal synchronization signal period is created, and the horizontal synchronization signal is gated with this pulse and supplied to the frequency control circuit. 2. The frequency control circuit has a frequency dividing circuit that steps down the output of the oscillator that oscillates at a frequency sufficiently higher than the horizontal frequency to the horizontal frequency, and the gate pulse is derived from the frequency dividing circuit. Horizontal synchronous circuit according to item 1.